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74741-169LF Amphenol FCi Board Connector, 30 Contact(s), 5 Row(s), Male, Straight, 0.079 inch Pitch, Press Fit Terminal, Locking, Plug, LEAD FREE visit Digikey
74741-101LF Amphenol FCi Board Connector, 30 Contact(s), 5 Row(s), Male, Straight, 0.079 inch Pitch, Press Fit Terminal, Locking, Plug, LEAD FREE visit Digikey
74741-172LF Amphenol FCi Board Connector, 30 Contact(s), 5 Row(s), Male, Straight, 0.079 inch Pitch, Press Fit Terminal, Locking, Plug, LEAD FREE visit Digikey
74743-101LF Amphenol FCi Board Connector, 120 Contact(s), 5 Row(s), Male, Straight, 0.079 inch Pitch, Solder Terminal, Locking, LEAD FREE visit Digikey
74741-163LF Amphenol FCi Board Connector, 30 Contact(s), 5 Row(s), Male, Straight, 0.079 inch Pitch, Press Fit Terminal, Locking, Receptacle, LEAD FREE visit Digikey
74742-107LF Amphenol FCi Board Connector, 60 Contact(s), 5 Row(s), Male, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Plug, LEAD FREE visit Digikey

pin DIAGRAM OF IC 7474

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: delay time for reliable operation. T Y PE 7474 74L S 74A 74S 74 NOTE: T Y P IC A L f , AX 25M H z 33M , 7474, LS74A, S74 LOGIC DIAGRAM MODE SELECT - FUNCTION TABLE IN PU TS O P E R A T IN G M O D E , Signetics 7474, LS74A, S74 Flip-Flops Dual D-Type Flip-Flop Product Specification Logic , e t (R D) are asynchro nous active-LO W inputs and operate independently of the Clock input. Infor m ation on the D ata (D) input is trans ferred to th e Q output on th e LO W -toH IG H transition of the -
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ic 7474 pin diagram 7474 ic pin configuration IC 7474 pin configuration pin IC 7474 logic ic 7474 pin diagram 74s74n 7474N 74S74N N741S 1N916 1N3064
Abstract: Inspection machines 8. 22 pin dual-in-line package (CERDIP) Block Diagram SHARP 452 CCD Linear , diagram of ( l) a r e a + 12 V Ri = lk f i C, = 5 0 0 p F CK Q D Q L 1 I ( System Configuration , IC l IC 2. 5.6 IC 3 IC4 IC 7. 8.9 SN 74132 SN 74107 SN 7404 SN 7474 SN 74161 OS Vss NC NC Vss , CCD Linear Image Sensor LZ2019 LZ2019 Description 2048-bit CCD Linear Image Sensor Pin , . Output non-uniformity ± 10% of Vqut MAX 3. 2048 photoelements on a single chip ; Photo ele ment size 14 -
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14 pin ic 7404 sn 7404 n ic diagram pin configuration of ic 7404 7404 ic diagram ic 7474 with timing diagram 7404 ic pin configuration
Abstract: to facsimile machines, optical character readers, and Inspection machines 8. 22 pin dual-in-line package (CERDIP) â  Block Diagram LZ2019 Pin Connections 452 SHARP» SHARP ELEK/ MELEC DIV 1SE 0 I 0100710 000157b Ml CCD Linear Image Sensor 1SE O I 0100710 0001575 ¿J T-41-55 LZ2019 Pin Description Pin , ' OS' J\ ( ti>40ns t5>10ns Enlarged diagram of (l)area System Configuration Example lkn -y^i DO-H , one output amplifier. â  Features 1. Dynamic range 1000 TPY. 2. Output non-uniformity ±10% of Vout -
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CI 7474 IC 7474 ic 74132 pin DIAGRAM OF IC 7404 CI 74107 pin configuration of 7474 ic L12-1-2
Abstract: (Each Half) INPUT @ tn D L H OUTPUTS @ tn + 1 IO O L H PIN PKGS Plastic DIP (P) C eram ic DIP (D , NATIONAL SENICOND -CLOGIO D2E D | LSDllES D0b371S 2 | T-46-07-09 74 CO NNECTIO N DIAGRAM S PINO UT A 54/7474 54H/74H74 54S/74S74 54LS/74LS74 DUAL D-TYPE POSITIVE EDGETRIG GERED FLIP-FLOP , entary (Q, Q) outputs. Inform ation at the input is transferred to the outputs on the positive edge of , tly related to the transition tim e of the positive going pulse. A fter the Clock Pulse input -
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74LS74 truth table 7474PC 74LS74PC DE flip-flop 7474 pin diagram of 74ls74 logic diagram of ic 7474 5474DM 54H74DM 54S74DM 54LS74DM 54S74FM 54/74H
Abstract: 74 C O N N E C T IO N DIAGRAM S P IN O U T A 54/7474 < ? / / 6 ' \/54H/74H74 © t f e. j w w , Inputs (Active LOW) D irect Set Inputs (Active LOW) Outputs LO G IC DIAGRAM (one half shown) D C C , positive edge of the clo ck pulse. C lo ck trig gering occu rs at a voltage level of the clo ck pulse and is not directly related to the transition time of the positive going pulse. After the C lo c k P ulse , be transferred to the outputs until the next rising edge of the C lo ck Pulse input. P IN O U T B -
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F7474PC 74ls74d 7474 pin out diagram 74H74D IC 74LS74 FOR IC 7474 4S/74S74 34LS/74LS74 54/74S 54/74LS
Abstract: . Phase Input: The phase input terminal, pin 18, controls the direction of the current through the motor , terminal (pin 11) provides a means of continuously varying the cur­ rent for situations requiring , determined by the reference voltage together with the value of the external sense resistor Rs (pin 16). , until a current reverse command is given. By reversing the logic level of the phase input (pin 8 , Schottky Commutating Diodes Wide Range of Current Control 5-1000mA Wide Voltage Range 10-45V Designed -
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UC1717 UC3717 UC3717S UC3717N UC1717J UC1717SP
Abstract: JEDEC standard pin configuration - 32-pin PDIP package - 32-pin PLCC package The M8720 is a , 27C020, with the added advantages of electrical erasability and onboard 12.75 volts MTP programmability , both DIP and surface mount packages. The DIP package is a 32-pin molded dual-in-line package. The surface mount package is a 32-pin PLCC package. Package & Pin Configurations A17 PGM# 32L PDIP , Laboratories Inc. M8720 : 2Mbit(256Kx8) MTP Flash Memory Block Diagram A9 Figure 1 - ALi M8720 2Mbit Acer Laboratories
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pin diagram of ic 6116 ACER LABORATORIES INC flash 32 Pin PLCC 2mbit Acer Laboratories EPROM 27020 features of ic 7474 M8720BRF02
Abstract: , this pin is an input â'˜MODEâ'™ for selecting the direction of pins 20 & 21. when MODE is set high , . This is a bidirectional pin. During power up, this pin is an input for selecting the direction of pin , ), the input selection is latched internally and this pin becomes a buffered output of the crystal , functions in this device (see Pin description, Page 2). During power-up of the device, these pins are in , Jumperless frequency selection - enable/disable each output pin - mode as tri-state, test, or normal Power International Microcircuits
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ALI m1541 ALI chipset M1541 ALI m1541 a1 INTERNAL DIAGRAM OF IC 7474 SG748 ALI-M1541 M1541 IMISG748CYB SG748CYB
Abstract: are stopped in low state putting the IC in shutdown (static) mode. This is a bidirectional pin. During power up, this pin is an input for selecting the direction of pin 15. (see page1,and app note on p.12). , and this pin becomes a buffered output of the crystal. This is a bidirectional pin. During power up , internal pin capacitance of 36 pF, Load to the crystal is therefore = 18.0 pF the total parasitic , functions in this device (see Pin description, Page 2). During power-up of the device, these pins are in International Microcircuits
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M1541 a1 PCI 6601 IMISG748 REF/SW15
Abstract: direction of pin^ . &18. when MODE is set high (default, internal pull-up) tlk · >bits are SDJ|Alvi(10:11 , direction of pin 15. (see pagel,and app note on p. 11). When the power reaches the rail(see fig.1, page 4), the input selection is latched internally and this pin becomes a buffered output of the crystal. This , Programmable registers featuring: - Jum perless frequency selection - enable/disable each output pin - mode as , Capacitors 48-pin SSOP package S p rea d S p e c tru m T e c h n o lo g y fo r EMI re d i tion S2 0 0 0 0 1 -
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HM 9820 internal circuit of ic 7474 SG750 AU-M1541 IMISG750 IMISG750CYB 750CYB
Abstract: is a bidirectional pin. During power up, this pin is an input `MODE' for selecting the direction of , the direction of pin 15. (see page1,and app note on p.11). When the power reaches the rail(see fig.1, page 4), the input selection is latched internally and this pin becomes a buffered output of the , the PWR_DWN# pin is activated. Following the acknowledge of the Address Byte (D2), two additional , internal pin capacitance of 36 pF, Load to the crystal is therefore = 18.0 pF the total parasitic International Microcircuits
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of IC 7474 in file external DIAGRAM OF IC 7474 L 4959 alim1541 48MHZ SG750CYB
Abstract: power up, this pin is an input `MODE' for selecting the direction of pins 17 & 18. when MODE is set , buffers are stopped in low state putting the IC in shutdown mode. This is a bidirectional pin. During power up, this pin is an input for selecting the direction of pin 15. (see page1,and app note on p.11). , pin becomes a buffered output of the crystal. This is a bidirectional pin. During power up, this pin , only on true power up, and not when the PWR_DWN# pin is activated. Following the acknowledge of the International Microcircuits
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Abstract: Diode Driver Differential Line Driver PIN Diode Driver Level Shifting Driver FUNCTIONAL DIAGRAM V DD , designed so the rising edge of one output crosses the 50% point of the transition within 5 ns of the other , speed-up capacitors. ORDERING INFORMATION Part No. TC430C PA TC430IJA TC430M JA Package 8-Pin Plastic 8-Pin CerDIP 8-Pin CerDIP Temperature Range 0 °C to +70°C - 2 5 ° C t o +85°C - 55°C to + 1 25°C PIN CONFIGURATION d ig ita l r r GROUND INPUT [ 2 LL TC430 T ] nc 3 »0 1 © VssE n -
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teledyne tsc QGD73 Q0073 74S74
Abstract: . external IC's but suffers in performance due to the necessity of the processor to service the F01771 every , Sector ~ector 1-128 "7 gap 2 Cyclic (17 Number U'flytn Hedundancy of lero's (flO of Check ·(CRC) Datd Data Adcll"';S' Bytes) Data .gap 3 Data 1 1 1.1 1 1 0 0 , Data Address Mark Introduction The FD 1771 is a MOS/LSI device that performs the function of interfacing a processor to a' flexible (Floppy) diskette drive. This single chip replaces nearly 80% of the -
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pin DIAGRAM OF IC 7474 d flip flop western digital FD1771 ic D flip flop 7474 fd1771 74ls161 counter floppy disk Stepping Motors connection FD1771 D1771
Abstract: VCC and GND w ill have a resistor of 10k£2± 5% for static burn-in 2. Each pin except VCC and GND w , ,1 9 ,2 0 NOTE: Each pin except VCC and GND w ill have a resistor of 47Kn f 5% for irradiation , 1992 Features Pinouts - r - S L r C T \ 20 PIN CERAMIC DUAL-IN-LINE MIL-STD , Max - VIH = VCC/2 Min gnd 20 PIN CERAMIC FLAT PACK MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD , . This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS244MS is -
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CDIP2-T20
Abstract: , 10,19 NOTES: 1. Each pin except VCC and GND will have a resistor of 10kii ± 5% for static burn-in 2. Each pin except VCC and GND will have a resistor of 680kn ± 5% for dynamic burn-in TABLE 9 , , 6, 8 ,1 1 ,1 3 ,1 5 ,1 7 ,1 9 ,2 0 NOTE: Each pin except VCC and GND will have a resistor of , ) 20 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C TOP VIEW â'¢ Dose , HCTS244MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of -
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Abstract: except VCC and GND will have a resistor of 10kn ± 5% for static burn-in 2. Each pin except VCC and GND , , Tri-State Pinouts 20 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C TOP VIEW , 2A1 ÏÜ 1Y 3 Ï 3 2A0 E 2Y2 [T 1A 2Ü 2Y1 E 1A3E 2YÛ E GND [10 20 PIN CERAMIC FLAT PACK , HCTS244MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of , : These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling -
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or ic 7473 CMOS pin diagram for IC 7473 circuit diagram for IC 7473 ic 7472 pin diagram 7474 truth table ic 7473 with timing diagram
Abstract: diagram of the 82303 that will facilitate understanding of the part. Note that the 82304 and 82303 ,   Integrated Card Setup Port (96H) B 100.pin Plastic Quad Flat Package The 82303 Local Channel Support , reduce system cost, design effort, and form factor constraints by replacing 50 IC devices in an , latches, and provides signals in support of system setup functions. PDABCPD« P103RD# * P103W R , ­ tem design to stay clear of directly exposing a VLSI component to an external connector.) The -
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82303 P101RD M60STR
Abstract: l l l l 8051 instruction set compatible 8 bit microcontroller 8051/8052 compatible pin out Complete static design, wide range of operation frequency from 1 ~ 40 MHz Large on-chip memory ² 64K , programming 44 pin PLCC or QFP package General Description The M6759 is an 8032/8052 instruction , the feasibility for general control systems in a variety of applications. Further more, the firmware , the timers of the 80C51). d) a 16-bit timer (identical to the Timer 2 of the 8052). e) a Acer Laboratories
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ALi M6759 A1 ALI M6759 M6759 A1 8052 basic e1 acer 1830-B 6759DS02
Abstract: compatible 8 bit microcontroller 8051/8052 compatible pin out Complete static design, wide range of , consumption ROM Code Protection 4.5V~5.5V operation voltage, 12V programming 44 pin PLCC or QFP package , in a variety of applications. Further more, the firmware can be protected by user-defined security , /O ports, two 16-bit timer/event counters (identical to the timers of the 80C51). d) a 16-bit timer (identical to the Timer 2 of the 8052). e) a multi-source two-priority-level nested interrupt structure. f -
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7474 pin configuration 7474 pin diagram 8052 pin structure 8052 micro controller mtp 26 8051 micro controller
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