XC4000E XC4000 MIL-PRF-38535 XC4005E XC4010E XC4013E XC4025E PG156 CB164 PG191 - Datasheet Archive

 

November 21, 1997 (Version 1.3) • System featured Field-Programmable Gate Arrays - Select-RAM™ memory:

 

HXILINX November 21, 1997 (Version 1.3) • System featured Field-Programmable Gate Arrays - Select-RAMâ„¢ memory: on-chip ultra-fast RAM with - synchronous write option - dual-port RAM option - Abundant flip-flops - Flexible function generators - Dedicated high-speed carry logic - Wide edge decoders on each edge - Hierarchy of interconnect lines - Internal 3-state bus capability - 8 global low-skew clock or signal distribution networks • System Performance beyond 60 MHz • Flexible Array Architecture • Low Power Segmented Routing Architecture • Systems-Oriented Features - IEEE 1149.1-compatible boundary scan logic support - Individually programmable output slew rate - Programmable input pull-up or pull-down resistors - 12-mA sink current per XC4000E XC4000E output • Configured by Loading Binary File - Unlimited reprogrammability • Readback Capability Table 1 : XC4000E XC4000E Field Programmable Gate Arrays Product Specification - Program verification - Internal node observability • Backward Compatible with XC4000 XC4000 Devices • Development System runs on most common computer platforms - Interfaces to popular design environments - Fully automatic mapping, placement and routing - Interactive design editor for design optimization • Available in class Q fully compliant QML and Military temperature range only - Certified to MIL-PRF-38535 MIL-PRF-38535, appendix A QML (Qualified Manufacturers Listing) Xîlinx High-Reliability XC4000E XC4000E family is supplied under the following standard microcircuit drawings (SMDs): XC4005E XC4005E 5962-97522 XC4010E XC4010E 5962-97523 XC4013E XC4013E 5962-97524 XC4025E XC4025E 5962-97525 For more information contact DSCC (Defense Supply Center Columbus) Columbus, Ohio. Device Max. Logic Gates (No RAM) Max. RAM Bits (No Logic) Typical Gate Range (Logic and RAM)* CLB Matrix Total CLBs Number of Flip-Flops Max. Decode Inputs per side Max. User I/O Packages XC4005E XC4005E 5,000 6,272 3,000 - 9,000 14x14 196 616 42 112 PG156 PG156, CB164 CB164 XC4010E XC4010E 10,000 12,800 7,000 - 20,000 20 x20 400 1,120 60 160 PG191 PG191, CB196 CB196 XC4013E XC4013E 13,000 18,432 10,000 -30,000 24x24 576 1,536 72 192 PG223 PG223, CB228 CB228 XC4025E XC4025E 25,000 32,768 15,000 -45,000 32 x32 1,024 2,560 96 256 PG299 PG299, CB228 CB228 * Max values of Typical Gate Range include 20-30% of CLBs used as RAM. November 21, 1997 (Version 1.3) 8-11 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays XC4000E XC4000E Absolute Maximum Ratings Symbol Description Value Units Vcc Supply voltage relative to GND -0.5 to +7.0 V V,n Input voltage relative to GND (Note 1) -0.5 to Vcc +0.5 V VTS Voltage applied to 3-state output (Note 1 ) -0.5 to Vcc +0.5 V tstg Storage temperature (ambient) -65 to +150 °c tsol Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 °c Tj Junction temperature Ceramic packages + 150 °c Note 1: Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this over- or undershoot lasts less than 20 ns. Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. XC4000E XC4000E Recommended Operating Conditions Symbol Description Min Max Units Vcc Supply voltage relative to GND, Tc = -55°C to +125°C 4.5 5.5 V V|h High-level input voltage TTL inputs 2.0 Vcc V V|l Low-level input voltage TTL inputs 0 0.8 V Tin Input signal transition time 250 ns Note: At case temperatures above those listed as Recommended Operating Conditions, all delay parameters increase by 0.35% per °C. Input and output Measurement thresholds are: 1,5V for TTL and 2.5V for CMOS. All specifications are subject to change without notice. 8-12 November 21, 1997 (Version 1.3) flXIUNX XC4000E XC4000E DC Characteristics Over Operating Conditions Symbol Description Min Max Units VoH High-level output voltage @ lOH = -4.0mA, Vcc min TTL outputs 2.4 V Vol Low-level output voltage @ lOL = 12.0mA, Vcc min (Note 1 ) TTL outputs 0.4 V 'cco Quiescent FPGA supply current (Note 2) 50 mA II Input or output leakage current -10 +10 |iA cin Input capacitance (sample tested) 16 PF Irin* Pad pull-up (when selected) @ V|N = 0V (sample tested) -0.02 -0.25 mA 'rll* Horizontal Longline pull-up (when selected) @ logic Low 0.2 2.5 mA Note 1: With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins. Note 2: With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA configured with the development system Tie option. * Characterized Only. XC4000E XC4000E Global Buffer Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature) Speed Grade -4 Description Symbol Device Max Units From pad through tpg XC4005E XC4005E 7.0 ns Primary buffer, XC4010E XC4010E 11.0 ns to any clock K XC4013E XC4013E 11.5 ns XC4025E XC4025E 12.5 ns From pad through Tsg XC4005E XC4005E 7.5 ns Secondary buffer, XC4010E XC4010E 11.5 ns to any clock K XC4013E XC4013E 12.0 ns XC4025E XC4025E 13.0 ns November 21, 1997 (Version 1.3) 8-13 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays XC4000E XC4000E Horizontal Longline Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E XC4000E devices unless otherwise noted. The following guidelines reflect worst-case values over the recommended operating conditions. Speed Grade -4 Units Description Symbol Device Max TBUF driving a Horizontal Longline (LL): I going High or Low to LL going High or Low, while T is Low. Buffer is constantly active. (Notel) T|Oi XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E 5.0 8.0 9.0 11.0 ns ns ns ns I going Low to LL going from resistive pull-up High to active Low. TBUF configured as open-drain. (Notel) T|02 XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E 6.0 10.5 11.0 12.0 ns ns ns ns T going Low to LL going from resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with 1 = Low. (Notel) ton XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E 7.0 8.5 8.7 11.0 ns ns ns ns T going High to TBUF going inactive, not driving LL toff XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E 1.8 3.0 3.5 4.0 ns ns ns ns T going High to LL going from Low to High, pulled up by a single resistor. (Note 1) Tpus XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E 23.0 29.0 32.0 42.0 ns ns ns ns T going High to LL going from Low to High, pulled up by two resistors. (Notel) Tpuf XC4005E XC4005E XC4010E XC4010E XC4013E XC4013E XC4025E XC4025E 10.0 13.5 15.0 18.0 ns ns ns ns Note 1 : These values include a minimum load. Use the static timing analyzer to determine the delay for each destination. 8-14 November 21, 1997 (Version 1.3) flXIUNX XC4000E XC4000E Wide Decoder Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E XC4000E devices unless otherwise noted. The following guidelines reflect worst-case values over the recommended operating conditions. Speed Grade -4 Description Symbol Device Max Units Full length, both pull-ups, twaf XC4005E XC4005E 9.5 ns inputs from IOB l-pins XC4010E XC4010E 15.0 ns XC4013E XC4013E 16.0 ns XC4025E XC4025E 18.0 ns Full length, both pull-ups, twafl XC4005E XC4005E 12.5 ns inputs from internal logic XC4010E XC4010E 18.0 ns XC4013E XC4013E 19.0 ns XC4025E XC4025E 21.0 ns Half length, one pull-up, twao XC4005E XC4005E 10.5 ns inputs from IOB l-pins XC4010E XC4010E 16.0 ns XC4013E XC4013E 17.0 ns XC4025E XC4025E 19.0 ns Half length, one pull-up, Twaol XC4005E XC4005E 12.5 ns inputs from internal logic XC4010E XC4010E 18.0 ns XC4013E XC4013E 19.0 ns XC4025E XC4025E 21.0 ns Notes: These delays are specified from the decoder input to the decoder output. Fewer than the specified number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used. November 21, 1997 (Version 1.3) 8-15 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays XC4000E XC4000E CLB Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E XC4000E devices unless otherwise noted. Speed Grade 4 Unit« Description Symbol Min Max Combinatorial Delays F/G inputs to X/Y outputs Tilo 3.9 ns F/G inputs via H to X/Y outputs T|ho 5.9 ns C inputs via H to X/Y outputs thhio 4.9 ns CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Topcy 4.4 ns Add/Subtract input (F3) to COUT tascy 6.8 ns Initialization inputs (F1, F3) to COUT Tincy 2.9 ns CIN through function generators to X/Y outputs tsum 5.0 ns CIN to COUT, bypass function generators tbyp 1.0 ns Sequential Delays Clock K to outputs Q Tcko 5.0 ns Setup Time before Clock K F/G inputs Tick 4.0 ns F/G inputs via H Tihck 6.1 ns C inputs via H1 through H Thhick 5.0 ns C inputs via H2 through H thh2ck 4.8 ns C inputs via DIN tdick 3.0 ns C inputs via EC tecck 4.0 ns C inputs via S/R, going Low (inactive) Trck 4.2 ns 8-16 November 21, 1997 (Version 1.3) flXIUNX XC4000E XC4000E CLB Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-date information, use the values provided by the static timing analyzer and used in the simulator. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E XC4000E devices unless otherwise noted. Speed Grade 4 Units Description Symbol Device Min Max Hold Time after Clock K F/G inputs Tcki 0 ns F/G inputs via H C inputs via H1 through H Tckih Tckhhi 0 0 ns ns C inputs via DIN Tckdi 0 ns C inputs via EC C inputs via SR, going Low (inactive) Tckec tckr 0 0 ns ns Clock Clock High time Tch 4.5 ns Clock Low time Tcl 4.5 ns Set/Reset Direct Width (High) Delay from C inputs via S/R, going High to Q Trpw Trio 5.5 6.5 ns ns Master Set/Reset Width (High or Low) tmrw 4005E 4005E 4010E 4010E 4013E 4013E 4025E 4025E 13.0 55.0 70.0 112.0 ns ns ns ns Delay from Global Set/Reset net to Q tmrq 4005E 4005E 23.0 ns 401OE 401OE 4013E 4013E 4025E 4025E 60.0 77.0 134.0 ns ns ns November 21, 1997 (Version 1.3) 8-17 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays XC4000E XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E XC4000E devices unless otherwise noted. Single Port RAM Speed Grade 4 Units Size Symbol Min Max Write Operation Address write cycle time (clock K period) 16x2 Twcs 15.0 ns 32x1 twcts 15.0 ns Clock K pulse width (active edge) 16x2 twps 7.5 1 ms ns 32x1 twpts 7.5 1 ms ns Address setup time before clock K 16x2 tass 2.8 ns 32x1 tasts 2.8 ns Address hold time after clock K 16x2 Tahs 0 ns 32x1 tahts 0 ns DIN setup time before clock K 16x2 tdss 3.5 ns 32x1 tdsts 2.5 ns DIN hold time after clock K 16x2 tdhs 0 ns 32x1 tdhts 0 ns WE setup time before clock K 16x2 Twss 2.2 ns 32x1 Twsts 2.2 ns WE hold time after clock K 16x2 Twhs 0 ns 32x1 Twhts 0 ns Data valid after clock K 16x2 Twos 10.3 ns 32x1 twots 11.6 ns Notes: Timing for the 16x1 RAM option is identical to 16x2 RAM timing. Applicable Read timing specifications are identical to Level-Sensitive Read timing. Dual-Port RAM Speed Grade - 4 Units Size Symbol Min Max Write Operation Address write cycle time (clock K period) 16x1 twcds 15.0 ns Clock K pulse width (active edge) 16x1 twpds 7.5 1 ms ns Address setup time before clock K 16x1 tasds 2.8 ns Address hold time after clock K 16x1 tahds 0 ns DIN setup time before clock K 16x1 Tdsds 2.2 ns DIN hold time after clock K 16x1 tdhds 0 ns WE setup time before clock K 16x1 twsds 2.2 ns WE hold time after clock K 16x1 twhds 0.3 ns Data valid after clock K 16x1 twods 10.0 ns Note: Applicable Read timing specifications are identical to Level-Sensitive Read timing. 8-18 November 21, 1997 (Version 1.3) XC4000E XC4000E CLB RAM Synchronous (Edge-Triggered) Write Timing WCLK (K) WE DATA IN ADDRESS DATA OUT â- \r ' DSS y j ' WPS 1 DHS -\r AHS y )( OLD I NEW r XC4000E XC4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing WCLK (K) WE DATA IN ADDRESS DATA OUT 1 WSDS V T, 1 DSDS )C 1 ASDS )C 1 ILO 1 WODS â-  ' WPDS A- WHDS 1 DHDS £ AHDS t 1 ILO )C OLD BC November 21, 1997 (Version 1.3) 8-19 XC4000E XC4000E High-Reliability Field Programmable Gate Arrays XC4000E XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605 MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E XC4000E devices unless otherwise noted. Speed Grade 4 Units Description Size Symbol Min Max Write Operation Address write cycle time 16x2 Twc 8.0 ns 32x1 twct 8.0 ns Write Enable pulse width (High) 16x2 TWP 4.0 ns 32x1 twpt 4.0 ns Address setup time before WE 16x2 tas 2.0 ns 32x1 tast 2.0 ns Address hold time after end of WE 16x2 Tah 2.5 ns 32x1 taht 2.0 ns DIN setup time before end of WE 16x2 tds 4.0 ns 32x1 tdst 5.0 ns DIN hold time after end of WE 16x2 Tdh 2.0 ns 32x1 tdht 2.0 ns Read Operation Address read cycle time 16x2 Trc 4.5 ns 32x1 Trct 6.5 ns Data valid after address change 16x2 Tilo 3.9 ns (no Write Enable) 32x1 T|ho 5.9 ns Read Operation, Clocking Data into Flip-Flop Address setup time before clock K 16x2 tick 4.0 ns 32x1 Tihck 6.1 ns Read During Write Data valid after WE goes active (DIN stable before WE) 16x2 Two 10.0 ns 32x1 Twot 12.0 ns Data valid after DIN 16x2 tdo 9.0 ns (DIN changes during WE) 32x1 tdot 11.0 ns Read During Write, Clocking Data into Flip-Flop WE setup time before clock K 16x2 twck 8.0 ns 32x1 Twckt 9.6 ns Data setup time before clock K 16x2 tdck 7.0 ns 32x1 Tdckt 8.0 ns Note: Timing for the 16x1 RAM option is identical to 16x2 RAM timing. 8-20 November 21, 1997 (Version 1.3) flXIUNX XC4000E XC4000E CLB Level-Sensitive RAM Timing Characteristics a r 7 V. WRITE WRITE ENABLE READ WITHOUT WRITE X,Y OUTPUTS VALID -TAS - - T|LO- AA 7V - TWO- 7v_ -TWP- -TDS- -TAH- ^ REQUIRED -TDH 7 V. READ, CLOCKING DATA INTO FLIP-FLOP i"«-tick - CLOCK XQ, YQ OUTPUTS VALID (OLD) â-  TCH ' â-  TCKO â-  A/~ 7V VALID (NEW) READ DURING WRITE WRITE ENABLE DATA IN (stable during WE) X, Y OUTPUTS DATA IN (changing during WE) X, Y OUTPUTS (PREVIOUS) / ^llllf \ (OLD) READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP -TWO" T^V A_/v -TWO" N/ Ny AA" 7 v. - Too â-  AA" 7 V. WRITE ENABLE XQ, YQ OUTPUTS X Y /v. VALID (NEW) /