SH7710 ERXD03 ERXD02 ERXD01 ERXD00 ERXD13 ERXD12 ERXD11 ERXD10 ETXD10 ETXD11

D 4 These schematics are provided for reference only. For any designs based on these schematics always contact National

5 D 4 These schematics are provided for reference only. For any designs based on these schematics always contact National Semiconductor Corporation BEFORE initiating PCB manufacturing and ask for your design to be reviewed. Copyright (c) 2004 National Semiconductor Corporation. All Rights Reserved. Unpublished rights reserved under the copyright laws of the United States of America, other countries and international treaties. These schematics are provided without fee. Permission to use, copy, store, modify, disclose, transmit or distribute the schematics is granted, provided that this copyright notice must appear in any copy, modification, disclosure, transmission or distribution of the schematics. National Semiconductor Corporation retains all ownership, copyright, trade secret and proprietary rights in the schematics. THESE SCHEMATICS HAVE BEEN PROVIDED "AS IS", WITHOUT EXPRESS OR IMPLIED WARRANTY INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND NON-INFRINGEMENT. 3 2 1 Note: For Reference Only RENESAS SH7710 SH7710 RISC Microprocessor D NOTE: For dual MII devices. U1 LNKSTA0 180 179 ERXD03 ERXD03 ERXD02 ERXD02 ERXD01 ERXD01 ERXD00 ERXD00 178 175 174 173 RX-DV0 RX-CLK0 RX-ER0 172 171 170 TX-ER0 TX-CLK0 TX-EN0 C 182 MDIO0 MDC0 169 166 165 LNKSTA1 MDIO1 MDC1 ERXD13 ERXD13 ERXD12 ERXD12 ERXD11 ERXD11 ERXD10 ERXD10 ERXD[13:10] RXDV1 RXCLK1 RXER1 TXER1 TXCLK1 TXEN1 C ETXD10 ETXD10 ETXD11 ETXD11 ETXD12 ETXD12 ETXD13 ETXD13 ETXD00 ETXD00 ETXD01 ETXD01 ETXD02 ETXD02 ETXD03 ETXD03 164 163 162 161 COL0 CRS0 160 157 COL1 CRS1 LNKSTA1 154 LNKSTA2 MDIO1 MDC1 152 151 ERXD13 ERXD13 ERXD12 ERXD12 ERXD11 ERXD11 ERXD10 ERXD10 150 145 144 143 RX-DV1 RX-CLK1 RX-ER1 142 141 140 TX-ER1 TX-CLK1 TX-EN1 139 136 135 ETXD10 ETXD10 ETXD11 ETXD11 ETXD12 ETXD12 ETXD13 ETXD13 134 133 132 131 COL1 CRS1 130 129 B ETXD[13:10] MDIO2 MDC2 ERXD23 ERXD23 ERXD22 ERXD22 ERXD21 ERXD21 ERXD20 ERXD20 ERXD[23:20] RXDV2 RXCLK2 RXER2 TXER2 TXCLK2 TXEN2 ETXD20 ETXD20 ETXD21 ETXD21 ETXD22 ETXD22 ETXD23 ETXD23 ETXD[23:20] B COL2 CRS2 sh7710mii MII Connections A A Title Size C Date: 5 4 3 2 RENESAS SH7710/NSC SH7710/NSC DP83847 DP83847 App. Note Document Number CID Working Draft: CPU MII Connections Thursday, October 28, 2004 1 Sheet Rev A 1 of 3 5 4 3 2 1 Note: For Reference Only MII ETHERNET PHY 1 PA[0.4] +3.3V D2 YEL D1 GRN SPEED C4 10uF R1 5.1K R6 324 Note: Place capacitors close to pin. + PA4 ACTIVE HI D NOTE: place 0.1uF capacitors close to each power pin (14, 28. 56) on U2. See layout of reference design board for proper connections to VDD bars (57, 59, 63). PA3 C3 0.1uF PA2 C2 0.1uF PA1 C1 0.1uF PA0 SPEED LED ON for 100 Mb/s OFF for 10 Mb/s SPEED D3 RED FULL DUPLEX R7 324 +3.3V R2 5.1K D4 GRN COLLISION R8 324 D5 YEL LINK R3 5.1K R9 324 R5 5.1K D6 GRN TX R4 5.1K R10 324 D RX R11 324 C5 C-0.1U Phy Address Strap = 00001 26 27 29 30 R20 49.9 R19 49.9 R21 49.9 31 32 33 RXD_DV RXD_CLK RXD_ER 35 36 37 TXER1 TXCLK1 TXEN1 R24 49.9 43 45 42 PA0 PA1 PA2 PA3 PA4 SPEED 17 16 15 10 11 7 6 Place capacitor close to pin 14. COL CRS R23 49.9 AN_EN AN_1 AN_0 TD+ TDRD+ RD- DSPHYTER II LLP R13 49.9 +3.3V C6 0.1uF R18 49.9 C C7 0.1uF TX+ TXRX+ RX- J1 1 2 3 4 5 6 7 8 T1 PE-68515 PE-68515 TD+ TDRD+ NC1 NC2 RDNC3 NC4 NC NC SHGND1 SHGND2 SHGND3 SHGND4 9 10 11 12 13 14 CON-RJ45 CON-RJ45 RBIAS Note: Place termination resistors as close as possible to DP83847 DP83847. +3.3V R27 10K 46 X2 X1 DP83847 DP83847 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 3 RBIAS 61 55 54 53 52 51 50 47 44 34 13 12 9 8 5 4 2 1 R26 R25 54.9 10K R28 54.9 C8 0.1uF R29 75 NOTE: Place close to DP83847 DP83847 R30 R31 R32 75 75 75 B C9 58 60 62 64 65 GND GND GND GND GND RESET_N 48 49 B VDD 59 63 VDD 57 TXD_0 TXD_1 TXD_2 TXD_3 ETXD10 ETXD10 ETXD11 ETXD11 ETXD12 ETXD12 ETXD13 ETXD13 ETXD[13:10] COL1 CRS1 VDD TX_ER TX_CLK TX_EN 23 22 21 20 19 18 1 2 3 4 5 6 7 8 ERXD[13:10] RXDV1 RXCLK1 RXER1 VDD RXD_3 RXD_2 RXD_1 RXD_0 38 39 40 41 R15 49.9 R17 49.9 LED_DPLX LED_COL LED_GDLNK LED_TX LED_RX LED_SPEED 16 15 14 13 12 11 10 9 R14 49.9 R16 49.9 R22 49.9 ERXD13 ERXD13 ERXD12 ERXD12 ERXD11 ERXD11 ERXD10 ERXD10 56 MDIO MDC MDIO1 MDC1 C LNKSTA1 RX+ TX+ RXTXRXO_CT TXI_CT NC1 NC4 RXI_CT TXO_CT TPRDTPTDTPRD+ TPTD+ NC2 NC3 24 25 VDD 1.5K VDD U2 VDD R12 28 +3.3V 14 +3.3V ISLAND_GND 1500pF C_GND NOTE: All GND are system ground plane C_GND is chassis ground plane +3.3V X1 14 7 R33 Vcc OUT Oscillator GND 25 MHz (50ppm) 8 0.0 OSC-25 OSC-25 MHz A A Title Size C Date: 5 4 3 2 Renesas SH7710/NSC SH7710/NSC DP83847 DP83847 App. Note Document Number CID Working Draft: MII Ethernet PHY 1 Friday, July 09, 2004 Rev A Sheet 1 2 of 3 5 4 3 2 1 Note: For Reference Only MII ETHERNET PHY 2 PA[0.4] +3.3V D SPEED R39 324 Note: Place capacitors close to pin. + C13 10uF R34 5.1K D9 RED FULL DUPLEX COLLISION R40 324 R35 5.1K D10 GRN R41 324 D11 YEL LINK R36 5.1K PA4 D8 YEL D7 GRN NOTE: place 0.1uF capacitors close to each power pin (14, 28. 56) on U2. See layout of reference design board for proper connections to VDD bars (57, 59, 63). +3.3V ACTIVE HI PA3 C12 0.1uF PA2 C11 0.1uF PA1 C10 0.1uF PA0 SPEED LED ON for 100 Mb/s OFF for 10 Mb/s SPEED R42 324 R38 5.1K D12 GRN TX R37 5.1K R43 324 D RX R44 324 C14 C-0.1U Phy Address Strap = 00011 26 27 29 30 R53 49.9 R52 49.9 R54 49.9 31 32 33 RXD_DV RXD_CLK RXD_ER 35 36 37 TXER2 TXCLK2 TXEN2 R57 49.9 43 45 42 PA0 PA1 PA2 PA3 PA4 SPEED 17 16 15 10 11 7 6 Place capacitor close to pin 14. COL CRS R56 49.9 AN_EN AN_1 AN_0 TD+ TDRD+ RD- DSPHYTER II LLP R46 49.9 +3.3V C15 0.1uF R51 49.9 C C16 0.1uF TX+ TXRX+ RX- J2 1 2 3 4 5 6 7 8 T2 PE-68515 PE-68515 TD+ TDRD+ NC1 NC2 RDNC3 NC4 NC NC SHGND1 SHGND2 SHGND3 SHGND4 9 10 11 12 13 14 CON-RJ45 CON-RJ45 RBIAS Note: Place termination resistors as close as possible to DP83847 DP83847. +3.3V R60 10K 46 X2 X1 DP83847 DP83847 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 3 RBIAS 61 55 54 53 52 51 50 47 44 34 13 12 9 8 5 4 2 1 R59 R58 54.9 10K R61 54.9 C17 0.1uF R62 75 NOTE: Place close to DP83847 DP83847 R63 R64 R65 75 75 75 B C18 58 60 62 64 65 GND GND GND GND GND RESET_N 48 49 B VDD 59 63 VDD 57 TXD_0 TXD_1 TXD_2 TXD_3 ETXD20 ETXD20 ETXD21 ETXD21 ETXD22 ETXD22 ETXD23 ETXD23 ETXD[23:20] COL2 CRS2 VDD TX_ER TX_CLK TX_EN 23 22 21 20 19 18 1 2 3 4 5 6 7 8 ERXD[23:20] RXDV2 RXCLK2 RXER2 VDD RXD_3 RXD_2 RXD_1 RXD_0 38 39 40 41 R48 49.9 R50 49.9 LED_DPLX LED_COL LED_GDLNK LED_TX LED_RX LED_SPEED 16 15 14 13 12 11 10 9 R47 49.9 R49 49.9 R55 49.9 ERXD23 ERXD23 ERXD22 ERXD22 ERXD21 ERXD21 ERXD20 ERXD20 56 MDIO MDC MDIO2 MDC2 C LNKSTA2 RX+ TX+ RXTXRXO_CT TXI_CT NC1 NC4 RXI_CT TXO_CT TPRDTPTDTPRD+ TPTD+ NC2 NC3 24 25 VDD 1.5K VDD U3 VDD R45 28 +3.3V 14 +3.3V ISLAND_GND 1500pF C_GND NOTE: All GND are system ground plane C_GND is chassis ground plane +3.3V X2 14 7 R66 Vcc OUT Oscillator GND 25 MHz (50ppm) 8 0.0 OSC-25 OSC-25 MHz A A Title Size C Date: 5 4 3 2 Renesas SH7710/NSC SH7710/NSC DP83847 DP83847 App. Note Document Number CID Working Draft: MII Ethernet PHY 2 Friday, July 09, 2004 Rev A Sheet 1 3 of 3