CMX910 - Datasheet Archive

 

Auxiliary ADC Inputs Auxiliary DAC Outputs 5-Input MUX Aux ADC Chip-Select - DAC I Rx1 Q - ADC I Rx 2 Q - ADC - ADC - ADC Q HDLC/

 

Multiplexed Auxiliary ADC Inputs Auxiliary DAC Outputs 5-Input MUX Aux ADC Chip-Select - DAC I Rx1 Q - ADC I Rx 2 Q - ADC - ADC - ADC Q HDLC/ NRZI Encoder Message Buffer AIS Raw or FSK I Q Level Tracking I Level Tracking HDLC/ NRZI Decoder Message Buffers FSK Demod. GF(M)SK Slicer d dt Q Tx Channel GF(M)SK Slicer d dt Tx FIFO AIS Burst Rx1 FIFO AIS Raw HDLC/ NRZI Decoder Message Buffers FSK Demod. AIS Burst Rx2 FIFO AIS Raw Rx Channel 2 Internal AVDD Device Enable Port Enab 5 Enab 4 Enab 3 Enab 2 Enab 1 Enab 0 AVSS IOVDD 3.0 to 3.6 volt input Reset and Clock Control Ref. Clock Enable outputs for timed control of peripheral circuits CMX910 CMX910 Block Diagram Reset FSK Retiming Serial Clock Command Data Rx Channel 1 FSK Analogue 2V5 regulator Receive Data Expansion Chip-Select C-BUS Expansion Port Q AIS Burst GF(M)SK/FSK Modulator and Filters External FSK Mute FSK Rx Data FSK Detect FSK FIFO Slot and Sample Timer UTC Sync Slot Clock Interrupt Generator Interrupt Exp 5 Exp 4 Exp 3 Exp 2 Exp 1 Exp 0 For selection of additional C-BUS or general purpose peripherals I - DAC I Tx C-BUS Interface Differential I and Q Tx Outputs DAC RAM Special Command Interface Differential I and Q Rx Inputs 10-bit DAC Aux DACs 10-bit ADC 10-bit DAC Bias Generator Sample and Hold 10-bit DAC VBIAS MUX 10-bit DAC DVSS 10-bit DAC Digital 2V5 Regulator C-BUS Serial Interface IOVDD DVDD 3.0 to 3.6 volt Input