CHIPS/230 CHIPS/250 CHIPS/280 CHIPS/450 DS159 ISA486 256KB 82C481 82C404 CS4021 - Datasheet Archive

 

(WingineTM) High Performance 'WindowsTM Engine' Data Sheet July 1992 P R E L I M I N A R Y ® Copyright Notice Copyright

 

64200 (WingineTM) High Performance 'WindowsTM Engine' Data Sheet July 1992 P R E L I M I N A R Y ® Copyright Notice Copyright © 1991, 1992 Chips and Technologies, Inc. ALL RIGHTS RESERVED. This manual is copyrighted by Chips and Technologies, Inc. You may not reproduce, transmit, transcribe, store in a retrieval system, or translate into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, any part of this publication without the express written permission of Chips and Technologies, Inc. Restricted Rights Legend Use, duplication, or disclosure by the Government is subject to restrictions set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at 252.277-7013. Trademark Acknowledgement CHIPS and NEAT are registered trademarks of Chips and Technologies, Incorporated. CHIPS, CHIPSet, MICROCHIPS, SCAT, NEATsx, LeAPSet, LeAPSetsx, PEAK, CHIPS/230 CHIPS/230, CHIPS/250 CHIPS/250, CHIPS/280 CHIPS/280, CHIPS/450 CHIPS/450, CHIPSPak, CHIPSPort, CHIPSlink, SMARTMAP and Wingine are trademarks of Chips and Technologies, Incorporated. IBM AT, XT, PS/2, Micro Channel, Personal System/2, Enhanced Graphics Adapter, Color Graphics Adapter, Video Graphics Adapter, IBM Color Display, and IBM Monochrome Display are trademarks of International Business Machines. Hercules is a trademark of Hercules Computer Technology. MS-DOS is a trademark of Microsoft, Incorporated. MultiSync is a trademark of Nippon Electric Company (NEC). Brooktree and RAMDAC are trademarks of Brooktree Corporation. Inmos is a trademark of Inmos Corporation. TRI-STATE® is a registered trademark of National Semiconductor Corporation. Disclaimer This document is provided for the general information of the customer. Chips and Technologies, Incorporated, reserves the right to modify the information contained herein as necessary and the customer should ensure that it has the most recent revision of the data sheet. CHIPS makes no warranty for the use of its products and bears no responsibility for any errors which may appear in this document. The customer should be on notice that the field of personal computers is the subject of many patents held by different parties. Customers should ensure that they take appropriate action so that their use of the products does not infringe upon any patents. It is the policy of Chips and Technologies, Incorporated to respect the valid patent rights of third parties and not to infringe upon or assist others to infringe upon such rights. ® Chips and Technologies, Inc. 3050 Zanker Road San Jose, California 95134 Phone: 408-434-0600 Telex: 272929 CHIPS UR FAX: 408-434-6452 Title: 64200 (WingineTM) Data Sheet Publication No.: DS159 DS159 Stock No.: 010159-001 Revision No.: 0.6 ® 64200 (WingineTM ) High Performance 'WindowsTM Engine' s Cost effective WindowsTM Accelerator s Interfaces directly with X86 SX/DX/DX2 Systems s Interfaces directly with ISA486 ISA486 CHIPSet s High performance achieved via direct access frame buffer Memory Bus Architecture s Direct linear mapping of entire video memory anywhere in system memory space s Flexible video memory configurations: 8, 16, or 32-bit wide VRAM (256KB 256KB­2MB) s Supports the following display modes with 1MB of VRAM: · 8bpp up to 1024x768 (interlaced or non-I/L) · 16bpp up to 800x600 (with Sierra RAMDAC) · 24bpp up to 640x480 (with Bt484 or equiv) s Supports higher resolution display modes with 2MB VRAM: · 8bpp up to 1280x1024 (non-interlaced) · 16bpp up to 1024x768 (interlaced or non-I/L) · 24bpp up to 800x600 (non-interlaced) s Highly integrated design (non-multiplexed system bus, direct bus drive, minimum external glue logic) s All video shifting performed on-chip to allow use of low-cost VGA RAMDACs (allows video rates to 80 MHz) s Compatible with high-resolution color palette RAMDACs such as the Bt484 and TI 34075 having separate 8-bit and 32-bit parallel inputs for direct connection to VRAM serial data (allows video rates to 135 MHz) s Full VGA compatibility s Interfaces directly with the 82C481 82C481 True-Color Graphics Accelerator s Direct interface to 82C404 82C404 programmable clock s In-Circuit Testability Features s Small low-cost package: EIAJ-standard 160-pin plastic flat pack s Chip pinouts optimized for PCB layout 8-bit I/O Access Clock Source 8-bit Digital 16-Bit I/O or Memory Access From System ISA Bus 64200 Color Palette (RAMDAC) To CRT Wingine TTL H/V Sync 16 / 32-Bit Memory Access From SX or DX System Memory Controller Analog RGB Buffers & Transceivers To CRT Serial Clock & 32-bit Serial Data Display Memory System Diagram - Memory Bus Architecture Revision 0.6 Preliminary 64200 ® Revision History Revision History Revision Date By Comment 0.2 10/10/91 DH Changed pinouts Modified & expanded application schematics Updated register bit definitions Added Introduction section Added Electrical specifications section Added support for Bt484 & MU color palette chips 0.21 11/4/91 DH Changed Bt484 application schematic hookup Added 82C481 82C481 connection application schematic 0.3 11/19/91 DH Rewrote introduction section Added 'NDA Required' disclaimer for protection until chip announcement Changed part number for chip to 64200 Changed chip pinouts to group P0-7, PCLK, and BLANK/ together Moved TOUT from VSYNC to VGA pin to keep next to TCLK Added NCLK output on pin 98 (moved DSF to reserved pin 137) Memory interface now remains tristated until 1st write to Master Ctrl reg Inverted Master Control register bit-6 (XREQ/ Divide control) Added Master Control register bit-7 (XREQ/ Direction control) Added XR3D bit-4 (word swap) for selection of 16-bit shiftout from CD (to allow DX 512K option for lower half of VRAMs to be optional) Moved the memory configuration bit from XR01 bit-3 to XR3D bit-5 Fixed the documentation to reflect 2MB VRAM support Added description of XR28 Video Interface Register 0.4 2/12/92 0.5 0.6 Revision 0.6 ST/DH Added missing register definitions Increased drive specifications on various pins Swapped DSF and WE/ pinouts (documentation error) Fixed bus reference specifications Changed electrical specs for 80MHz video frequencies Fixed bit definitions (XR03[6], XR3D[5]) and added MEM/ config bit Added 64201 interface diagrams and updated 481 intfc block diagram 4/92 VS Added table of supported resolutions Added information on interfacing to CS4021 CS4021 system chipset Added more information on interfacing to CS82310 CS82310 system chipset Added Winglue information Removed XR02 bits 0,2 (always 16-bit access) Removed XR04 bits 6-7 (not implemented) Added XR3D bit 3 (481 mode) Removed XR44 (not implemented) Removed generic bus interface timing 7/92 VS/ST Modified Memory Timing Removed XR03 bits 2-3 (not implemented) Added description of how to support external VGA Release Data Sheet to Marcom 2 Preliminary 64200 ® Table of Contents Table of Contents Section Page Introduction . 5 Display Memory Configurations . System Support Requirements. Memory Interface . Recommended Memory Chips . System Interface . Wingine/CS4021 Interface. Wingine/CS82310 Interface. Section 5 6 6 6 7 7 7 Application Schematic Examples. 89 System Bus Interface . Display Memory Interface. Video Interface . Clock Interface . Absolute Maximum Conditions. Normal Operating Conditions . DC Characteristics. DC Drive Characteristics. AC Test Conditions . AC Characteristics Clock Timing. Reset Timing. Bus Timing . Display Memory Timing . Video Timing. Mechanical Specifications. 13 14 15 17 19 20 Register and Port Address Summaries . 21 CGA, MDA, and Hercules Registers. EGA Registers . VGA Registers. VGA Indexed Registers. Extension Registers . 90 91 100 104 Electrical Specifications. 105 Pinouts. 13 Pin Diagram. Pin List. Pin Descriptions - System Bus Interface . Pin Descriptions - Display Memory . Pin Descriptions - Video Interface . Pin Descriptions - Clock, Power & Ground Page 21 21 21 22 23 105 105 106 106 106 107 107 108 110 114 115 Plastic 160-PFP 160-PFP Package Dimensions . 115 PCB Layout Pad Dimensions . 115 Register Descriptions . 27 Global Control (Setup) Registers . General Control and Status Registers. CGA / Hercules Registers. Sequencer Registers. CRT Controller Registers . Graphics Controller Registers . Attribute Controller and Color Palette Registers . Extension Registers . Revision 0.6 29 31 23 37 41 55 63 69 3 Preliminary 64200 ® List of Figures and Tables List of Figures and Tables Figure Page Table System Diagram . 1 Wingine Interface to ISA486 ISA486 . 8 Wingine Interface to PEAK/DM. 10 Pin List . 14 Pin Descriptions . 15 Register Summary - CGA/MDA/Herc Modes Register Summary - EGA Mode . Register Summary - VGA Mode. Register Summary - Indexed Registers. Register Summary - Extension Registers. Clock Timing. System Bus Timing . Display Memory Page Mode Write Timing. Display Memory Page Mode Read Timing. Display Memory Refresh Timing . Video Timing . 63 69 105 105 106 106 106 AC Characteristics Clock Timing. Reset Timing. System Bus Timing . Display Memory Read/Write Timing. Display Memory Refresh Timing. Video Timing. 107 108 111 112 112 113 29 31 33 37 41 55 Absolute Maximum Conditions . Normal Operating Conditions . DC Characteristics. DC Drive Characteristics . AC Test Conditions. 90 91 92 93 94 95 96 96 97 98 99 100 101 102 103 104 104 21 21 21 22 23 Register List - Setup Registers . Register List - General Control & Status . Register List - CGA/Hercules Registers . Register List - Sequencer . Register List - CRT Controller. Register List - Graphics Controller . Register List - Attribute Controller and Color Palette . Register List - Extension Registers . Pinouts. 13 Application Schematic Examples System Bus (ISA) . Display Memory (DX w/ VRAM's) . Display Memory (SX w/ VRAM's) . Display Memory (SX Minimum System) . Display Memory (SX w/ VGA DRAM's) . Display Memory (82C481 82C481 Graphics Accel) 82C481 82C481 + Wingine Block Diagram . 82C481 82C481 + Wingine PCB Layout. Peak/DM Interface Block Diagram . Peak/DM Interface Circuit Part 1 . Peak/DM Interface Circuit Part 2 . Video (BT475 BT475 RAMDAC) . Video (SC11482 SC11482 RAMDAC) . Video (MU9C1715 MU9C1715 RAMDAC) Video (Bt484 RAMDAC) . Clock (82C404 82C404 Clock Chip) . Clock (Discrete Oscillators) . Page 107 107 108 111 113 114 Package Mechanical Dimensions. 114 Suggested PCB Pad Layout. 115 Revision 0.6 4 Preliminary 64200 ® Introduction Introduction The concept behind the 64200 'Windows Engine' (Wingine) is the implementation of video display memory as a bank (or banks) of system memory. The idea is that the system CPU (typically at least a 386-class processor) can manipulate pixels on the screen quickly if the display memory bottleneck is removed. The video memory is accessed directly by the system CPU as a frame buffer through the VRAM random access port while the display is continuously being refreshed via the VRAM serial data port. Wingine directly supports 4bpp (nibble) and 8bpp (byte) modes with standard VGA 8-bit RAMDACs which are available up to 80 MHz. 16bpp mode may be supported with an extended capability RAMDAC such as a Sierra SC11482 SC11482, 483, or 484. Wingine can also support various types of high performance and extended capability RAMDACs with 32-bit parallel data input ports. These RAMDACs typically support pixel rates to 135 MHz and modes of 1bpp, 2bpp, 4bpp, 8bpp, 16bpp, and / or 24bpp. All known RAMDACs support these modes lsb first (e.g., nibble modes shift the first pixel out of bits 0-3 of the first byte in memory, the second pixel out of bits 4-7, etc). All of these modes up to 16bpp are also supported in the XGA ('lsb first' is referred to as 'Intel order' in IBM's XGA documentation). Therefore, for compatibility, pixel shift order is always lsb first and pixels are always stored in Wingine memory as a linear array of n-sized elements starting with bit-0 of byte 0. Wingine is basically a standard 16-bit VGA with extensions. The primary extension is to allow the system to directly access VRAM display memory as system memory. Wingine operates in two modes: 'Windows Acceleration' mode and 'VGA' mode. In 'VGA' mode, Wingine drives the video memory. Wingine uses the VRAMs as DRAMs in VGA mode (no special capabilities of the VRAMs are required or used); all VGA operations are implemented via the VRAM random access port. (Wingine pinouts are defined such that future implementations may be extended to take advantage of the VRAM serial port in VGA mode.) In 'Windows Acceleration' mode, the VRAM random access ports are driven by the system memory controller; the Wingine chip does not have access to the VRAMs, but performs all VRAM serial data shift operations and provides HSYNC and VSYNC for the display monitor. In 'Windows Acceleration' mode, the system performs all data transfer operations based on information provided from the Wingine chip. DISPLAY MEMORY CONFIGURATIONS The VRAM frame buffer may be implemented with two, four, or eight 256Kx4 (1Mb) or two or four 256Kx8 (2Mb) VRAMs, accessed as 1 bank of 32bit memory in 386 DX or 486 systems or as 2 banks of 16-bit memory in 386 SX systems. This provides 1MB of display memory, which is adequate for support of 1024x768 at 8bpp (256color). This amount of memory, using split buffer VRAMs and a Sierra RAMDAC (or equivalent), will also support 16bpp modes up to 800x600. Wingine allows 512KB 512KB upgradable to 1MB of display memory in 386 SX (16-bit) systems by optionally populating the upper bank. The 512KB 512KB configuration supports 1024x768 at 4bpp (16-color) and 640x480 at 8bpp (256-color). If word interleaving is done in 16-bit systems, the memory map is identical between 16 and 32 bit systems (and the same drivers may be used). Wingine is designed to also handle non-word-interleaved 2 bank 16-bit memory maps, if word interleaving is not implemented by the system. The result is very high performance, since the entire random port bandwidth is available for CPU access and the VRAMs may always be accessed at full memory speed. In addition, memory may be accessed at the full width of system memory (16 or 32 bits). The frame buffer may be accessed as a linear array of pixels (in 'packed-pixel' format) anywhere in the system memory space. Another major advantage is the ability to accept 32 bits of serial data from the VRAMs and convert it into an 8-bit video data stream compatible with a standard low-cost VGA RAMDAC. This capability removes the requirement for an expensive RAMDAC, allowing implementation of cost effective, high performance graphics system. Revision 0.6 If 256Kx4 VRAMs are used, 512KB 512KB of display memory (upgradable to 1MB) may also be implemented by optionally populating the upper nibble of each byte. In this configuration, the 5 Preliminary 64200 ® Introduction system would always manipulate display memory assuming 8bpp; screen display would be 16-color with 4 VRAMs installed and 256-color with 8 VRAMs installed (the RAMDAC pixel mask register would be set to mask out the upper 4 bits of video data in 4-VRAM mode). MEMORY INTERFACE Two types of memory subsystems can be designed with Wingine. In the first type, 2 or 4 DRAMs can be used for VGA compatible modes. For Wingine modes, separate VRAMs are used. In this implementation, VGA memory and 'Wingine mode' memory are separate. No external buffers are required to isolate the two memory buses. Wingine will support 24bpp modes up to 640x480 in 1MB configurations, but a RAMDAC must be used which allows packing R, G, & B every 3 bytes and AT &T 206491 RAMDACs. The Bt482 support this type of pixel packing. However Wingine will support 24bpp modes up to 640x400 if the RAMDAC ignores one byte out of every four. Many 32-bit input RAMDACs (Bt484 / 485, TI 34075 / 34076) support 24bpp mode in this fashion (by ignoring the upper byte of the 32-bit input). Since only one pixel is input to the RAMDAC every shift clock, the maximum pixel rate in this mode is limited by the VRAM shift clock rate: 33 MHz for '-10' (100nS) VRAMs and 40 MHz for '-8' (80nS) VRAMs). In the second type of memory subsystem, a shared memory bus is used for a cost effective implementation. In this case, only VRAMs are used. In VGA mode, Wingine controls video memory. In 'Wingine' mode, the system memory controller has control over video memory. External buffers are required to isolate the two buses - the Wingine memory bus and the system memory bus. Refer to the following section for additional details. Wingine can support up to 2 Mbytes of display memory. It can also support 256 Kbyte and 512 Kbyte memory configurations. The following table shows a matrix of resolution and memory requirements. This table assumes a shared memory architecture. It is important to buffere SCLK with a fast buffer when 2 Mbyte configuration is used. Wingine supports interlaced displays at 1024x768 resolution. Wingine maintains a linear address mapping scheme so that software drivers are independent of whether the display is interlaced or not. Resolution Wingine is compatible with VRAM memory configurations larger than 1MB, if implemented by the system as either multiple banks of 32-bit memory using '256K x N' VRAMs or single banks of 32-bit memory using '512K x N' or '1M x N' VRAMs. These configurations would typically be implemented with 32-bit input extended-function, high-performance RAMDACs and support high resolutions (e.g., 1280x1024) and/or high-color modes (16bpp and 24bpp). VGA Mode 640x480 16 Colors 800x600 16 Colors 640x480 256 Colors 1024x768 16 Colors 256 Kbytes 256 Kbytes 512 Kbytes 512 Kbytes Wingine Mode 640x480 256 Colors 800x600 256 Colors 1024x768 256 Colors 640x480 16 bits/pixel 640x480 24 bits/pixel 800x600 16 bits/pixel 1024x768 16 bits/pixel 1280x1024 256 colors SYSTEM SUPPORT REQUIREMENTS To implement a Wingine-based Graphics subsystem, the system memory controller must be able to map a bank (or banks) of VRAMs into the system memory space. The memory controller must be aware of the differences between VRAMs and DRAMs for random access port control (the VRAM serial port is controlled by Wingine). Wingine support exists in the CS4021 CS4021 486 CHIPSet. Chips and Technologies plans to provide Wingine support in all future Systems Logic CHIPSetsTM and SYSTEMSetsTM to allow Wingine to interface directly to those products. Extensions are also planned for all current CHIPSetsTM and SYSTEMSetsTM. Revision 0.6 Memory 512 Kbytes 512 Kbytes 1 Mbyte 1 Mbyte 1 Mbyte 1 Mbyte * 2 Mbyte* 2 Mbytes * Requires Split - Buffer VRAMs. * Requires Bt484 compatible DAC. RECOMMENDED MEMORY CHIPS Standard Micron Mitshubishi Toshiba NEC 6 Split Buffer MT42C4256 MT42C4256 442256 524256 42273 Preliminary 64200 ® Introduction SYSTEM INTERFACE The 64200 Wingine chip is tightly coupled to system chipsets from Chips and Technologies. This tight coupling between Wingine and the system chipset results in a very high performance Windows architecture. The Wingine graphics controller can be interfaced to two high performance CHIPSets from Chips & Technologies - the CS4021 CS4021 and CS82310 CS82310 chipsets. lines. During VGA modes, the ISA486 ISA486 memory controller is isolated from video memory by pulling the VGA pin high. The addresses and control signals for video memory are generated by Wingine. In 'Wingine' mode, the VGA pin goes low and the system memory controller drives the address and control lines. The Wingine memory bus is tristated during this mode. Wingine/CS82310 Interface The CS82310 CS82310 (also called the PEAK/DM chipset) is another high end chipset that can support Wingine. To simplify the interface to PEAK/DM, a companion chip "64201 (Winglue)" has been designed. Winglue interfaces between PEAK/DM and Wingine. Figure 3 shows the data bus interface for PEAK/DM. The external data buffers are controlled by Winglue. Wingine uses the VGA pin to indicate if it is in VGA or 'Wingine' mode. In VGA mode, the VOE/ pin from Winglue is high thus tristating the data buffers on the upper data bus. For a 16 bit VGA interface, the external PAL generates MEMCS16/ MEMCS16/ for the AT bus. The same signal is used by Winglue to qualify VMEMR/ and VMEMW/ to Wingine for valid VGA cycles. In 'Wingine' mode, Winglue pulls the VOE/ pin low to enable the data buffers. The MDINP pin from Winglue controls the direction of the data buffers for read/write cycles. Winglue performs the transfer cycles to the video RAMs based on the XREQ/ input from Wingine. Winglue also arbitrates with the system memory controller for control of the memory bus during transfer cycles using the HLD/HLDA protocol. Figure 4 shows the interface for address and control signals. During VGA mode, the VOE/ pin is high to disable the address/control buffers. In 'Wingine' mode, VOE/ goes low to allow the memory controller to drive the address and control lines. Wingine tristates its memory bus during 'Wingine' mode. Wingine/CS4021 Interface CS4021 CS4021 (also called the ISA486 ISA486 chipset) is CHIPS' next generation high end chipset. This chipset can support both 386 and 486 designs. Special features are provided in the ISA486 ISA486 chipset for a simple and elegant interface to the Wingine subsystem. Figure 1 and Figure 2 show the Wingine/ISA486 interface. Figure 1 shows the data path between the ISA486 ISA486 memory controller and Wingine memory. In VGA mode, Wingine interfaces to the ISA bus. In this mode, display memory is controlled by Wingine. The CPU accesses video memory through Wingine. In VGA mode, up to 512 Kbytes of video memory is supported. In this mode, the VGA pin from Wingine is high to isolate the data bus from ISA486 ISA486. As Wingine has 17 address lines, it is necessary to qualify memory read and memory writes with a valid VGA address. The external PAL decodes the upper address (LA17 -LA23 -LA23) from the ISA bus for a valid VGA access (0A0000 0A0000 - 0BFFFFh) and qualifies the MEMR/ and MEMW/ signals to Wingine. When the 64200 is switched to 'Windows Accelerator' (or Wingine) mode, the ISA486 ISA486 chipset can access video memory directly for much higher video performance. In this mode up to 2 Mbytes of display memory can be supported. Figure 1 shows a 1MB implementation. In 'Wingine' mode the full 32 bit memory bus can be utilized for accessing display memory. In this mode, Wingine tristates its memory bus and pulls the VGA pin low. The two data buffers on the upper 16 bits of the memory bus are enabled allowing the ISA486 ISA486 memory controller to access video memory directly. The direction of the data buffers is controlled by an external signal derived from the RAS/, CAS/, and WE/ signals from ISA486 ISA486. For Write operations, data is driven onto the video memory data lines. During read cycles, the buffers are turned around to drive the data onto the system memory bus. The XREQ/ signal from Wingine is used to request a transfer cycle from the system memory controller. The memory controller will perform a transfer cycle to the video RAMs when XREQ/ goes active. Figure 2 shows the interface for address and control Revision 0.6 EXTERNAL VGA SUPPORT An external VGA can be supported in Wingine system. The motherboard Wingine can be disabled by disconnecting the AEN signal to Wingine. This will prevent Wingine from being initialized. An external VGA can then reside in the system without any conflict with Wingine. MEMCS16/ MEMCS16/ from the Wingine subsystem should also be disabled to allow 8 bit VGA cards. Two jumpers can be used on the AEN and MEMCS16/ MEMCS16/ lines. Refer to Figure 1 and Figure 3. 7 Preliminary 64200 ® Introduction 245 D G MD24-31 MD24-31 MD16-23 MD16-23 CAS2/ DWE/ VRAS/ CAS3/ DIR REF LDWE 245 D G VGA PAL 2 SYSTEM LOGIC (ISA486 ISA486) MEMORY CONTROLLER ISA BUS XREQ/ MBD7-0 MEMR/ MEMW/ PAL 1 VMEMR/ D7-0 SD7-0 SDD7-0 256KX8 256KX8 VRAM SOE/ LA17-LA23 LA17-LA23 VMEMW/ WINGINE MAD7-0 D7-0 SCD7-0 J MEMCS16/ MEMCS16/ SD7-0 VRAM VCC J 256KX8 256KX8 AEN SOE/ SBD7-0 SAD7-0 DATA/ADDRESS D7-0 MD8-15 MD8-15 256KX8 256KX8 VRAM SD7-0 SOE/ RESET MD7-0 SOE/ 256KX8 256KX8 D7-0 VRAM SD7-0 OPTIONAL Figure 1 - Wingine Interface to ISA486 ISA486 (Data) PAL EQUATIONS: PAL 1 RAMADD = !LA23 & !LA22 & !LA21 & !LA20 & LA19 & !LA18 & LA17; VMEMR = MEMR & RAMADD; VMEMW = MEMW & RAMADD; MEMCS16 MEMCS16.OE = RAMADD; MEMCS16 MEMCS16 = 'B' 1; PAL 2 CASS = CAS2 # CAS3; REF = CAS2 & !VRAS # REF & CAS2 # REF & VRAS; LDWE = DWE & !CASS # LDWE & CASS # LDWE & DWE; DIR = CASS & VRAS & !REF & !LDWE; Where REF - Indicates a valid memory refresh cycle LDWE - Latched write enable with CAS. Revision 0.6 8 Preliminary 64200 ® Introduction SYSTEM LOGIC (ISA486 ISA486) XREQ/ MB8-0 A0-8 256KX8 256KX8 VRAM CONTROL MEMORY CONTROLLER WINGINE ISA BUS MA8-0 A0-8 256KX8 256KX8 VRAM VGA A0-8 256KX8 256KX8 VRAM E CONTROL 244 A0-8 E 256KX8 256KX8 VRAM 244 A0-A8 E OPTIONAL 244 Figure 2 - Wingine Interface to ISA486 ISA486 (Address/Control) Revision 0.6 9 Preliminary 64200 ® Introduction 245 MD24-31 MD24-31 DI G R MD16-23 MD16-23 DI G R 245 VOE MDINP SYSTEM LOGIC PEAK/DM WINGLUE HLD/HLDA MBD7-0 XREQ/ MEMORY CONTROLLER D7-0 SDD7-0 SD7-0 256KX8 256KX8 VRAM WINGINE VGA ISA BUS MEMCS16/ MEMCS16/ D7-0 SCD7-0 256KX8 256KX8 SD7-0 VRAM MEMCS16/ MEMCS16/ J SMEMR/ VCC SMEMW/ LA17-LA23 LA17-LA23 VMEMR/ VMEMW/ SBD7-0 SAD7-0 J MD8-15 MD8-15 MAD7-0 AEN DATA/ADDRESS 256KX8 256KX8 D7-0 VRAM SD7-0 256KX8 256KX8 MD7-0 D7-0 VRAM SD7-0 OPTIONAL Figure 3 - Wingine Interface to PEAK/DM (Data) PAL EQUATION: RAMADD = ! LA23 & !LA22 & !LA21 & !LA20 & LA19 & !LA18 & LA17; VMEMR = MEMR & RAMADD; VMEMW = MEMW & RAMADD; MEMCS16 MEMCS16 .OE. = RAMADD; MEMCS16 MEMCS16 . = ' b' 1 ; Revision 0.6 10 Preliminary 64200 ® Introduction BA8-0 AA8-0 CONTROL SYSTEM LOGIC HLD/HLDA BA8-0 WINGLUE PEAK/DM A8-0 256KX8 256KX8 VRAM XREQ/ CONTROL WINGINE VGA 256KX8 256KX8 AA8-0 A8-0 VRAM MEMORY CONTROLLER VOE A8-0 E CONTROL 256KX8 256KX8 VRAM 244 E A8-0 256KX8 256KX8 VRAM 244 E A0-A8 244 OPTIONAL Figure 4 - Wingine Interface to PEAK/DM (Address/Control) Revision 0.6 11 Preliminary 64200 ® Revision 0.6 12 Preliminary 64200 ® Pinouts 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 (ICT1/) (TSE1/) 64200 Wingine Note: Pin names shown indicate ISA (PC/AT) bus connections Pin names in parentheses (.) indicate alternate function (ICT0/) (TSE0/) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 GND SENSE PALWR/ PALRD/ VSYNC HSYNC XREQ/ IRQ RESET VCC GND D15 D7 D14 D6 GND D13 D5 D12 D4 VCC GND D11 D3 D10 D2 GND D9 D1 D8 GND VCC D0 IOCS16/ IOCS16/ A16 A15 A14 A13 A12 A11 MAD5 MAD6 MAD7 SAD0 SBD0 SCD0 SDD0 SAD1 SBD1 SCD1 SDD1 SAD2 SBD2 SCD2 SDD2 SAD3 SBD3 SCD3 SDD3 VCC GND RDY IORD/ IOWR/ VMEMR/ VMEMW/ RFSH/ AEN BHE/ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 MBD4 MBD3 MBD2 MBD1 MBD0 BA8 BA7 BA6 BA5 GND BA4 BA3 BA2 BA1 BA0 DTOEB/ WE/ CASB/ RASB/ VCC GND RASA/ CASA/ DSF DTOEA/ AA0 AA1 AA2 AA3 GND AA4 AA5 AA6 AA7 AA8 MAD0 MAD1 MAD2 MAD3 MAD4 120 119 118 117 116 115 114 113 112 111 110 (BUS0)(CFG0) 109 (BUS1)(CFG1) 108 (OSC/)(CFG2) 107 (MEM/)(CFG3) 106 (CFG4) 105 (CFG5) 104 (CFG6) 103 (CFG7) 102 101 100 99 98 97 (FLD)(MUX) (CSEL2) 96 (CSEL1) 95 (CSEL0) 94 (CLKIN) 93 92 91 90 89 88 87 86 85 84 83 82 81 MBD5 MBD6 MBD7 SAD4 SBD4 SCD4 SDD4 SAD5 SBD5 SCD5 SDD5 SAD6 SBD6 SCD6 SDD6 SAD7 SBD7 SCD7 SDD7 GND VCC SCLK NCLK VGA (TOUT) CLK3 (TCLK) CLK2 CLK1 CLK0 MCLK GND BLANK/ PCLK P0 P1 P2 P3 P4 P5 P6 P7 Pinouts Revision 0.6 13 Preliminary 64200 ® Pin Name A00 A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 AA0 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AEN BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BA8 BHE/ BLANK/ CASA/ CASB/ CLK0 CLK1 CLK2 CLK3 (TCLK) D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 DSF Pin List Pin # Dir Drive Pin Name 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 146 147 148 149 151 152 153 154 155 28 135 134 133 132 131 129 128 127 126 29 (DE) 90 143 138 (CLKIN) 93 (CSEL0) 94 (CSEL1) 95 (CSEL2) 96 (FLD) (MUX) 48 52 55 57 61 63 66 68 51 53 56 58 62 64 67 69 144 Revision 0.6 In In In In In In In In In In In In In In In In In Out Out Out Out Out Out Out Out Out In Out Out Out Out Out Out Out Out Out In Out Out Out In I/O I/O I/O -4mA 4mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA -4mA 4mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA -4mA 4mA 4mA -4mA 4mA 4mA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Out 24mA 24mA 24mA 24mA 24mA 24mA 24mA 24mA 24mA 24mA 24mA 24mA 24mA 24mA 24mA 24mA 2mA Pin # Dir Drive Pin Name DTOEA/ DTOEB/ GND GND GND GND GND GND GND GND GND GND GND GND HSYNC IOCS16/ IOCS16/ IORD/ IOWR/ IRQ MAD0 (TSE0/) MAD1 (ICT0/) MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 MBD0 (TSE1/) MBD1 (ICT1/) MBD2 MBD3 MBD4 MBD5 MBD6 MBD7 MCLK NCLK P0 P1 P2 P3 P4 P5 P6 P7 PALRD/ PALWR/ PCLK RASA/ RASB/ RDY RESET RFSH/ SAD0 SAD1 SAD2 SAD3 SAD4 SAD5 SAD6 (CFG0) (BUS0) SAD7 (CFG4) SBD0 14 145 136 21 50 54 59 65 70 80 91 101 130 141 150 75 47 23 24 73 156 157 158 159 160 1 2 3 125 124 123 122 121 120 119 118 92 98 88 87 86 85 84 83 82 81 77 78 89 142 139 22 72 27 4 8 12 16 117 113 109 105 5 Out Out -Out I/O In In I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O In Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out In In In In In In In In In In In 2mA 2mA -24mA 24mA -24mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA -4mA 4mA 4mA 4mA 4mA 4mA 4mA 4mA 4mA 2mA 2mA 4mA 4mA 4mA 24mA - Pin # Dir Drive SBD1 SBD2 SBD3 SBD4 SBD5 SBD6 (CFG1) (BUS1) SBD7 (CFG5) SCD0 SCD1 SCD2 SCD3 SCD4 SCD5 SCD6 (CFG2) (OSC/) SCD7 (CFG6) SCLK SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 (CFG3) (MEM/) SDD7 (CFG7) SENSE VCC VCC VCC VCC VCC VCC VGA (TOUT) VMEMR/ VMEMW/ VSYNC XREQ/ WE/ (BUS0,BUS1) (CFG0-7) (CLKIN) (CLKSEL0-2) (DE) (FLD) (ICT0/) (ICT1/) (MEM/) (MUX) (OSC/) (TSE0/) (TSE1/) (TCLK) (TOUT) 9 13 17 116 112 108 104 6 10 14 18 115 111 107 103 99 7 11 15 19 114 110 106 102 79 20 49 60 71 100 140 97 25 26 76 74 137 In In In In In In In In In In In In In In In Out In In In In In In In In In -Out In In Out I/O Out -4mA -2mA -24mA 4mA 4mA See SAD6,SBD6 See SxD6,SxD7 See CLK0 See CLK1-3 see BLANK/ See CLK3 See MAD1 See MBD1 See SDD6 See CLK3 See SCD6 See MAD0 See MBD0 See CLK3 See VGA Preliminary 64200 ® Pin Descriptions PIN DESCRIPTIONS Pin # Pin Name System Bus Interface Type Active Description 48 52 55 57 61 63 66 68 51 53 56 58 62 64 67 69 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O High High High High High High High High High High High High High High High High System Data Bus 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 In In In In In In In In In In In In In In In In In High High High High High High High High High High High High High High High High High System Address Bus (Note: upper addresses are decoded external to the chip and used to qualify the VMEMR/ and VMEMW/ inputs) Note: Pin names in parentheses (.) indicate alternate functions Revision 0.6 15 Preliminary 64200 ® Pin Descriptions PIN DESCRIPTIONS Pin # Pin Name System Bus Interface (continued) Type Active Description 72 RESET In High Reset. Connect directly to the bus reset signal. Note: the VRAM SOE/ pins should also be connected to RESET. 27 RFSH/ In Low This pin is an active low signal indicating a Refresh cycle. When this pin is low, memory is not accessible. 29 BHE/ In Low Byte High Enable. BHE/ low indicates the high order byte at the current word address is being accessed. 28 AEN In Both Indicates valid I/O address: 0 = valid I/O address, 1 = invalid I/O address (IORD/ and IOWR/ will be ignored). 73 IRQ Out Both Frame Interrupt Output. Interrupt polarity is programmable. Set when interrupt on VSYNC is enabled. Cleared by reprogramming register 11h in the CRT Controller. 47 IOCS16/ IOCS16/ Out Low 23 IORD/ In Low 24 IOWR/ In Low 25 VMEMR/ In Low 26 VMEMW/ In Low 22 RDY Out High I/O Select 16. Indicates 16-bit I/O access. I/O Read Strobe I/O Write Strobe Memory Read Strobe qualified with upper address bits Memory Write Strobe qualified with upper address bits Ready. Driven low to indicate that the current cycle should be extended with wait states. This signal is driven high at the end of the cycle, then tristated. Note: Pin names in parentheses (.) indicate alternate functions Revision 0.6 16 Preliminary 64200 ® Pin Descriptions PIN DESCRIPTIONS Pin # Pin Name Display Memory Interface Type Active Description 146 147 148 149 151 152 153 154 155 AA0 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 Out Out Out Out Out Out Out Out Out High High High High High High High High High DRAM address bus for planes 0-1 135 134 133 132 131 129 128 127 126 BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BA8 Out Out Out Out Out Out Out Out Out High High High High High High High High High DRAM address bus for planes 2-3 142 139 RASA/ RASB/ Out Out Low Low Row address strobe for memory planes 0-1 Row address strobe for memory planes 2-3 143 138 CASA/ CASB/ Out Out Low Low Column address strobe for planes 0-1 Column address strobe for planes 2-3 137 WE/ Out Low Write enable for memory all planes 145 136 DTOEA/ DTOEB/ Out Out Low Low VRAM data transfer output enable for planes 0-1 VRAM data transfer output enable for planes 2-3 144 DSF Out High VRAM Special Function (block write, etc.) 156 157 158 159 160 1 2 3 MAD0 MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 (TSE0/) (ICT0/) I/O I/O I/O I/O I/O I/O I/O I/O High High High High High High High High Display memory data bus for planes 0 and 1 125 124 123 122 121 120 119 118 MBD0 MBD1 MBD2 MBD3 MBD4 MBD5 MBD6 MBD7 (TSE1/) (ICT1/) I/O I/O I/O I/O I/O I/O I/O I/O High High High High High High High High Display memory data bus for planes 2 and 3 (see clock pins page for explanation of the TSE and ICT features) Note: Pin names in parentheses (.) indicate alternate functions Revision 0.6 17 Preliminary 64200 ® Pin Descriptions PIN DESCRIPTIONS Pin # Pin Name Display Memory Interface (continued) Type Active Description 4 8 12 16 117 113 109 105 SAD0 SAD1 SAD2 SAD3 SAD4 SAD5 SAD6 SAD7 (SD0) (SD1) (SD2) (SD3) (SD4) (SD5) (SD6) (SD7) I/O I/O I/O I/O I/O I/O (CFG0) I/O (CFG4) I/O High High High High High High High High Serial data for bits 0-7 (pixel A) 5 9 13 17 116 112 108 104 SBD0 SBD1 SBD2 SBD3 SBD4 SBD5 SBD6 SBD7 (SD8) I/O (SD9) I/O (SD10) I/O (SD11) I/O (SD12) I/O (SD13) I/O (SD14) (CFG1) I/O (SD15) (CFG5) I/O High High High High High High High High Serial data for bits 8-15 (pixel B) 6 10 14 18 115 111 107 103 SCD0 SCD1 SCD2 SCD3 SCD4 SCD5 SCD6 SCD7 (SD16) I/O (SD17) I/O (SD18) I/O (SD19) I/O (SD20) I/O (SD21) I/O (SD22) (CFG2) I/O (SD23) (CFG6) I/O High High High High High High High High Serial data for bits 16-23 (pixel C) 7 11 15 19 114 110 106 102 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 (SD24) I/O (SD25) I/O (SD26) I/O (SD27) I/O (SD28) I/O (SD29) I/O (SD30) (CFG3) I/O (SD31) (CFG7) I/O High High High High High High High High Serial data for bits 24-31 (pixel D) 99 SCLK Out High VRAM shift clock. Inactive during H/V blanking. 74 XREQ/ I/O Low Transfer Request. Used as an output to signal that a VRAM data transfer cycle needs to be performed (i.e., VRAM shift registers need to be filled). Used as an input to signal that a data transfer has been performed (i.e., VRAM shift registers are ready to be shifted out). Tristate if Wingine mode is disabled (default). Internal pullup. Direction is controlled by XR03 bit-7. 97 VGA Out High CFG1 is also called BUS1 (see config register XR01) CFG2 is also called OSC/ (see config register XR01) CFG3 is also called MEM/ (see config register XR01) VRAM Control Select. High indicates the Wingine chip is driving the VRAM address, data, and control Also becomes the test output in ICT mode. See lines. Low indicates Wingine's VRAM address, data, the clock pins page for an explanation of ICT and control pins are tri-stated. Controlled by XR03 d (Master Control register, port 22-23h index E0h) bit-0 inverted Note: Pin names in parentheses (.) indicate alternate functions Revision 0.6 (TOUT) CFG0 is also called BUS0 (see config register XR01) 18 Preliminary 64200 ® Pin Descriptions PIN DESCRIPTIONS Pin # Pin Name Video Interface Type Active Description 81 82 83 84 85 86 87 88 P7 P6 P5 P4 P3 P2 P1 P0 Out Out Out Out Out Out Out Out High High High High High High High High 8-bit video data output 76 VSYNC Out Both Horizontal Sync (polarity is programmable: MSR bit7) 75 HSYNC Out Both 89 PCLK Out High Vertical Sync (polarity is programmable: MSR bit-6) Pixel clock for video data. In 16-bit/pixel mode, the rising edge may be used externally to latch the 'upper' data byte and the following falling edge used to transfer the 'lower' byte. 90 BLANK/ (DE) Out Both Blanking signal for the external color palette chip (polarity is programmable: see XR28 bit-0). This pin may also be redefined as a Display Enable signal (see XR28 bit-1). 78 PALWR/ Out Low I/O write strobe for the external color palette chip (IMSG176 IMSG176, BT47x, or compatible). Asserted when the chip is enabled and an I/O Write occurs to addresses 3C6-3C9h (or 43Cx, 83Cx, and C3Cx if enabled by XR02). 77 PALRD/ Out Low I/O read strobe for an external color palette chip (IMSG176 IMSG176, BT47x, or compatible). Asserted when an I/O Read occurs from addresses 3C6h, 3C8h, or 3C9h (or 43Cx, 83Cx, and C3Cx if enabled by XR02). The chip responds directly for reads from 3C7h. 79 SENSE In High Monitor sense input. Normally connected to the outputs of an LM339 LM339 comparator on the external color palette chip analog RGB outputs (or directly to the color palette chip if this function is built in such as in the BT475 BT475). The state of this pin may read as bit-4 of Input Status Register 0 (port 3C2h). See also extension register XR1F (Virtual Switch Register). Note: Pin names in parentheses (.) indicate alternate functions Revision 0.6 19 Preliminary 64200 ® Pin Descriptions PIN DESCRIPTIONS Pin # Pin Name Clock, Power, and Ground Type Active In High Memory Clock. 50 MHz for 100ns RAM's, 56 MHz for 80 ns RAM's, or 65 MHz for 70ns RAM's. If external clock selection is enabled (default), CLKIN is the input dotclock for all pixel clock frequencies and CLK0-1 become clock select outputs driven by Misc Output Register (MSR at port 3C2h) bits 2 and 3 (CSEL 0 and 1, respectively). The CLK3 pin can be programmed (via FCR port 3BA/3DA bits 0-1) to be low or high (CSEL2), an odd/even field indicator for interlace mode (FLD), or PCLK÷2 (MUX). CLK3 is also used as the test clock (TCLK) in ICT mode (see the description of ICT mode at bottom of page). 92 MCLK 93 CLK0 (CLKIN) In High 94 CLK1 (CSEL0) I/O High 95 CLK2 (CSEL1) I/O High 96 CLK3 (CSEL2) (FLD) (MUX) (TCLK) I/O High Description If internal clock selection is enabled (see configuration pin 'OSC/' and config register XR01), CLK0, CLK1, CLK2, and CLK3 are inputs for external discrete oscillators. One of the four is selected as the input dotclock per Misc Output Register (MSR port 3C2h) bits 2-3. 98 NCLK Out High 20 49 60 71 100 140 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC - 21 50 54 59 65 70 80 91 101 130 141 150 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PCLK ÷ 4 or ÷ 8 (free-running version of SCLK). - Power Ground ICT Mode: If ICT0/ and ICT1/ are low with RESET high, a rising edge on CLK3 will put the chip into 'In Circuit Test' mode. In ICT mode, all digital signal pins become inputs which are part of a long path starting at NCLK (pin 98) and proceeding to higher pin numbers around the chip to pin 160 then to pin 1 and ending at CLK3 (pin 96). If all pins in the path are high, the VGA output will be high. If any pin is low, the VGA output will be low. Thus the chip can be checked in circuit to determine if all pins are connected properly by toggling all pins one at a time (CLK3 last) and observing the effect on VGA. CLK3 must be toggled last because rising edges on CLK3 with ICT1/ or ICT2/ high or RESET low will exit ICT mode. As a side effect, ICT mode effectively 3-states all pins except VGA. If TSE0/ and TSE1/ are low with RESET high, a rising edge on CLK3 will 3-state all pins. A CLK3 rising edge without the enabling conditions exits 3-state. Note: Pin names in parentheses (.) indicate alternate functions Revision 0.6 20 Preliminary 64200 ® Register Summary REGISTER SUMMARY - CGA, MDA, AND HERCULES MODEs Register ST00 (STAT) Register Name Display Status CLPEN SLPEN Clear Light Pen Flip Flop Set Light Pen Flip Flop 0 0 W(n/a) W(n/a) MODE COLOR CGA/MDA/Hercules Mode Control CGA Color Select 7 6 HCFG Hercules Configuration 2 RW RW RW W RW RX, R0-11 R0-11 XRX, XR0-7F '6845' Registers Extension Registers Bits AccessI/O Port - MDA/Herc I/O Port - CGA 7 R 3BA 3DA 0-8 0-8 3BB (ignored) 3B9 (ignored) Comment 3DB (ignored) 3DC (ignored) ref only: no light pen ref only: no light pen 3B8 3D8 n/a 3D9 3D6-3D7 index 7E 3D6-3D7 index 7E 3BF n/a 3D6-3D7 index 14 3D6-3D7 index 14 RW RW 3B4-3B5 3D6-3D7 XR7E XR14 3D4-3D5 3D6-3D7 REGISTER SUMMARY - EGA MODE Register MSR FCR Register Name Miscellaneous Output Feature Control Bits 7 4 Access I/O Port - Mono I/O Port - Color W 3C2 3C2 W 3BA 3DA ST00 (FEAT) ST01 (STAT) Feature Read (Input Status 0) Display Status (Input Status 1) 4 7 R R 3C2 3BA 3C2 3DA CLPEN SLPEN Clear Light Pen Flip Flop Set Light Pen Flip Flop 0 0 W(n/a) W(n/a) 3BB (ignored) 3B9 (ignored) 3DB (ignored) 3DC (ignored) SRX, SR0-7 CRX, CR0-3F GRX, GR0-8 ARX, AR0-14 AR0-14 XRX, XR0-7F Sequencer CRT Controller Graphics Controller Attributes Controller Extension Registers 0-8 0-8 0-8 0-8 0-8 RW RW RW RW RW 3C4-3C5 3B4-3B5 3CE-3CF 3C0-3C1 3D6-3D7 3C4-3C5 3D4-3D5 3CE-3CF 3C0-3C1 3D6-3D7 Comment ref only: no light pen ref only: no light pen REGISTER SUMMARY - VGA MODE Register MASTER Register Name Master Control VSE SETUP ENABLE Video Subsystem Enable Setup Control Global Enable 1 2 1 MSR Miscellaneous Output 7 W R 3C2 3CC 3C2 3CC FCR Feature Control 4 W R 3BA 3CA 3DA 3CA ST00 (FEAT) ST01 (STAT) Feature Read (Input Status 0) Display Status (Input Status 1) 4 6 R R 3C2 3BA 3C2 3DA CLPEN SLPEN Clear Light Pen Flip Flop Set Light Pen Flip Flop 0 0 W(n/a) W(n/a) 3BB (ignored) 3B9 (ignored) 3DB (ignored) 3DC (ignored) DACMASK DACSTATE DACRX DACWX DACDATA Color Palette Pixel Mask 8 Color Palette State 2 Color Palette Read-Mode Index 8 Color Palette Write-Mode Index 8 Color Palette Data 0-FF 3x6 or 3x8 RW R W RW RW 3C6, 83C6 3C7, 83C7 3C7, 83C7 3C8, 83C8 3C9, 83C9 3C6, 83C6 3C7, 83C7 3C7, 83C7 3C8, 83C8 3C9, 83C9 SRX, SR0-7 CRX, CR0-3F GRX, GR0-8 ARX, AR0-14 AR0-14 XRX, XR0-7F Sequencer CRT Controller Graphics Controller Attributes Controller Extension Registers RW RW RW RW RW 3C4-3C5 3B4-3B5 3CE-3CF 3C0-3C1 3D6-3D7 3C4-3C5 3D4-3D5 3CE-3CF 3C0-3C1 3D6-3D7 Revision 0.6 Bits 8 0-8 0-8 0-8 0-8 0-8 Access I/O Port - Mono I/O Port - Color Comment W 22-23h index E0h 22-23h index E0h R/W Copy in System RW 3D6-3D7 index 03 3D6-3D7 index 03 XR03 RW 3C3 if PI 3C3 if PI Disabled by XR70 bit-6 W 46E8 if ISA 46E8 if ISA Disabled by XR70 bit-7 RW 102 if ISA 102 if ISA Setup Only 21 ref only: no light pen ref only: no light pen Preliminary 64200 ® Register Summary REGISTER SUMMARY - INDEXED REGISTERS (VGA) Register SRX SR0 SR1 SR2 SR3 SR4 SR7 Register Name Sequencer Index Reset Clocking Mode Plane Mask Character Map Select Memory Mode Reset Horizontal Character Counter CRX CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CRA CRB CRC CRD CRE CRF LPENH LPENL CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR22 CR24 CR3x CRTC Index Horizontal Total Horizontal Display End Horizontal Blanking Start Horizontal Blanking End Horizontal Retrace Start Horizontal Retrace End Vertical Total Overflow Preset Row Scan Character Cell Height Cursor Start Cursor End Start Address High Start Address Low Cursor Location High Cursor Location Low Light Pen High Light Pen Low Vertical Retrace Start Vertical Retrace End Vertical Display End Offset Underline Row Scan Vertical Blanking Start Vertical Blanking End CRT Mode Control Line Compare Graphics Controller Data Latches Attribute Controller Index/Data Latch Clear Vertical Display Enable FF GRX GR0 GR1 GR2 GR3 GR4 GR5 GR6 GR7 GR8 ARX AR0-F AR10 AR11 AR12 AR13 AR14 Register Type Access (VGA) Access (EGA) VGA/EGA RW RW VGA/EGA RW RW VGA/EGA RW RW VGA/EGA RW RW VGA/EGA RW RW VGA/EGA RW RW VGA W n/a I/O Port 3C4 3C5 3C5 3C5 3C5 3C5 3C5 6 8 8 8 5+2+1 8 5+2+1 8 5 5+2 5+3 5+1 5+2 8 8 8 8 8 8 8 4+4 8 8 5+2 8 8 7 8 8 1 0 VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA VGA VGA RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R RW RW RW RW RW RW RW RW RW R R W RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R W W RW RW RW RW RW RW RW n/a n/a n/a 3B4 Mono, 3D4 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color 3B5 Mono, 3D5 Color Graphics Controller Index Set/Reset Enable Set/Reset Color Compare Data Rotate Read Map Select Mode Miscellaneous Color Don't Care Bit Mask 4 4 4 4 5 2 6 4 4 8 VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 3CE 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF 3CF Attribute Controller Index Internal Palette Regs 0-15 Mode Control Overscan Color Color Plane Enable Horizontal Pixel Panning Color Select 6 6 7 6 6 4 4 VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA/EGA VGA RW RW RW RW RW RW RW RW RW RW RW RW RW n/a 3C0 3C0 3C0 3C0 3C0 3C0 3C0 Revision 0.6 Bits 3 2 6 4 6 3 0 22 (3C1) (3C1) (3C1) (3C1) (3C1) (3C1) (3C1) Preliminary 64200 ® Register Summary EXTENSION REGISTER SUMMARY: 00-2F 00-2F Reg Register Name XRX Extension Index Register Bits Access 7 R/W Port 3D6 Reset -xxxxxxx XR00 XR01 XR02 XR03 XR04 XR05 XR06 XR07 XR08 XR09 XR0A XR0B XR0C XR0D XR0E XR0F Chip Version Configuration CPU Interface Control Master Control (ROM Interface) Memory Control (Clock Control) (Color Palette Control / DRAM Intfc) -reserved(General Purpose Output Select B) (General Purpose Output Select A) (Cursor Address Top) CPU Paging Start Address Top Auxiliary Offset Text Mode Control (Configuration Register 2) 8 8 5 6 3 -3 1 2 2 - R/O R/O R/W R/W R/W -R/W R/W R/W R/W - 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 1010 r r r r dddddddd 00000 - - 0000 - -00 - -0 - -0 -0 XR10 XR11 XR12 XR13 XR14 XR15 XR16 XR17 XR18 XR19 XR1A XR1B XR1C XR1D XR1E XR1F Single/Low Map Register 8 High Map Register 8 -reserved-reserved-Emulation Mode 8 Write Protect 8 (Trap Enable) -(Trap Status) -Alternate H Disp End 8 Alternate H Sync Start / Half-line 8 Alternate H Sync End 8 Alternate H Total 8 Alternate H Blank Start (H Panel Size)8 Alternate H Blank End 8 Alternate Offset 8 Virtual EGA Switch Register 5 R/W R/W -R/W R/W -R/W R/W R/W R/W R/W R/W R/W R/W 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 xxxxxxxx xxxxxxxx XR20 XR21 XR22 XR23 XR24 XR25 XR26 XR27 XR28 XR29 XR2A XR2B XR2C XR2D XR2E XR2F -reserved(453 Interface II)/(SUD) -reserved(Sliding Hold A) -reserved(Sliding Hold B) -reserved(SHC)/(WBM Ctrl) (FP AltMaxScanline/SHD/WBM Patt) (FP AltGrHVirtPanel Size/453PinDefn Size/453PinDefn) -reserved(453 Config) -reservedVideo Interface -reserved(Function Control) -reserved(Frame Intrpt Count) Default Video (FP Vsync (FLM) Delay/Force H High) (FP Hsync (LP) Delay / Force H Low) (FP Hsync (LP) Delay / Force V High) (FP Hsync (LP) Width / Force V Low) -R/W -R/W - 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 -7 -8 - Chips' VGA Product Family 450 451 452 453 455 456 457 64200 65530 . . . . . . . . . . . . . . . . . . . . . . . . . . . - - -0 - - 00 00 -0 00 - - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - . . . . . . . . - . . . . . . . . . . . . . 0000hh00 00000000 . . x x x x x 0 x 0 xxx xxx xxx xxx xxx xxx xxx - - - xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx 0000 -000 00000000 R e s e t C o d e s : x = Not changed by RESET (indeterminate on power-up) d = Set from the corresponding data bus pin on falling edge of RESET h = Read-only Hercules Configuration Register Readback bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ = Not implemented (always reads 0) r = Chip revision # (starting from 0000) 0/1 = Reset to 0/1 by falling edge of RESET N o t e : Check marks in the table above indicate the register listed to the left is implemented in the chip named at the top of the column N o t e : 450­453 & 64xxx VGAs drive CRTs, 455­457 & 655x0 VGAs drive both CRT and Flat Panel displays (Plasma, EL, and LCD) Revision 0.6 23 Preliminary 64200 ® Register Summary EXTENSION REGISTER SUMMARY: 30-5F 30-5F Chips' VGA Product Family 450 451 452 453 455 456 457 64200 65530 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - - xxxxxx . . . . . . . . - - - xxxxx . . . . . . . . . . . . . . . . . . . . . . . . . . Reg XR30 XR31 XR32 XR33 XR34 XR35 XR36 XR37 XR38 XR39 XR3A XR3B XR3C XR3D XR3E XR3F Register Name Bits Access (Graphics Cursor Start Address High) -(Graphics Cursor Start Address Low) -(Graphics Cursor End Address) -(Graphics Cursor X Position High) -(Graphics Cursor X Position Low) -(Graphics Cursor Y Position High) -(Graphics Cursor Y Position Low) -(Graphics Cursor Mode) -(Graphics Cursor Mask) -(Graphics Cursor Color 0) -(Graphics Cursor Color 1) -reserved-Serial / Row Count 6 R/W Multiplexer Mode 5 R/W -reserved-reserved- Port 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 Reset XR40 XR41 XR42 XR43 XR44 XR45 XR46 XR47 XR48 XR49 XR4A XR4B XR4C XR4D XR4E XR4F -reserved(Virtual EGA Switch Register) -reserved-reserved(Software Flag Register) (Software Flag Register 2 / FG Color) - - - - 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XR50 XR51 XR52 XR53 XR54 XR55 XR56 XR57 XR58 XR59 XR5A XR5B XR5C XR5D XR5E XR5F (Panel Format) (Display Type) (Power Down Control / Panel Size) (Line Graphics Override) (FP Interface / Alternate Misc Output) (H Compensation / Text 350_A Comp) (H Centering / Text 350_B Comp) (V Compensation / Text 400 Comp) (V Centering / Graphics 350 Comp) (V Line Insertion/Graphics 400 Comp) (V Line Replication/FP VDisp St 400) -reserved(FP VDisp End 400) (Weight Control Clock A) (Weight Control Clock B) (ACDCLK Control) (Power Down Mode Refresh) - - 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . R e s e t C o d e s : x = Not changed by RESET (indeterminate on power-up) d = Set from the corresponding data bus pin on falling edge of RESET h = Read-only Hercules Configuration Register Readback bits ­ = Not implemented (always reads 0) r = Chip revision # (starting from 0000) 0/1 = Reset to 0/1 by falling edge of RESET N o t e : Check marks in the table above indicate the register listed to the left is implemented in the chip named at the top of the column N o t e : 450­453 & 64xxx VGAs drive CRTs, 455­457 & 655x0 VGAs drive both CRT and Flat Panel displays (Plasma, EL, and LCD) Revision 0.6 24 Preliminary 64200 ® Register Summary EXTENSION REGISTER SUMMARY: 60-7F 60-7F Reg XR60 XR61 XR62 XR63 XR64 XR65 XR66 XR67 XR68 XR69 XR6A XR6B XR6C XR6D XR6E XR6F Register Name (Blink Rate Control) (SmartMapTM Control) (SmartMapTM Shift Parameter) (SmartMapTM Color Mapping Control) (FP Alternate Vertical Total) (FP Alternate Overflow) (FP Alternate Vertical Sync Start) (FP Alternate Vertical Sync End) (FP V Panel Size / FP Alt V DE End) (FP V Display Start 350) (FP V Display End 350) (FP V Overflow 2) (Weight Control Clock C) (FRC Control) (Polynomial FRC Control) (Frame Buffer Control) XR70 XR71 XR72 XR73 XR74 XR75 XR76 XR77 XR78 XR79 XR7A XR7B XR7C XR7D XR7E XR7F Setup / Disable Control - Compensation Diagnostic) CGA/Hercules Color Select Diagnostic Bits Access -1 -6 8 R/W -R/W R/W Port 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 3D7 Reset 0- - - xxxxxx 00xxxx00 R e s e t C o d e s : x = Not changed by RESET (indeterminate on power-up) d = Set from the corresponding data bus pin on falling edge of RESET h = Read-only Hercules Configuration Register Readback bits Chips' VGA Product Family 450 451 452 453 455 456 457 64200 65530 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ = Not implemented (always reads 0) r = Chip revision # (starting from 0000) 0/1 = Reset to 0/1 by falling edge of RESET N o t e : Check marks in the table above indicate the register listed to the left is implemented in the chip named at the top of the column N o t e : 450­453 & 64xxx VGAs drive CRTs, 455­457 & 655x0 VGAs drive both CRT and Flat Panel displays (Plasma, EL, and LCD) Revision 0.6 25 Preliminary 64200 ® Revision 0.6 26 Preliminary 64200 ® Registers Registers Sequencer Memory Mode Register handles all memory, giving access by the CPU to 4/16/32KBytes, Odd/Even addresses (planes) and writing of data to display memory. GLOBAL CONTROL (SETUP) REGISTERS The Setup Control Register is used to enable or disable the VGA. It is also used to place the VGA in normal or setup mode. CRT CONTROLLER REGISTERS The Global and Extension Enable Registers are accessible only during Setup mode. The Global ID Register contains the ID number that identifies the 64200 as a Chips & Technologies product. The CRT Controller Index Register contains a 6-bit index to the CRT Controller Registers. Twenty eight registers perform all display functions for modes: horizontal and vertical blanking and sync, panning and scrolling, cursor size and location, light pen, and underline. Note: In setup mode in the IBM VGA, the Global Setup Register (defined as port address 102) actually occupies the entire I/O space. Only the lower 3 bits are used to decode and select this register. To avoid bus conflicts with other peripherals, reads should only be performed at the 10xh port addresses while in setup mode. To eliminate potential compatibility problems in widely varying PC systems, the 64200 decodes the Global Setup register at I/O port 102h only. GRAPHICS CONTROLLER REGISTERS The Graphics Controller Index Register contains a 4-bit index to the Graphics Controller Registers. The Set/Reset Register controls the format of the CPU data to display memory. It also works with the Enable Set/Reset Register. Reducing 32 bits of display data to 8 bits of CPU data is accomplished by the Color Compare Register. Data Rotate Registers specify the CPU data bits to be rotated and subjected to logical operations. The Read Map Select Register reduces memory data for the CPU in the four plane (16 color) graphics mode. The Graphics Mode Register controls the write, read, and shift register modes. The Miscellaneous Register handles graphics/text, chaining of odd/even planes, and display memory mapping. Additional registers include Color Don't Care and Bit Mask. GENERAL CONTROL REGISTERS Two Input Status Registers read the SENSE pin, pending CRT interrupt, display enable/HSYNC output, and vertical retrace/video output. The Feature Control Register selects the VSYNC function while the Miscellaneous Output Register controls I/O address select, clock selection, access to video RAM, memory page, and video SYNC polarity. CGA / HERCULES REGISTERS CGA Mode and Color Select registers are provided on-chip for emulation of CGA modes. Hercules Mode and Configuration registers are provided onchip for emulation of Hercules mode. ATTRIBUTE CONTROLLER AND EXTERNAL COLOR PALETTE REGISTERS The Attribute Controller Index Register contains a 5-bit index to the Attribute Controller Registers. A 6th bit is used to enable the video. The Attribute Controller Registers handle internal color lookup table mapping, text/graphics mode, overscan color, and color plane enable. The horizontal Pixel Panning and Pixel Padding Registers control pixel attributes on screen. External color palette registers handle CPU reads and writes to I/O address range 3C6h3C9h. Some of the registers are located external to the 64200 in the external color palette. Inmos IMSG176 IMSG176 (Brooktree BT471/476 BT471/476) compatible registers are documented in this manual. SEQUENCER REGISTERS The Sequencer Index Register contains a 3-bit index to the Sequencer Data Registers. The Reset Register forces an asynchronous or synchronous reset of the sequencer. The Sequencer Clocking Mode Register controls master clocking functions, video enable/disable and selects either an 8 or 9 dot character clock. A Plane/Map Mask Register enables the color plane and write protect. The Character Font Select Register handles video intensity and character generation and controls the display memory plane through the character generator select. The Revision 0.6 27 Preliminary 64200 ® Registers EXTENSION REGISTERS The 64200 uses several additional registers to support new features that are not available in an ordinary VGA. No new bits are defined and no reserved/unused bits are used in the regular VGA registers. These extended 64200 registers and the functions they control are disabled on reset. The extended registers can be accessed by two sets of control bits (disabled on reset). Access to 64200 extended registers is accomplished by putting the 64200 in VGA setup mode and setting bit-D7 of the register at I/O address 103h. Once access is enabled, extended registers can be addressed using the index/data pair of registers at I/O address 3B6h / 3B7h or 3D6h / 3D7h. In the 64200, a new extended register, 46E8 Register Override (XR70) has been implemented. When set, this register write protects setup register 103 (Extension Enable Register). This forces the extended registers to stay enabled no matter what is written to port 46E8 or the setup registers. The extension registers handle a variety of interfacing, compatibility, and display functions as discussed below. They are grouped into the following logical groups for discussion purposes: 1. Miscellaneous Registers include the 64200 Version number, Dip Switch, CPU interface, paging control, memory mode control, and diagnostic functions. 2. General Purpose Registers handle video blanking and the video default color. 3. Backwards Compatibility Registers control Hercules, MDA, and CGA emulation modes. Write Protect functions are provided to increase flexibility in providing backwards compatibility. 4. Alternate Horizontal and Vertical Registers handle all horizontal and vertical timing, including sync, blank and offset. These are used for backwards compatibility. Note: The state of most of the Standard VGA Registers is undefined at reset. All registers specific to the 64200 (Extension Registers) are summarized in the Extension Register Table. Revision 0.6 28 Preliminary 64200 ® Global Control (Setup) Registers Global Control (Setup) Registers Register Mnemonic Register Name Index Access I/O Address Protect Group Page ­ ­ Setup Control Global Enable ­ ­ W RW 46E8h 102h & Setup mode ­ ­ 29 29 SETUP CONTROL REGISTER Write only at I/O Address 46E8h GLOBAL ENABLE REGISTER Read/Write at I/O Address 102h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 VGA Sleep Reserved VGA Enable VGA Setup Reserved Reserved This register is cleared by RESET. 2-0 3 4 7-5 This register is only accessible in Setup Mode. It is cleared by RESET. Reserved (0) VGA Enable 0 VGA is disabled 1 VGA is enabled Setup Mode 0 VGA is in Normal Mode 1 VGA is in Setup Mode Reserved (0) Revision 0.6 0 7-1 29 VGA Sleep 0 VGA is disabled 1 VGA is enabled Reserved (0) Preliminary 64200 ® Revision 0.6 30 Preliminary 64200 ® General Control Registers General Control & Status Registers Register Mnemonic Register Name Index Access I/O Address Protect Group Page ST00 ST01 FCR Input Status 0 Input Status 1 Feature Control ­ ­ ­ 31 31 32 Miscellaneous Output ­ 3C2h 3BAh/3DAh 3BAh/3DAh 3CAh 3C2h 3CCh ­ ­ 5 MSR R R W R W R 5 32 INPUT STATUS REGISTER 0 (ST00) Read only at I/O Address at 3C2h INPUT STATUS REGISTER 1 (ST01) Read only at I/O Address 3BAh/3DAh D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DE/Hsync Output Reserved Vertical Retrace/Video Reserved Switch Sense Video Feedback Reserved Vsync Output Reserved CRT Interrupt Pending 3-0 4 6-5 7 0 Reserved (0) Switch Sense This bit returns the Status of the SENSE pin. Reserved (0) 2-1 CRT Interrupt Pending 0 Indicates no CRT interrupt is pending 1 Indicates a CRT interrupt is waiting to be serviced 3 5-4 Display Enable/HSYNC Output The functionality of this bit is controlled by the Emulation Mode register (XR14[4]). 0 Indicates DE or HSYNC inactive 1 Indicates DE or HSYNC active Reserved (0) Vertical Retrace/Video The functionality of this bit is controlled by the Emulation Mode register (XR14[5]). 0 Indicates VSYNC or video inactive 1 Indicates VSYNC or video active Video Feedback 1, 0 These are diagnostic video bits which are selected via the Color Plane Enable Register. 6 7 Revision 0.6 31 Reserved (0) Vsync Output The functionality of this bit is controlled by the Emulation Mode register (XR14[6]). It reflects the active status of the VSYNC output: 0=inactive, 1=active. Preliminary 64200 ® General Control Registers FEATURE CONTROL REGISTER (FCR) Write at I/O Address 3BAh/3DAh Read at I/O Address 3CAh Group 5 Protection MISCELLANEOUS OUTPUT REGISTER (MSR) Write at I/O Address 3C2h Read at I/O Address 3CCh Group 5 Protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 I/O Address Select RAM Enable Feature Control BHE/ Disable Vsync Control Clock Select Reserved Page Select Hsync Polarity Vsync Polarity Reserved 1-0 This register is cleared by RESET. 0 I/O Address Select. This bit selects 3Bxh or 3Dxh as the I/O address for the CRT Controller registers, the Feature Control Register (FCR), and Input Status Register 1 (ST01). 0 Select 3Bxh I/O address 1 Select 3Dxh I/O address 1 Enable RAM 0 Prevent CPU access to display memory 1 Allow CPU access to display memory 3-2 Clock Select. These bits usually select the dot clock source for the CRT interface: MSR3:2 = 00 = Select CLK0 MSR3:2 = 01 = Select CLK1 MSR3:2 = 10 = Select CLK2 MSR3:2 = 11 = Select CLK3 See extension register XR01 bits 2-3 (Configuration) and FCR bits 0-1 for variations of the above clock selection mapping. See also XR1F (Virtual Switch Register) for additional functionality potentially controlled by these bits. 4 Reserved (0) 5 Page Select. In Odd/Even Memory Map Mode 1 (GR6), this bit selects the upper or lower 64K byte page in display memory for CPU access: 1=select lower page; 0=select upper page. 6 CRT Hsync Polarity. 0=pos, 1=neg Feature Control When the 'OSC/' configuration bit is high (see XR01) indicating CLK1-3 are outputs, these bits determine the CLK3 (CSEL2) pin function as follows: FCR1:0 = 00 = CLK3 pin low FCR1:0 = 01 = CLK3 pin high FCR1:0 = 10 = CLK3 is Field (0=even) FCR1:0 = 11 = CLK3 is PCLK÷ 2 3 '10' is for interface to the BT484 BT484 'FLD' pin which indicates the odd or even field for the hardware cursor in interlace mode. '11' is for interface with the Music Semiconductor RAMDAC 'MUX' pin. '00' and '01' may be used to control the Sierra Semiconductor RAMDAC 'HICOLOR/' pin. Use of the CLK3 pin for RAMDAC control assumes an 82C404 82C404 programmable clock chip is being used and therefore CLK3 is not needed for clock selection. BHE/ Disable This bit may be set to disable 16-bit operations to the chip (the chip will always treat the BHE/ input as high regardless of the state of the pin if this register bit is set). Vsync Control 7-4 0 VSync output on the VSYNC pin (default) 1 Logical 'OR' of VSync and Display Enable output on the VSYNC pin This capability is not typically very useful, but is provided for IBM compatibility. Reserved (0) 2 Revision 0.6 7 32 CRT Vsync Polarity. 0=pos, 1=neg (Blank pin polarity can be controlled via the Video Interface Register, XR28) Preliminary 64200 ® CGA / Hercules Registers CGA / Hercules Registers Register Mnemonic Register Name MODE COLOR HCFG Index CGA/Hercules Mode CGA Color Select Hercules Configuration Access I/O Address Protect Group Page ­ ­ ­ RW RW RW 3D8h 3D9h 3BFh ­ ­ ­ 33 34 35 CGA / HERCULES MODE CONTROL REGISTER (MODE) Read/Write at I/O Address 3B8h/3D8h 2 0 1 3 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Res Text Graphics Mode (0=Text) Monochrome (CGA only) 4 Hi-Res Graphics (CGA only) Text Blink Enable 5 Reserved This register is effective only in CGA and Hercules modes. It is accessible if CGA or Hercules emulation mode is selected or the extension registers are enabled. If the extension registers are enabled, the address is determined by the address select in the Miscellaneous Outputs register. Otherwise the address is determined by the emulation mode. It is cleared by RESET. 0 1 1 Disable character blink attribute (blink attribute bit-7 used to control background intensity) Enable character blink attribute 6 Reserved (0) 7 Hercules Page Select 0 Select the lower part of memory (starting address B0000h) in Hercules Graphics Mode 1 Select the upper part of the memory (starting address B8000h) in Hercules Graphics Mode CGA 80/40 Column Text Mode 0 1 Select 320x200 graphics mode Select 640x200 graphics mode CGA/Hercules Text Blink Enable 0 (Herc only) Blank the screen Enable video output CGA High Resolution Mode 0 1 Video Enable Select CGA color mode Select CGA monochrome mode CGA/Hercules Video Enable 0 1 (CGA only) Page Select CGA Mono/Color Mode Select 40 column CGA text mode Select 80 column CGA text mode CGA/Hercules Graphics/Text Mode 0 1 Revision 0.6 Select text mode Select graphics mode 33 Preliminary 64200 ® CGA / Hercules Registers CGA COLOR SELECT REGISTER Read/Write at I/O Address 3D9h 640x200 2-color: D7 D6 D5 D4 D3 D2 D1 D0 The background color (the color displayed when the pixel value is 0) is black. Color bit-0 (Blue) Color bit-1 (Green) Color bit-2 (Red) Color bit-3 (Intensity) Intensity Enable Color Set Select 4 320x200 4-color: 640x200 2-color: 5 This register is effective only in CGA modes. It is accessible if CGA emulation mode is selected or the extension registers are enabled. This register may also be read or written as an Extension Register (XR7E). It is cleared by RESET. 3-0 Enables intensified background colors Enables intensified colors 0-3 Don't care Color Set Select This bit selects one of two available CGA color palettes to be used in 320x200 graphics mode (it is ignored in all other modes) according to the following table: Pixel Value Color 320x200 4-color: Background Color (color when the pixel value is 0) The foreground colors (colors when the pixel value is 1-3) are determined by bit-5 of this register. Revision 0.6 Intensity Enable Text Mode: Reserved Foreground Color (color when the pixel value is 1) 0 0 1 1 7-6 34 0 1 0 1 Color Set 0 Color Set 1 Color per bits 0-3 Green Red Brown Color per bits 0-3 Cyan Magenta White Reserved (0) Preliminary 64200 ® CGA / Hercules Registers HERCULES CONFIGURATION REGISTER (HCFG) Write only at I/O Address 3BFh D7 D6 D5 D4 D3 D2 D1 D0 Enable Graphics Mode Enable Memory Page 1 Reserved This register is effective only in Hercules mode. It is accessible in Hercules emulation mode or if the extension registers are enabled. It may be read back through XR14 bits 2 & 3. It is cleared by RESET. 0 Enable Graphics Mode 0 1 1 Enable Memory Page 1 0 1 7-2 Lock the 64200 in Hercules text mode. In this mode, the CPU has access only to memory address range B0000h-B7FFFh (in text mode the same area of display memory wraps around 8 times within this range such that B0000 B0000 accesses the same display memory location as B1000 B1000, B2000 B2000, etc.). Permit entry to Hercules Graphics mode. Prevent setting of the Page Select bit (bit 7 of the Hercules Mode Control Register). This function also restricts memory usage to addresses B0000hB7FFFh. The Page Select bit can be set and the upper part of display memory (addresses B8000h - BFFFFh) is available. Reserved (0) Revision 0.6 35 Preliminary 64200 ® Revision 0.6 36 Preliminary 64200 ® Sequencer Registers Sequencer Registers Register Mnemonic Register Name SRX SR00 SR01 SR02 SR03 SR04 SR07 Index Access I/O Address Sequencer Index Reset Clocking Mode Plane/Map Mask Character Font Memory Mode Horizontal Character Counter Reset ­ 00h 01h 02h 03h 04h 07h RW RW RW RW RW RW W Protect Group Page 3C4h 3C5h 3C5h 3C5h 3C5h 3C5h 3C5h 1 1 1 1 1 1 ­ SEQUENCER INDEX REGISTER (SRX) Read/Write at I/O Address 3C4h SEQUENCER RESET REGISTER (SR00) Read/Write at I/O Address 3C5h Index 00h Group 1 Protection D7 D6 D5 D4 D3 D2 D1 D0 37 37 38 38 39 40 40 D7 D6 D5 D4 D3 D2 D1 D0 Sequencer Index Async Reset Sync Reset Reserved Reserved 0 This register is cleared by RESET. 2-0 Sequencer Index 7-3 These bits contain a 3-bit Sequencer Index value used to access sequencer data registers at indices 0 through 7. Reserved (0) Display memory data will be corrupted if this bit is set to zero. 1 7-2 Revision 0.6 Asynchronous Reset 0 Force asynchronous reset 1 Normal operation 37 Synchronous Reset 0 Force synchronous reset 1 Normal operation Display memory data is not corrupted if this bit is set to zero for a short period of time (a few tens of microseconds). Reserved (0) Preliminary 64200 ® Sequencer Registers SEQUENCER CLOCKING MODE REGISTER (SR01) Read/Write at I/O Address 3C5h Index 01h Group 1 Protection SEQUENCER PLANE/MAP MASK REGISTER (SR02) Read/Write at I/O Address 3C5h Index 02h Group 1 Protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 8/9 Dot Clocks Reserved Shift Load Input Clock Divide Shift 4 Screen Off Color Plane Enable Reserved Reserved 0 8/9 Dot Clocks This bit determines whether a character clock is 8 or 9 dot clocks long. 0 Select 9 dots/character clock 1 Select 8 dots/character clock 1 Color Plane Enable 0 1 Write protect corresponding color plane Allow write to corresponding color plane. In Odd/Even and Quad modes, these bits still control access to the corresponding color plane. Reserved (0) 2 3-0 Shift Load 0 Load video data shift registers every character clock 1 Load video data shift registers every other character clock 7-4 Reserved (0) Bit-4 of this register must be 0 for this bit to be effective. 3 Input Clock Divide 0 Sequencer master clock output on the PCLK pin (used for 640 (720) pixel modes) 1 Master clock divided by 2 output on the PCLK pin (used for 320 (360) pixel modes) 4 Shift 4 0 Load video shift registers every 1 or 2 character clocks (depending on bit-2 of this register) 1 Load shift registers every 4th character clock. 5 Screen Off 0 Normal Operation 1 Disable video output and assign all display memory bandwidth for CPU accesses Reserved (0) 7-6 Revision 0.6 38 Preliminary 64200 ® Sequencer Registers CHARACTER FONT SELECT REGISTER (SR03) Read/Write at I/O Address 3C5h Index 03h Group 1 Protection The following table shows the display memory plane selected by the Character Generator Select A and B bits. Code 0 1 2 3 4 5 6 7 D7 D6 D5 D4 D3 D2 D1 D0 Font Font Font Font Font Font Select Select Select Select Select Select B B A A B A bit-1 bit-2 bit-1 bit-2 bit-0 bit-0 Character Generator Table Location First 8K of Plane 2 Second 8K of Plane 2 Third 8K of Plane 2 Fourth 8K of Plane 2 Fifth 8K of Plane 2 Sixth 8K of Plane 2 Seventh 8K of Plane 2 Eighth 8K of Plane 2 where 'code' is: Character Generator Select A (bits 3, 2, 5) when bit-3 of the the attribute byte is one. Character Generator Select B (bits 1, 0, 4) when bit3 of the attribute byte is zero. Reserved In text modes, bit-3 of the video data's attribute byte normally controls the foreground intensity. This bit may be redefined to control switching between character sets. This latter function is enabled whenever there is a difference in the values of the Character Font Select A and the Character Font Select B bits. If the two values are the same, the character select function is disabled and attribute bit3 controls the foreground intensity. SR04 bit-1 must be 1 for the character font select function to be active. Otherwise, only character fonts 0 and 4 are available. 1-0 High order bits of Character Generator Select B 3-2 High order bits of Character Generator Select A 4 Low order bit of Character Generator Select B 5 Low order bit of Character Generator Select A 7-6 Reserved (0) Revision 0.6 39 Preliminary 64200 ® Sequencer Registers SEQUENCER MEMORY MODE REGISTER (SR04) Read/Write at I/O Address 3C5h Index 04h Group 1 Protection SEQUENCER HORIZONTAL CHARACTER COUNTER RESET (SR07) Read/Write at I/O Address 3C5h Index 07h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved Extended Memory Odd/Even Mode Quad Four Mode Don't Care Reserved 0 1 Writing to SR07 with any data will cause the horizontal character counter to be held reset (character counter output = 0) until a write to any other sequencer register with any data value. The write to any index in the range 0-6 clears the latch that is holding the reset condition on the character counter. Reserved (0) Extended Memory 0 Restrict CPU access to 4/16/32 Kbytes 1 Allow complete access to memory This bit should normally be 1. 2 Odd/Even Mode The vertical line counter is clocked by a signal derived from horizontal display enable (which does not occur if the horizontal counter is held reset). Therefore, if the write to SR07 occurs during vertical retrace, the horizontal and vertical counters will both be set to zero. A write to any other sequencer register may then be used to start both counters with reasonable synchronization to an external event via software control. 0 CPU accesses to Odd/Even addresses are directed to corresponding odd/even planes 1 All planes are accessed simultaneously (IRGB color) Bit-3 of this register must be 0 for this bit to be effective. This bit affects only CPU write accesses to display memory. 3 This is a standard VGA register which was not documented by IBM. Quad Four Mode 0 CPU addresses are mapped to display memory as defined by bit-2 of this register 1 CPU addresses are mapped to display memory modulo 4. The two low order CPU address bits select the display memory plane. This bit affects both CPU reads and writes to display memory. 7-4 Reserved (0) Revision 0.6 40 Preliminary 64200 ® CRT Controller Registers CRT Controller Registers Register Mnemonic Register Name CRX CR00 CR01 CR02 CR03 CR04 CR05 CR06 CR07 CR08 CR09 CR0A CR0B CR0C CR0D CR0E CR0F CR10 CR11 CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR22 CR24 CR3x Index CRTC Index Horizontal Total Horizontal Display Enable End Horizontal Blank Start Horizontal Blank End Horizontal Sync Start Horizontal Sync End Vertical Total Overflow Preset Row Scan Maximum Scan Line Cursor Start Scan Line Cursor End Scan Line Start Address High Start Address Low Cursor Location High Cursor Location Low Vertical Sync Start (See Note 2) Vertical Sync End (See Note 2) Lightpen High (See Note 2) Lightpen Low (See Note 2) Vertical Display Enable End Offset Underline Row Vertical Blank Start Vertical Blank End CRT Mode Control Line Compare Memory Data Latches Attribute Controller Toggle Clear Vertical Display Enable Access I/O Address ­ 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 10h 11h 12h 13h 14h 15h 16h 17h 18h 22h 24h 3xh RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW W or RW W or RW R R RW RW RW RW RW RW RW R R W 3B4h/3D4h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h 3B5h/3D5h Protect Group Page ­ 0 0 0 0 0 0 0 0/3 3 2/4 2 2 ­ ­ ­ ­ 4 3/4 ­ ­ 4 3 3 4 4 3/4 3 ­ ­ ­ 42 42 42 43 43 44 44 45 45 46 46 47 47 48 48 48 48 49 49 49 49 50 50 50 51 51 52 53 54 54 54 Note 1: When MDA or Hercules emulation is enabled, the CRTC I/O address should be set to 3B4h-3B5h by setting the I/O address select bit in the Miscellaneous Output register (3C2h/3CCh bit-0) to zero. When CGA emulation is enabled, the CRTC I/O address should be set to 3D4h-3D5h by setting Misc Output Register bit-0 to 1. Note 2: In the EGA, all CRTC registers except the cursor (CR0C-CR0F) and light pen (CR10 and CR11) registers are write-only (i.e., no read back). In both the EGA and VGA, the light pen registers are at index locations conflicting with the vertical sync registers. This would normally prevent reads and writes from occurring at the same index. Since the light pen registers are not normally useful, the VGA provides software control (CR03 bit-7) of whether the vertical sync or light pen registers are readable at indices 10-11. Revision 0.6 41 Preliminary 64200 ® CRT Controller Registers CRTC INDEX REGISTER (CRX) Read/Write at I/O Address 3B4h/3D4h HORIZONTAL DISPLAY ENABLE END REGISTER (CR01) Read/Write at I/O Address 3B5h/3D5h Index 01h Group 0 protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 CRTC Index Horizontal Displayed Reserved 5-0 CRTC data register index 7-6 Reserved (0) This register is used for all VGA and EGA modes on CRTs. It is also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. HORIZONTAL TOTAL REGISTER (CR00) Read/Write at I/O Address 3B5h/3D5h Index 00h Group 0 protection 7-0 Horizontal Displayed This register should be programmed to hold the number of characters displayed per scan line ­ 1. D7 D6 D5 D4 D3 D2 D1 D0 Horizontal Total This register is used for all VGA and EGA modes. It is also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. 7-0 Horizontal Total Total number of character clocks per line = contents of this register + 5. This register determines the horizontal sweep rate. Revision 0.6 42 Preliminary 64200 ® CRT Controller Registers HORIZONTAL BLANK START REGISTER (CR02) Read/Write at I/O Address 3B5h/3D5h Index 02h Group 0 protection HORIZONTAL BLANK END REGISTER (CR03) Read/Write at I/O Address 3B5h/3D5h Index 03h Group 0 protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 H Blank End H Blank Start DE Skew Control Light Pen Reg. Enable This register is used for all VGA and EGA modes. It is also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. This register is used for all VGA and EGA modes. It is also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. 7-0 4-0 Horizontal Blank Start Horizontal Blank End These are the lower 5 bits of the character clock count used to define the end of horizontal blank. The interval between the end of horizontal blank and the beginning of the display (a count of 0) is the left side border on the screen. If the horizontal blank width desired is W clocks, the 5-bit value programmed in this register = [contents of CR02 + W] and 1Fh. The most significant bit is programmed in CR05 bit-7. This bit = [( CR02 + W) and 20h]/20h. These bits specify the beginning of horizontal blank in terms of character clocks from the beginning of the display scan. The period between Horizontal Display Enable End and Horizontal Blank Start is the right side border on screen. 6-5 Display Enable Skew Control Defines the number of character clocks that the Display Enable signal is delayed to compensate for internal pipeline delays. 7 Light Pen Register Enable Must be 1 for normal operation; when this bit is 0, CRTC registers CR10 and CR11 function as lightpen readback registers. Revision 0.6 43 Preliminary 64200 ® CRT Controller Registers HORIZONTAL SYNC START REGISTER (CR04) Read/Write at I/O Address 3B5h/3D5h Index 04h Group 0 protection HORIZONTAL SYNC END REGISTER (CR05) Read/Write at I/O Address 3B5h/3D5h Index 05h Group 0 protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Horizontal Sync End Horizontal Sync Start Horizontal Sync Delay H Blank End Bit 5 This register is used for all VGA and EGA modes. It is also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. This register is used for all VGA and EGA modes. It is also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. 7-0 4-0 Horizontal Sync Start Horizontal Sync End Lower 5 bits of the character clock count which specifies the end of Horizontal Sync. If the horizontal sync width desired is N clocks, then these bits = (N + contents of CR04) and 1Fh. These bits specify the beginning of Hsync in terms of Character clocks from the beginning of the display scan. These bits also determine display centering on the screen. 6-5 Horizontal Sync Delay These bits specify the number of character clocks that the Horizontal Sync is delayed to compensate for internal pipeline delays. 7 Horizontal Blank End Bit 5 Sixth bit of the Horizontal Blank End Register (CR03). Revision 0.6 44 Preliminary 64200 ® CRT Controller Registers VERTICAL TOTAL REGISTER (CR06) Read/Write at I/O Address 3B5h/3D5h Index 06h Group 0 protection OVERFLOW REGISTER (CR07) Read/Write at I/O Address 3B5h/3D5h Index 07h Group 0 protection on bits 0-3 and bits 5-7 Group 3 protection on bit 4 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 V Total Bit 8 V DE End Bit 8 V Sync Start Bit 8 V Blank Start Bit 8 Line Compare Bit 8 V Total Bit 9 V DE End Bit 9 V Sync Start Bit 9 V Total (Scan Lines) (Lower 8 Bits) This register is used in all modes. This register is used in all modes. Vertical Total 0 Vertical Total Bit 8 These are the 8 low order bits of a 10-bit register. The 9th and 10th bits are located in the CRT Controller Overflow Register. The Vertical Total value specifies the total number of scan lines (horizontal retrace periods) per frame. 1 Vertical Display Enable End Bit 8 2 Vertical Sync Start Bit 8 3 Vertical Blank Start Bit 8 4 Line Compare Bit 8 5 Vertical Total Bit 9 6 Vertical Display Enable End Bit 9 7 7-0 Vertical Sync Start Bit 9 Programmed Count = Actual Count ­ 2 Revision 0.6 45 Preliminary 64200 ® CRT Controller Registers PRESET ROW SCAN REGISTER (CR08) Read/Write at I/O Address 3B5h/3D5h Index 08h Group 3 Protection MAXIMUM SCAN LINE REGISTER (CR09) Read/Write at I/O Address 3B5h/3D5h Index 09h Group 2 protection on bits 0-4 Group 4 Protection on bits 5-7 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Start Row Scan Count Byte Panning Control Reserved 4-0 Scan Lines Per Row V Blank Start Bit 9 Line Compare Bit 9 Double Scan 4-0 Start Row Scan Count These bits specify the number of scan lines in a row: Number of scan lines per row = value + 1. These bits specify the starting row scan count after each vertical retrace. Every horizontal retrace increments the character row scan line counter. The horizontal row scan counter is cleared at maximum row scan count during active display. This register is used for soft scrolling in text modes. 6-5 5 Bit 9 of the Line Compare register 7 Double Scan 0 Normal Operation 1 Enable scan line doubling Byte Panning Control The vertical parameters in the CRT Controller (even for a split screen) are not affected, only the CRTC row scan counter (bits 0-4 of this register) and display memory addressing screen refresh are affected. Reserved (0) Revision 0.6 Bit 9 of the Vertical Blank Start register 6 These bits specify the lower order bits for the display start address. They are used for horizontal panning in Odd/Even and Quad modes. 7 Scan Lines Per Row 46 Preliminary 64200 ® CRT Controller Registers CURSOR START SCAN LINE REGISTER (CR0A) Read/Write at I/O Address 3B5h/3D5h Index 0Ah Group 2 Protection CURSOR END SCAN LINE REGISTER (CR0B) Read/Write at I/O Address 3B5h/3D5h Index 0Bh Group 2 protection D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Cursor Start Scan Line Cursor End Scan Line Cursor off Cursor Delay Reserved Reserved 4-0 4-0 Cursor Start Scan Line These bits specify the scan line of a character row where the cursor display ends: Last scan line for the block cursor = Value + 1. These bits specify the scan line of the character row where the cursor display begins. 5 7-6 Cursor End Scan Line 6-5 Cursor Off 0 Text Cursor On 1 Text Cursor Off Cursor Delay These bits define the number of character clocks that the cursor is delayed to compensate for internal pipeline delay. Reserved (0) 7 Reserved (0) Note: If the Cursor Start Line is greater than the Cursor End Line, then no cursor is generated. Revision 0.6 47 Preliminary 64200 ® CRT Controller Registers START INDEX HIGH REGISTER (CR0C) Read/Write at I/O Address 3B5h/3D5h Index 0Ch CURSOR LOCATION HIGH REGISTER (CR0E) Read/Write at I/O Address 3B5h/3D5h Index 0Eh D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Display Start Index High (Upper 8 bits) 7-0 Text Cursor Mem. Index (Upper 8 bits) Display Start Index High 7-0 Upper 8 bits of display start address. In CGA/MDA/Hercules modes, this register wraps around at the 16, 32, and 64 Kbyte boundaries respectively. Text Cursor Memory Index High Upper 8 bits of the memory address where the text cursor is active. In CGA/MDA/Hercules modes, this register wraps around at 16, 32, and 64 Kbyte boundaries respectively. START INDEX LOW REGISTER (CR0D) Read/Write at I/O Address 3B5h/3D5h Index 0Dh CURSOR LOCATION LOW REGISTER (C