MH4171D MC3417 MC3517 MC3418 MC3518 MC351 MC3417/MC3517 62O-1O 751G-01 SQ-16L - Datasheet Archive

 

From Motorola h4fax Ph: 602-244+591 Fax: 602+444693 To Wolfgang Perto Id Oznl Order this data sheet by MH4171D MC3417,MC3517

 

08[18B8 00:53 From Motorola h4fax Ph: 602-244+591 Fax: 602+444693 To Wolfgang Perto Id Oznl Order this data sheet by MH4171D MH4171D MC3417 MC3417,MC3517 MC3517 MC3418 MC3418,MC3518 MC3518 * e `. . .' CONTINUOUSLY VARIABLE SLOPE DELTA MODULATOR/DEMODULATOR Providing decoding, secure - the a simplified communication A single IC provides q and to Input commercia[ both encoding Encode and Decode a Qigita[ approach digital speech encoding/ MC351 MC351 7/78 series of CVSDS is designed for militay Functions telephone applications. and decoding functions. on the Same Chip with . P Sumx PMS~C PACWGE CASE M-06 L SUFFK for Selection /.*}, i:+t .:$~: \/$> , ~ CMOS Compatible Digital Output *J,*:.$v ,*_ "~v%h .,., ,>, f?~- *$ *\:~> - - ~ + `~$. ,.* - *1.O - - %?.0 - - =1.3 - - =1.3 - & 2.5 = 4.0 = 4.5 =5.5 0.1 Vcc - 1.0 Vcc -0.2 + 3.2 Syilatic Pi!ter Appfied Voltage (Pin ,~~ (Rgure 2} vth -0.4 18 & 6.0 = 8.0 510 - 0.4 - - Vcc­ 1.0 - Vcc + 3.2 8.o 10 1.45 1.5 12 1.55 - 3.0 - 3.25 rrrv - 0.1 0.4 ICc-a.z - Vcc 8.0 1.4 1.42 2;5 vth -0.4 18 2.75 - 12 1,55 1.58 3.25 VO{AV*) - = 100 = 250 - - - = 100 = 100 = 250 = 280 ltH - - :., Digital Oata tnput Cfock !nput Encode/Decode tnvut I Clock tnput. VIL =" 0.4 V +5.0 + 5.0 + 5.0 -( - - - - - - - - -lo -360 -36 -72 - - - - - - - - NO= 2. @narnic Iotal loop offset (lVoff~etl equals VIO {comparator) {Rgure 3} minus VIOX (Hgu m 5). The inpm offset vo[tages and of me integrator amplifier include the effems of input offset current through the input resistors. The slope polarity aPPears as an avera9ev0ita9e aCrossthe 10 k integrator resistor. For the MWT71MC3517 MWT71MC3517, the ctock frequency is M~518, the clock frequen~ is 32 kHz. Idle channel performance is guaranteed if this dynamic Iotal Ioop offset is change in integrator output voltage durrrrg one clock cycle (ramp $!ep size). Laser trimming I - - .- @ MOTOROLA -lo -360 -36 -72 of the analog com~arator witch current mismatch 16 kHz. For the MC3418/ MC3418/ Iesg than ~ne.~alf Of the is used 10 insure good idle channel performance. Semiconductor Products Inc. 3 + 5.0 + 5.0 + 5.0 08/1 8B8 00:53 From Motorola fvffax Ph: 602-2444591 DEFIN~ONS Fax: 602-2444693 To Wolfgang Pertold 05E1 AND FUNCTION OF PINS . the encode mode or when the digital data input : P . ,.i lPin 13) is high in the decode mode. For the opposite states, Ilnt flows out of Pin 6. Single integration systems require a capacitor and resistor between Pins 6 and 7. Multipole configurations will have different circuitry. The resistance between Pins 6 and 7 should always be between 8.0 k~ a nd 13 k~ to maintain good idle channel characteristics. "': ," \.:$,( l'.l'\:t*;.>.,\:;*.} . .$\,)+,. . .,.,., ~ ,~. Wn 7 - Analag Output ,." This is the integrator OP amp output. It is+.&~@e of driving a 600-ohm load referenced t@#~}~ to amp + 6.0 dBrn and can otherwise be treate~g~~~~pp output. Pins 5, 6, and 7 provide full ac&@,$P''the inte" grater op amp for designing int@&&*' filter networks. The slew rate of the in$~rn~a$compensated integrator op amp is typically~~~~V/&s. Pin 7 output is current limited for both R*~Q~l& of current ffow at ~>$:$ .P* :Ci typically 30 mA. ,. * \k. .' \"'.:>. . >,.*., ,:,.$,}, " ,.,?. .y:,.&+\>, ` Pin 8 - VEE The circuit is de~ped:'b work in either single or dual Pin 1 - Analog Input This is the analog comparator inverting input where the voice signal is applied. it may be ac or dc coupled depending an the appiicatian. If the voice signal is to be ievel shifted to the internal reference voltage, then a bias resistor between Pins 1 and 10 is used. The resistor is used to establish the reference as the new dc average of the ac coup!ed signal. The analog comparator was designed for low hysteresis (typically less than 0.1 mV) and high gain (typically TO dB). Pin 2 - Analog Feedback This is the noninverting input to the analog signal comparator within the IC. In an encoder application it should be connected to the analog output of the errcoder circuit This may be Pin 7 or a low pass filter output connected to Pin 7. In a decode circuit Pin 2 is not used and may be tied to VCC/2 on Pin 10, ground or Ieft open. .- .,The analog input comparator .has. bias currenof 1.5 WA max, thus the driving impedances of Pins 1 and 2 should be equal to avoid disturbing Che idle channel characteristics of the encoder. Power SUPP[Y h$~,&hns. Pin 8 is always connected to the most n~a~@ supply. \\+- .>%.*.?.J:, 4:'? Rn 3 - Syllabic Filter Thi$ is the point at which the syllabic filter voltage is returned to the IC in order to control the integrator step size. It is an NPN input to an OP amp. The syllabic filter consists of an RC network between Pins 11 and 3. Typical time constant values of 6.0 ms to 50 ms are used in voice codecs. Pin9- ,D#Jgai output The,r$~gital" `output provides the results of the delta .> .:., , m~&~,~t&Es conversion. it swings between VCC and ~~a@ is CMOS or TTL compatible. Pin 9 is inverting .l,w$f~spem to Pin 1 and non-invertina with resoect to `X:#~r2. It is clocked on the faIIina edg~ of Pin 14. The ~pical 10% to 90% rise and fall-tim;s are 250 ns and Pin 4 - Gain Control Input 50 ns respectively for VCC = 12 V and CL = 25 pF to The syllabic filter voltage appears across Cs of ths$, ground. syllabic filter and is the voltage between VCC .@N, "~> - .$y,:,*,!.* Q+w Pin 3. The active voltage to current (V-1) coqyew~ drives Pin 4 to the same voltage at a sle~$$$~k,~~ Pin 10 - vcc/2 output An internal low impedance mid-supply reference is typically 0.5 V/Ws. Thus the current injecteQ,~@~ 4 provided for use of the MC3417/18 MC3417/18 in single supply [IGc) is the syllabic filter voltage dividq~~~$the Rx resistance. Figure 7 shows the relatiq+$h$~"'beween applications. The interns I regulator is a current source and must be loaded with a resistorto insure its sinking IGC (x-axis) and the integrating CU@n$-#~t {Y-aXiS). The discrepancy, which is mos~ ~QH%@nt at verv low capability. If a +6.0 dBrno signal is expected across slope polarity currents, is due to circuitry wl~in'$he a 600 ohm input bias resistor, then Pin 10 must sink 2.2 VJ600 VJ600 Q = 3.66 mA. This is only possible if Pin 10 switch which enables trim~$m~:'$~~ a iow total loop sources 3.66 mA into a resistor normally" and will offset. The Rx resistor is theh~.$~ed to adjust the 10oP source only the difference under peak load. The refgain of the codec, but @~,uld be no larger than 5.0 k~ erence load resistor is chosen accordingly. A 0.1 PF to maintain stability. $~~$$F'& `~l:. \ bypass capacitor from Pin 10 to VEE is also recom{k 5 10 k 11 6 0.05 PF r .7. ~ . Note: .'0 B 1 g I"'M' = The analog comparator Off Sat vo~taga is tested under dynamic conditions and th@r@f~r* must be measured FIGURE 5- with appropriate V/[ CONVERTER ., . . ., . G fi Itering. OFFSET VOLTAGE, Vlo and VIQX ~s .?;:! \ t?.< *32 k~Z 16 kHz MC3418/MC3518 MC3418/MC3518 MC3417fMC3617 v~c v~c ? .~?.\ , ,\.\/, ,:~,. . C `. MOTOROLA @ Semiconductor Pmducfs Inc. 8 . 08i18m8 From 00:53 . Motorola Mfax Ph: 602-2444591 .: . ., FIGURE 14-16 kHz SIMPLEX VOICE tional conversion distance Signa~&~~~e{~atios digital trqs%~~on easier to design. The do ~. the nature of+~~e'~t stream without changing the channel bit rate. ,~p,t"-.SL},< ,$:., . a[gorithm is that it provid@,)i~.:~a$ure the fre. gain of the on the there output voltage accepted the is, for charges The be taken the integrator. - that not $, e . .> gain of the output control. simplicity rithms the analog input by the nyquist are The its output. delta bit rate. The are governed capabilities the to accurately digital limited of The that coincidence the integrator controls modulator or upldown The Commanding Algorithm advantages it indicates small. a single pole low pass filter. ~3 shows the corresponding decoder block diagram. The fundamental - if it contains 12 shows the delta modu- Figure {cantinud} when the framing a delta modulator Similarly bit errors. lator waveforms CVSD begins without DESCRIPTION for digitizing is especially algorithm a voice input convenient for digital requirements. lNFORMATtON CONSIDERATIONS ,.;,' j.: ~~ ".ik?,~> \,+ the MC3417 MC3417 or MC~18 A simple CVSD enQ,@[{~ii9 [CS are 9en@ral Pumose is shown in Figur@ri~~: *ese CVSD building ~~W#tihich allow the system designer ,$, .,. \ transmission chara~eristics to to tailor the Wwkr's 2. Required number 3. Selection of loop gain 4. Selection of minimum the applic~~~~~hus, 6. Design of syllabic the achievable transmission 5. Design of integration capsr- seven of the design MC3417 MC3417 considerations and MC3418 MC3418. involved There application, and they 1. Selection of clock The circuit possible. are intelligible in designing these basic CVSD building blocks into a specific sufficient. codec their are as follows: are rate For filter transfer voice simplest both ? through 10 in Figure many function function 14 is the most basic CVSD applications channel In this circuit, form. single pole The requirements, items syllabic networks. Prducb circuit in secure radio or other it is entirelY 5 and 6 are reduced and integration The selection 4 govern the codec performance. Semiconductor @ step size filter transfer 7. Design of low pass filter at the receiver bilities.;w~strained by the fundamental limitations ,.*,., of del&/@&dulation and the design of encoder paramy,~$.~k ete~q$rxtik performance is not dictated by the internal confl~uration of shift register bits inc. of to filters . . items L 9 Oigitai Qulput Coincldenca output 4 Gain Control Sv?labic F ii ter G, - IK"W=, Oecodo - ,.>. . - - 4 1 f' " `I,.mlti T IOA I = 5A 6A vc~i2 Ref Filter output Inpul Input 8A VEE 08/18&8 00:53 From Motorola Mfax Ph: 602-244+591 CVSD Layout DESIGN CONSIDERATIONS Considerations Care should to isolate all digital of the circuit in Figure Rx. Rx must be selected (Pins 9, 11, 13, and 14) from analog signal paths paths ,., ., P - .$ of Loop Gain The gain signal to provide step size for high level signals (Wrr$ 1-7 and 10} in order to achieve proper idle channel ratio does not exceed petiormance. 13RI Pertold (continued} Selection be exercised To Wolfgang Fax: 602-2444693 about 14 is set by resistor the proper integrator such that the ampanding 25Y0. The commanding ratio is the active low duty cycleof the coincidence output on ClOck Rate With may Rn 11of the codec circuit Thus the system gain is dep~, minor be modifications operated the anywhere circuit from 9.6 in Figure kHz to 14 kHz 64 clock rates. Obviously the higher the clock rate the higher the S/N performance. produces The the S/N selection bandwidth of the systems Some radio telephone systems at 32K rate require will are higher allow Figure Voice than 12 kHz. operated useful dynamic HZ. level. 4-wire 16 kHz Other may To use bit rates codecs achieved filter. W*TH SINGLE AND COMMANDING [ I INTEGRATION, I I I I I I I { - 15 ~- - I I / I clock /; Rate :16 kHz respo;se / from move the I / co,rnw~ng ratio should not \$\+. .+{:(J. k$i,\, .J$ ,y>+ ~ ~ $.,i req~~,~,~~p size current, we must of the w~~eristic$ of Figure integra~iors 14, a single pole of -'$ J?a? Note that the integration filter produces I I I 10 the tran$fer ,$, $;~fiN The sign81 to rsoise results of the active c@@ing network are shown in Figure 19. A smootktZi@J~roP is realized from +12 dBrn to -24 under t{@''~i&&$ol of Al. At -24 dBm, A2 begins to degene,w~%~~$companding so as to reference and the resulting step siz&~s U@uced RESPONSE (Wowing the improvement tie CARRIER ma] ized with cimuit in Figuro 18.) a. SIGNAL-TO-NOISE PERFORMANCE OF TELEPHONY QUALITY DELTAMODULATOR 35 I m u 4 BIT ALGORITHM 3?.?K 1 kHz B ITS TEST C MESSAGE TONE WEIGHT extend the dynamic range o{p~~