500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
PCI-T64-E2-U6 Lattice Semiconductor Corporation PCI TARGET 64BIT EC/ECP visit Digikey Buy
PCI-T32-E3-U6 Lattice Semiconductor Corporation IP CORE PCI TARGET 32BIT ECP3 visit Digikey Buy
PCI-MT32-E2-U6 Lattice Semiconductor Corporation IP PCI MASTER/TARGET 32B EC/ECP visit Digikey Buy
PCI-T32-XM-UT6 Lattice Semiconductor Corporation SITE LICENSE PCI TARGET 32BIT XP visit Digikey Buy
PCI-T32-X2-UT6 Lattice Semiconductor Corporation SITE LICENSE PCI TARGET 32B XP2 visit Digikey Buy
PCI-T64-XM-U6 Lattice Semiconductor Corporation IP CORE PCI TARGET 64BIT XP visit Digikey Buy

pci target

Catalog Datasheet MFG & Type PDF Document Tags

NOR flash controller vhdl code

Abstract: NOR Flash design. Features · Supports 33-MHz,32-bit PCI target functions with PCI Local Bus Specification Rev , Flash data sheet The reference design does not support the following features: · PCI target interface , register space ­ Cache line register ­ Interrupt signal from PCI target to PCI initiator · NOR Flash , of the PCI target that completes the current configuration cycle on the PCI bus. pci_frame_l , Output Low The PCI target drives this signal low prior to the positive edge of a clock when it can
Lattice Semiconductor
Original

Verification Using a Self-checking Test Bench

Abstract: ispMACH M4A3 Designing a 33MHz, 32-Bit PCI Target Using ispMACH Devices July 2001 Reference Design RD1008 , a 33MHz, 32-bit PCI target for ispMACHTM devices. It is designed to provide users with a starting point for designing a PCI target into a Lattice CPLD. The reference design source code is available from Lattice upon the signing of a simple non-disclosure agreement. The 33MHz, 32-bit PCI target , modifications · A fully automated and self-checking HDL test bench for ease of verification The PCI Target
Lattice Semiconductor
Original
Verification Using a Self-checking Test Bench ispMACH M4A3 signal path designer M4A3-384/192-65AC M4A3384/192-65AC 1-800-LATTICE

CODE VHDL TO ISA BUS INTERFACE

Abstract: Signal path designer Designing a 33MHz, 32-Bit PCI Target Using Lattice Devices January 2010 Reference Design , design solution for a 33MHz, 32-bit PCI target for LatticeXP2TM, MachXOTM and ispMACH® devices. It is designed to provide users with a starting point for designing a PCI target into Lattice devices. The , . The 33MHz, 32-bit PCI target reference design comes with a fully-automated HDL test environment and , self-checking HDL test bench for ease of verification The PCI Target does not support the following features
Lattice Semiconductor
Original
PCI33 LCMXO1200 LCMXO2280 CODE VHDL TO ISA BUS INTERFACE verilog hdl code for multiplexer 4 to 1 vhdl code for 32bit parity generator XO1200 XO2280

vhdl code for a 9 bit parity generator

Abstract: Signal Path DESIGNER Designing a 33MHz, 32-Bit PCI Target Using MACH Devices Reference Design Application Note Table of Contents DESIGNING A 33MHZ, 32-BIT PCI TARGET USING MACH DEVICES , . 5 REGISTER TRANSFER LEVEL (RTL) IMPLEMENTATION OF THE PCI TARGET REFERENCE DESIGN. 6 PCI TARGET TOP , . 13 THE DEVICE-UNDER-TEST (THE PCI TARGET
Lattice Semiconductor
Original
vhdl code for a 9 bit parity generator pci initiator in verilog pci target verilog hdl code for parity generator vhdl code for 4 bit even parity generator vhdl code for 9 bit parity generator M4A-384/192-7AC

PLX PCI9030 bridge

Abstract: pci target PCI target interfaces can be implemented at lower costs using CPLDs, resulting in cost savings and , function as a 32-bit, 66-MHz PCI target interface by integrating Altera's PCI target interface , implements a local bus interface similar to common ASSP-based PCI interfaces. The Altera PCI target interface , block diagram of Altera's MAX II CPLD-based PCI target interface solution. WP-AAB090305-1.3 March , Corporation Figure 2. Altera's MAX II CPLD-Based PCI Target Interface Solution Block Diagram 32-bit PCI I
Altera
Original
PLX PCI9030 bridge plx 9030 PCI9030 64-BIT SOUND CARD cpldbased EPM1270 66-MH

E2925A

Abstract: 21052-AB pcit1 PCI Target MegaCore Function Data Sheet ® 1998 6 ver.1 Data Sheet s s s , I/O MRM MRL MWI Page 1 pcit1 PCI Target MegaCore Function , Corporation pcit1 PCI Target MegaCore Function Data Sheet MAX+PLUS II.gdf pcit1 pcit1 , TABORT_SIG SERR_SIG PERR_DET Page 3 pcit1 PCI Target MegaCore Function Data Sheet PCI pcit1 PCI , pcit1pcit1PCI pcit1PCI pcit1 Page 4 Altera Corporation pcit1 PCI Target MegaCore Function Data
Altera
Original
E2925A FF000000 21052-AB 803-4 BUS BAR specification 430HX 430TX 3233MH 10KFLEX BARFLEX550790 132M/

wishbone rev. b

Abstract: wishbone the PCI and WISHBONE sides of the bridge · Supports 33 MHz,32-bit PCI target functions with PCI Local , Parity generation for all read cycles · Two FIFOs between PCI target module and WISHBONE master module , design does not support the following features: · PCI target interface ­ PERR and SERR ­ Expansion ROM , register ­ Interrupt signal from PCI target to PCI initiator · WISHBONE master interface ­ Respond to , design is used to interface a PCI initiator, or master, and a WISHBONE slave device. It acts as a target
Lattice Semiconductor
Original
wishbone rev. b wishbone verilog code for pci to pci bridge RD1045 LCMXO2280C-3FT324C LFXP2-5E-5FT256C

AGP Host to PCI Bridge

Abstract: gart ) will be described. Processor 1 2 4 PCI Target PCI Master (Optional) AGP Master AGP , Controller 8 6 System Memory 3 PCI Controller AGP Compliant Corelogic PCI PCI Target/Master PCI Target/Master Target/Master 6-1 Figure 0-1 Configuration View of an A.G.P. Target , Controller also provides a means for PCI masters to access the PCI target that resides on the A.G.P. port , Bridge Architecture Specification. The P2P bridge makes it possible to configure the PCI target
Intel
Original
AGP Host to PCI Bridge gart commands pci controller ECR-16

plx 9030

Abstract: plx 9030 data sheet . . . 2.1.1.1. PCI Target Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 2.1.1.3. PCI Target Accesses to an 8- or 16-Bit Local Bus Device . . . . . . . . . . . . . . . . . . . . . , 3-1 3-1 3-1 3-1 3-1 3-1 3-3 3-6 3-6 3-7 3-7 3-8 4. PCI Target (Direct Slave) Operation . , . . . . . . . 4.2.1. PCI Target Operation (PCI Master-to-Local Bus Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1.1. PCI Target Lock . . . . . . . . . . . . .
PLX Technology
Original
plx 9030 data sheet mini pci pcb layout plx 9030 176-pin pqfp 9030-SIL-DB-P1-1

XC4400

Abstract: Xilinx XC4013E-3PQ208C ® PCI Target System Module for XILINX XC4000E FPGA September 27, 1995 Design Description , fully-implemented 33 MHz PCI Target interface in 40% of an XC4013E-3PQ208C FPGA. n Verified electrical and , PCI Target inte rface, configuration registers, burst FIFOs, and a custom back-end interface. n , cost. Application Procedure The Xilinx PCI Target System Module ensures fast time-to-volume by , required to obtain the PCI Target System Module. To apply for the PCI Target System Module design
Xilinx
Original
XC4400 Xilinx XC4013E-3PQ208C XC4000

plx 9030

Abstract: plx 9030 176-pin pqfp . . . . . . . . . . . . . . 1.1.3.1. High-Performance PCI Target Interface . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1.1. PCI Target Command , . . . . . . . . . . . . . . . . . . . . . . . 2.1.1.5. PCI Target Accesses to an 8-or 16-Bit Local , 3-6 3-7 3-7 3-8 4. PCI Target (Direct Slave) Operation . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1. PCI Target
PLX Technology
Original
93cs66l PLX Technology 9030-AA60BI 93CS56L PPC401 TMS320C6202

plx 9030

Abstract: 9030-AA60BI .2 compliant 32-bit 33MHz Target Interface Chip enabling PCI Burst Transfers up to 132Mbytes/second. s Up to 60MHz Local Bus operation enabling burst transfers up to 240Mbytes/second s PCI Target Read Ahead Mode s PCI Target Programmable Burst s PCI Target Delayed Write s Posted Memory , to do a PCI target design. Many PCI chip and core designs only attempt to implement the minimum PCI , your current PCI target design, the PCI 9030 with SMARTarget technology provides the fastest and
PLX Technology
Original
176-PQFP PCI 9030 BGA 180 176PQFP 9030-AA60PI 9030RDK-LITE 9030-SIL-PB-P1-03
Abstract: 1.2.3.1. High-Performance PCI Target Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . 2.1.1.1. PCI Target Command Codes . . . . . . . . . . . . . . , . . . . . . . . . . . . 2.1.1.3. PCI Target Accesses to an 8- or 16-Bit Local Bus Device . . . . . , 3-1 3-3 3-6 3-6 3-7 3-7 3-8 4. PCI Target (Direct Slave) Operation . . . . . . . . . . . . . , 4.2.1. PCI Target Operation (PCI Master-to-Local Bus Access) . . . . . . . . . . . . . . . . . . . . . . PLX Technology
Original

EJTAG PROBE

Abstract: 20A4 target reads and writes as well as PCI master reads and writes. There are separate eight-word-deep FIFOs , majority of PCI devices and nearly all of the customer systems IDT has seen utilize target reads and , increasing the target access buffer sizes, numerous other architectural changes were made. General PCI , system controller registers. PCI Target Write Changes In the Z-revision, target PCI writes are , PCI target write never performs burst transactions across the local bus, the 1-1-1 is not taken
Integrated Device Technology
Original
AN-350 RC32332 EJTAG PROBE 20A4 RC32334/RC32332 RC32334

176-PQFP

Abstract: plx 9030 .2 compliant 32-bit 33MHz Target Interface Chip enabling PCI Burst Transfers up to 132Mbytes/second. s Up to 60MHz Local Bus operation enabling burst transfers up to 240Mbytes/second s PCI Target Read Ahead Mode s PCI Target Programmable Burst s PCI Target Delayed Write s Posted Memory , to do a PCI target design. Many PCI chip and core designs only attempt to implement the minimum PCI , your current PCI target design, the PCI 9030 with SMARTarget technology provides the fastest and
PLX Technology
Original

430VX

Abstract: ® pcit1 PCI Target MegaCore Function Data Sheet July 1998, ver. 1.01 Features s s s s , -bit, 33-MHz peripheral component interconnect (PCI) target interface Fully compliant with the PCI Special , Corporation A-DS-PCIT1-01.01 1 pcit1 PCI Target MegaCore Function Data Sheet General Description , target interface (ordering code: PLSM-PCIT1). Because the pcit1 function handles the complex PCI protocol , and implements the logic. 2 Altera Corporation pcit1 PCI Target MegaCore Function Data Sheet
Altera
Original
430VX 33-MH 800-EPLD

AN-350

Abstract: AN-366 -366 Notes PCI Target Transactions Several programmable settings are provided to control the throughput of PCI target transactions. Also, changes were made to the internal hardware in the Y revision to , registers are modified. The following example shows that the optimum setting for the PCI target control , target read operations. The CPU clock is 66Mhz and PCI clock is 33Mhz. In this example, since it is feasible to perform bursts with this packet size, by setting the MW/MWI bit to 1, the PCI target control
Integrated Device Technology
Original
AN-366 IDT79RC32334 IDT79RC32332 TN-45

MCF5470

Abstract: MCF5471 Disconnected PCI read bursts when MCF547x is master can cause corruption when followed by target access 4 , /2004 All PCI target interface prefetch from slow memory 6 PCI 08/17/2004 All , /17/2004 All PCI target interface does not expect false writes on the first data beat 12 , /write results in data loss 16 PCI 08/17/2004 All PCI target read prefetch data , target interface of the PCI controller and a read to PCI across the XL bus collide. The condition occurs
Freescale Semiconductor
Original
MCF5475 MCF5470 MCF5471 MCF5472 MCF5473 MCF5474

DS437

Abstract: 0X00 Master write to a remote PCI target (both single and burst) - PCI Initiator read of a remote OPB slave (both single and multiple) · OPB Master read of a remote PCI target (both single and burst , data written to the register is broadcast over the PCI bus. The V3 core functioning as a target , IPIF/V3 bridge when executed by a remote PCI initiator and received by the V3 as a target. To execute , /LogiCore V3 PCI Core Bridge - OPB Master Write Target Abort - OPB Master Abort Write - OPB
Xilinx
Original
DS437 PCI64 0X00 REQ64

93CS66L

Abstract: LAD1 12v 8 pin relay 1.2.2.3. PCI Target (Direct Slave , 2.1.1. PCI Target Command Codes .2-1 2.1.2. PCI , 2.2.8. PCI Target Accesses to 8- or 16-Bit Local Bus , (Local Master-to-PCI Target) .3-1 3.4.1.1. PCI Initiator Memory , Initiator/Target 3.4.1.10. PCI Initiator
-
OCR Scan
LAD1 12v 8 pin relay PLX PCI9054 MC 9080 plx 9054 SD card V2.0 Physical Layer Spec ali 3511 9054-SIL-DB-P1-2 USA/0899 LAD25 LAD24 LAD30 LAD23
Showing first 20 results.