500 MILLION PARTS FROM 12000 MANUFACTURERS

Datasheet Archive - Datasheet Search Engine

 

Direct from the Manufacturer

Part Manufacturer Description PDF Samples Ordering
X9428WS16 Intersil Corporation X9428WS16, SOP-16 pdf Buy
X9428WS16I Intersil Corporation X9428WS16I, SOP-16 pdf Buy
X9428WS16IT1 Intersil Corporation X9428WS16IT1, SOP-16 pdf Buy

outline of the heat sink for JEDEC

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: ascending pin count. Altera package outlines meet the requirements of JEDEC Publication No. 95. 484 , outline figure references, respectively, for the 484-pin thermally enhanced FineLine BGA packaging , Device Handbook, Volume 2 Package Outlines Figure 10­1 shows a package outline for the 484 , package outline for the 672-pin thermally enhanced FineLine BGA packaging. Altera Corporation October , information and package outline figure references, respectively, for the 1,020-pin thermally enhanced ... Altera
Original
datasheet

10 pages,
255.04 Kb

MS-034 EP2S90 EP2S60 EP2S30 EP2S180 EP2S15 bga package weight AAU1 SII52010-1 TEXT
datasheet frame
Abstract: are for each of the +V and -V supplies. HEAT SINK - ESOIC PACKAGES Both the 14-pin and 16 , sink located on the bottom surface of the device. This heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. The heat sink is electrically isolated from the chip and , ) Electrically isolated heat sink pad on bottom of package. Connect to any ground or power plane for optimum , series with each output. The HI-318X HI-318X series of line drivers are intended for use where logic signals must ... HOLT Integrated Circuits
Original
datasheet

11 pages,
297.85 Kb

124 008r HI-3182 HI-3183 HI-3184 HI-3185 HI-3186 HI-3187 HI-3188 TEXT
datasheet frame
Abstract: are for each of the +V and -V supplies. HEAT SINK - ESOIC PACKAGES Both the 14-pin and 16 , sink located on the bottom surface of the device. This heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. The heat sink is electrically isolated from the chip and , heat sink pad on bottom of package. Connect to any ground or power plane for optimum thermal , for short periods of time (125ms). The Vref pin has an internal pull-up resistor to V+, allowing the ... HOLT Integrated Circuits
Original
datasheet

11 pages,
106.9 Kb

ESD 138C 124 008r HI-3182 HI-3183 HI-3184 HI-3185 HI-3186 HI-3188 TEXT
datasheet frame
Abstract: listed are for each of the +V and -V supplies. HEAT SINK - ESOIC PACKAGES Both the 14-pin and 16 , sink located on the bottom surface of the device. This heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. The heat sink is electrically isolated from the , alternate sources for the HS-3182 HS-3182 ( Intersil/Harris), the RM3182 RM3182 (Fairchild /Raytheon) and a variety of , between 800 - 900 mA for short periods of time (125ms). The Vref pin has an internal pull-up resistor to ... HOLT Integrated Circuits
Original
datasheet

12 pages,
105.28 Kb

RM3182 HI-3184 HI-3185 HI-3186 HI-3188 HI-8382 HI-8383 HS-3182 HI-3182 HI-3183 TEXT
datasheet frame
Abstract: package information and package outline figure references, respectively, for the 484-pin FBGA packaging , BSC Figure 14­1 shows a package outline for the 484-pin FineLine BGA packaging. Figure 14­1. 484 , Package Outlines Figure 14­2 shows a package outline for the 780-pin FineLine BGA packaging. Figure , 14­7 and 14­8 show the package information and package outline figure references, respectively, for , , Volume 2 Document Revision History Figure 14­3 shows a package outline for the 1,152-pin FineLine ... Altera
Original
datasheet

10 pages,
193.66 Kb

MS-034 arria AGX52014-1 FBGA-484 datasheet TEXT
datasheet frame
Abstract: ascending pin count. Altera package outlines meet the requirements of JEDEC Publication No. 95. 14­2 , Handbook, Volume 2 Package Outlines Figure 14­1 shows a package outline for the 484-pin FineLine BGA , GX Device Handbook, Volume 2 Package Outlines Figure 14­2 shows a package outline for the 780 , Handbook, Volume 2 Document Revision History Figure 14­3 shows a package outline for the 1,152 , that meets JDEC specifications and for a typical board. The following values are provided ... Altera
Original
datasheet

8 pages,
167.49 Kb

MS-034 AGX52014-1 altera cross reference bt 146 EP1AGX90 FBGA PACKAGE thermal resistance MS 034 asme y14.5m 84 FBGA outline FBGA-484 datasheet TEXT
datasheet frame
Abstract: of ascending pin count. Altera package outlines meet the requirements of JEDEC Publication No. 95 , . 0.50 b Nom. 0.60 0.70 e 1.00 BSC Figure 14­1 shows a package outline for the 484 , information and package outline figure references, respectively, for the 780-pin FBGA packaging. Table , for the 780-pin FineLine BGA packaging. Figure 14­2. 780-Pin FBGA Package Outline TOP VIEW , outline for the 1,152-pin FineLine BGA packaging. Figure 14­3. 1,152-Pin FBGA Package Outline TOP VIEW ... Altera
Original
datasheet

10 pages,
200.77 Kb

MS-034 moisture sensitivity JEDEC FBGA EP1AGX90 AGX52014-1 484-pin BGA MS-034 1152 BGA FBGA-484 datasheet TEXT
datasheet frame
Abstract: Information for Arria GX Devices Package Outlines The package outlines are listed in order of ascending pin count. Altera package outlines meet the requirements of JEDEC Publication No. 95. 484-Pin FBGA , . 0.50 b Nom. 0.60 0.70 e 1.00 BSC Figure 14­1 shows a package outline for the 484 , information and package outline figure references, respectively, for the 780-pin FBGA packaging. Table , for the 780-pin FineLine BGA packaging. Figure 14­2. 780-Pin FBGA Package Outline TOP VIEW ... Altera
Original
datasheet

8 pages,
197.69 Kb

MS-034 MS 034 aaj led flip-chip 84 FBGA outline AGX52014-1 altera cross reference bt 146 1152 FBGA-484 FBGA 152 84 FBGA thermal FBGA-484 datasheet MS-034 1152 BGA TEXT
datasheet frame
Abstract: has a lip designed for a CPGA package to prevent movement of the heat sink relative to the package , capacitors, and exposed pins on the top side of the package. For use on the PPGA package, if the heat sink , . For example, an electrically conductive heat sink should not contact the exposed pins, external , drawings and dimensions for the 296 lead PPGA package. The package meets JEDEC outline spec MO-128 MO-128 for pin , outline drawings and dimensions for the 370 lead FCPGA package. The package meets JEDEC outline spec MO ... Intel
Original
datasheet

26 pages,
588.91 Kb

A719-0 a7190 outline of the heat sink for Theta JC FCPGA JEDEC Thin Matrix Tray outlines BGA PACKAGE TOP MARK intel A7646-01 socket s1 REFLOW socket 615-PIN A7190-01 A7647-01 A7647 TEXT
datasheet frame
Abstract: FBGA w/ fin (1) Notes to Table 26: (1) "fin" is an extra heat sink that customers can add to the , outlines meet the requirements of JEDEC Publication No. 95. 25 Altera Device Package Information , dimension is in millimeters. N is the number of leads. Package Information Package Outline Figure , in inches. N is the number of leads. Package Information Package Outline Figure Reference , is the number of leads. Package Information Package Outline Figure Reference Description ... Altera
Original
datasheet

135 pages,
2141.88 Kb

epm7032 plcc EP1C12 Altera pdip top mark 192 BGA PACKAGE thermal resistance BGA sumitomo 724p 240 pin rqfp drawing TEXT
datasheet frame

Archived Files

Abstract Saved from Date Saved File Size Type Download
to sink different amounts of heat. Utilization of IMS is considered for several appli- cations heat sink is ap- plied to the IMS by means of screws, bolts or riv- ets. The total thermal resistance insertion packages. In view of the larger pin count needed for smart power products, a family of packages 0.5 sec. Therefore the range of application exceeds 20 W, the same as for traditional power kind of self centering effect has been observed, which is mostly due to the dual-in-line outline and
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1732-v3.htm
STMicroelectronics 25/05/2000 38.78 Kb HTM 1732-v3.htm
depending on the chip size. For large dissipation, an external heat sink is ap- plied to the IMS by means of demonstrates that PowerSO-20 is the real successor of Multiwatt for surface mount applications and can become a to cover the require- ments of advanced smart power, needing more I/Os for the logic circuitry. Due the larger pin count needed for smart power products, a family of packages has been designed, covering ] Coplanarity Lead coplanarity is considered a major issue for surface mount devices. In the case of Power
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1732-v1.htm
STMicroelectronics 02/04/1999 36.9 Kb HTM 1732-v1.htm
depending on the chip size. For large dissipation, an external heat sink is ap- plied to the IMS by means of smaller systems. Evolution of SMT drove the development of sev- eral new packages for discrete and IC structure for in- sertion and are mounted manually in the PCB, with loss of time, productivity, floor space However, the experience of SGS THOMSON with above solutions is not totally satisfactory, for a number of as traditional insertion packages. In view of the larger pin count needed for smart power products, a
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1732.htm
STMicroelectronics 20/10/2000 40.14 Kb HTM 1732.htm
depending on the chip size. For large dissipation, an external heat sink is ap- plied to the IMS by means of demonstrates that PowerSO-20 is the real successor of Multiwatt for surface mount applications and can become a to cover the require- ments of advanced smart power, needing more I/Os for the logic circuitry. Due the larger pin count needed for smart power products, a family of packages has been designed, covering ] Coplanarity Lead coplanarity is considered a major issue for surface mount devices. In the case of Power
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1732-v2.htm
STMicroelectronics 14/06/1999 36.87 Kb HTM 1732-v2.htm
prevent both MOSFETs from conducting simultaneously. The ISL6596 ISL6596 features 4A typical sink current for Bottom Copper Pad for Heat Spreading Dual Flat No-Lead (DFN) Package Compliant to JEDEC The price listed is the manufacturer's suggested retail price for quantities between 100 and 999 3nF load with less than 10ns rise/fall time. Bootstrapping of the upper gate driver is implemented via an internal low forward drop diode, reducing implementation cost, complexity, and allowing the use of
/datasheets/files/intersil/device_pages/device_isl6596.html
Intersil 07/09/2006 35.55 Kb HTML device_isl6596.html
The price listed is the manufacturer's suggested retail price for quantities between 100 and 999 MOSFETs forms complete core-voltage regulator solutions for advanced microprocessors. The ISL6614B ISL6614B PHASE node is connected to the gate of the low side MOSFET (LGATE). The output voltage of the converter is then limited by the threshold of the low side MOSFET, which provides some protection to the is used in some systems for protecting the load from reversed output voltage events.  
/datasheets/files/intersil/device_pages/device_isl6614b.html
Intersil 07/09/2006 40.01 Kb HTML device_isl6614b.html
Expandable Bottom Copper Pad for Enhanced Heat Sinking QFN Package: Compliant to JEDEC PUB95 PUB95 The price listed is the manufacturer's suggested retail price for quantities between 100 and 999 MOSFETs form complete corevoltage regulator solutions for advanced microprocessors. The ISL6614A ISL6614A drives PHASE node is connected to the gate of the low side MOSFET (LGATE). The output voltage of the converter is then limited by the threshold of the low side MOSFET, which provides some protection to the
/datasheets/files/intersil/device_pages/device_isl6614a.html
Intersil 07/09/2006 42.44 Kb HTML device_isl6614a.html
The price listed is the manufacturer's suggested retail price for quantities between 100 and 999 N-Channel MOSFETs form complete core-voltage regulator solutions for advanced microprocessors. The ISL6614 ISL6614 PHASE node is connected to the gate of the low side MOSFET (LGATE). The output voltage of the converter is then limited by the threshold of the low side MOSFET, which provides some protection to the This feature eliminates the Schottky diode that is used in some systems for protecting the load from
/datasheets/files/intersil/device_pages/device_isl6614.html
Intersil 07/09/2006 44 Kb HTML device_isl6614.html
Appendix E - Board Issues for Heat Dissipation The internal temperature of the device must remain below drive to allow for single supply switching. The center tap of the primary side of the transformer is sink current on pin PAOP and PAON 7 600 1000 mA This is the sum of the current from PAOP1 and full scale (for signal gain of 20.1dB, the full scale signal at power amplifier input is 1.05 Vp). The voltage of the distortion product. For the Two Tone A spec the tones are at f1=500KHz and f2=300KHz
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/7442.htm
STMicroelectronics 07/12/2000 39.97 Kb HTM 7442.htm
FOR FORMS SUB INTERESTING CONNECTION AMONG SUM SINK STOPS UNPLEASANT SAMPLING RESISTOR ACTIVE SIGNAL MAGNITUDE DUMPED NPNS BIAS AIDS MOST CURRENT IMPEDANCE CHANGE MAY FOR DENSITIES SATURATE TURN CUT SINK GOALS and Applying the LT1005 LT1005 Multifunction Regulatoran1.pdfApplication NoteWILLIAMS DROPS SETPOINTS BUT INPUTS CURRENT INTERFACES BEING IMPEDANCE MAY FOR TURN DROPOUT OVERLOADS FLOP 3300RPM 3300RPM FLOW RESISTOR CONDUCTION ACHIEVED REACHES PUSHBUTTON HELD CHARGES UNDER TAKING THROUGH THE DETERMINED ZENERING NTC
/datasheets/files/linear/lview3/parts-v1.edb
Linear 08/10/1998 5000.33 Kb EDB parts-v1.edb