500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
UA7815CKTE Texas Instruments 15V FIXED POSITIVE REGULATOR, PSSO3, HEAT SINK, SO-3 visit Texas Instruments
UA7885CKTE Texas Instruments 8.5V FIXED POSITIVE REGULATOR, PSSO3, HEAT SINK, SO-3 visit Texas Instruments
UA7812CKTE Texas Instruments 12V FIXED POSITIVE REGULATOR, PSSO3, HEAT SINK, SO-3 visit Texas Instruments
UA7824CKTE Texas Instruments 24V FIXED POSITIVE REGULATOR, PSSO3, HEAT SINK, SO-3 visit Texas Instruments
UA7805CKTE Texas Instruments 5V FIXED POSITIVE REGULATOR, PSSO3, HEAT SINK, SO-3 visit Texas Instruments
UA7808CKTE Texas Instruments 8V FIXED POSITIVE REGULATOR, PSSO3, HEAT SINK, SO-3 visit Texas Instruments

outline of the heat sink for JEDEC

Catalog Datasheet MFG & Type PDF Document Tags

bga package weight

Abstract: AAU1 ascending pin count. Altera package outlines meet the requirements of JEDEC Publication No. 95. 484 , outline figure references, respectively, for the 484-pin thermally enhanced FineLine BGA packaging , Device Handbook, Volume 2 Package Outlines Figure 10­1 shows a package outline for the 484 , package outline for the 672-pin thermally enhanced FineLine BGA packaging. Altera Corporation October , information and package outline figure references, respectively, for the 1,020-pin thermally enhanced
Altera
Original

124 008r

Abstract: B13W are for each of the +V and -V supplies. HEAT SINK - ESOIC PACKAGES Both the 14-pin and 16 , sink located on the bottom surface of the device. This heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. The heat sink is electrically isolated from the chip and , ) Electrically isolated heat sink pad on bottom of package. Connect to any ground or power plane for optimum , series with each output. The HI-318X series of line drivers are intended for use where logic signals must
HOLT Integrated Circuits
Original
124 008r B13W HI-3182 HI-3183 HI-3184 HI-3185 HI-3186 HI-3187

ESD 138C

Abstract: 124 008r are for each of the +V and -V supplies. HEAT SINK - ESOIC PACKAGES Both the 14-pin and 16 , sink located on the bottom surface of the device. This heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. The heat sink is electrically isolated from the chip and , heat sink pad on bottom of package. Connect to any ground or power plane for optimum thermal , for short periods of time (125ms). The Vref pin has an internal pull-up resistor to V+, allowing the
HOLT Integrated Circuits
Original
ESD 138C HI-3188 HI-8382 HI-8383 HS-3182 RM3182 28-PIN

k0319

Abstract: HI-3183 listed are for each of the +V and -V supplies. HEAT SINK - ESOIC PACKAGES Both the 14-pin and 16 , sink located on the bottom surface of the device. This heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. The heat sink is electrically isolated from the , alternate sources for the HS-3182 ( Intersil/Harris), the RM3182 (Fairchild /Raytheon) and a variety of , between 800 - 900 mA for short periods of time (125ms). The Vref pin has an internal pull-up resistor to
HOLT Integrated Circuits
Original
k0319 32-PIN

FBGA-484 datasheet

Abstract: AGX52014-1 package information and package outline figure references, respectively, for the 484-pin FBGA packaging , BSC Figure 14­1 shows a package outline for the 484-pin FineLine BGA packaging. Figure 14­1. 484 , Package Outlines Figure 14­2 shows a package outline for the 780-pin FineLine BGA packaging. Figure , 14­7 and 14­8 show the package information and package outline figure references, respectively, for , , Volume 2 Document Revision History Figure 14­3 shows a package outline for the 1,152-pin FineLine
Altera
Original
AGX52014-1 MS-034 FBGA-484 datasheet arria EP1AGX35 EP1AGX50 EP1AGX20 EP1AGX90 152-P

FBGA-484 datasheet

Abstract: asme y14.5m ascending pin count. Altera package outlines meet the requirements of JEDEC Publication No. 95. 14­2 , Handbook, Volume 2 Package Outlines Figure 14­1 shows a package outline for the 484-pin FineLine BGA , GX Device Handbook, Volume 2 Package Outlines Figure 14­2 shows a package outline for the 780 , Handbook, Volume 2 Document Revision History Figure 14­3 shows a package outline for the 1,152 , that meets JDEC specifications and for a typical board. The following values are provided
Altera
Original
asme y14.5m 84 FBGA outline FBGA-484 FBGA PACKAGE thermal resistance FBGA1152 bt 146 EP1AGX60

FBGA-484 datasheet

Abstract: MS-034 1152 BGA of ascending pin count. Altera package outlines meet the requirements of JEDEC Publication No. 95 , . 0.50 b Nom. 0.60 0.70 e 1.00 BSC Figure 14­1 shows a package outline for the 484 , information and package outline figure references, respectively, for the 780-pin FBGA packaging. Table , for the 780-pin FineLine BGA packaging. Figure 14­2. 780-Pin FBGA Package Outline TOP VIEW , outline for the 1,152-pin FineLine BGA packaging. Figure 14­3. 1,152-Pin FBGA Package Outline TOP VIEW
Altera
Original
MS-034 1152 BGA 484-pin BGA JEDEC FBGA moisture sensitivity

MS-034 1152 BGA

Abstract: FBGA-484 datasheet Information for Arria GX Devices Package Outlines The package outlines are listed in order of ascending pin count. Altera package outlines meet the requirements of JEDEC Publication No. 95. 484-Pin FBGA , . 0.50 b Nom. 0.60 0.70 e 1.00 BSC Figure 14­1 shows a package outline for the 484 , information and package outline figure references, respectively, for the 780-pin FBGA packaging. Table , for the 780-pin FineLine BGA packaging. Figure 14­2. 780-Pin FBGA Package Outline TOP VIEW
Altera
Original
FBGA 152 84 FBGA thermal 1152 MS 034 aaj led flip-chip altera cross reference

A7647

Abstract: A7647-01 has a lip designed for a CPGA package to prevent movement of the heat sink relative to the package , capacitors, and exposed pins on the top side of the package. For use on the PPGA package, if the heat sink , . For example, an electrically conductive heat sink should not contact the exposed pins, external , drawings and dimensions for the 296 lead PPGA package. The package meets JEDEC outline spec MO-128 for pin , outline drawings and dimensions for the 370 lead FCPGA package. The package meets JEDEC outline spec MO
Intel
Original
A7647 A7647-01 A7190-01 socket s1 REFLOW socket 615-PIN BGA PACKAGE TOP MARK intel A5775-01

240 pin rqfp drawing

Abstract: BGA sumitomo FBGA w/ fin (1) Notes to Table 26: (1) "fin" is an extra heat sink that customers can add to the , outlines meet the requirements of JEDEC Publication No. 95. 25 Altera Device Package Information , dimension is in millimeters. N is the number of leads. Package Information Package Outline Figure , in inches. N is the number of leads. Package Information Package Outline Figure Reference , is the number of leads. Package Information Package Outline Figure Reference Description
Altera
Original
EP1C12 240 pin rqfp drawing BGA sumitomo 724p Altera pdip top mark 192 BGA PACKAGE thermal resistance epm7032 plcc 7000B 7000AE EP1C20 DS-PKG-11 EP1SGX10D

HI-8586 thermal

Abstract: HI8585PSIN -8586 products. The ESOIC package includes a metal heat sink located on the bottom surface of the device. This heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. The , until one of the inputs becomes a One. If for example TX1IN goes high, a charging path is enabled to , ESOIC (Thermally enhanced SOIC with built in heat sink). Heat sink not soldered to the PCB. 6. 8 Lead Plastic ESOIC (Thermally enhanced SOIC with built in heat sink). Heat sink soldered to the PCB. 7
HOLT Integrated Circuits
Original
HI-8585 HI-8586 HI-8588 HI-8586 thermal HI8585PSIN INTERFACE TECHNOLOGY ARINC 429 HI-3282 HI-6010 HI-8282

transistor d333

Abstract: TRANSISTOR BC 384 contact between the transistor and heat sink: (a) Remove all burrs from the edges of clearance holes in the heat sink. (b) Use a small amount of silicone grease either between the transistor and heat sink , For detail dimensions see Page 6 2704 Dâ'"11 In the interest of improved product design, changes _ _ , . The transistors comply with JEDEC TO-3/TÛ-204 outline. 2. The collector is internally connected to , pins must not be bent. The pins may be dip-soldered at a temperature of 240°C for a maximum of 10
-
OCR Scan
DT5336 DT4335 transistor d333 TRANSISTOR BC 384 mercury wetted relay, double contact power darlington 100W npn darlington 6A 400V G7G13 T4335 DT4336 DT5335 DT4335/6

HI-8586 thermal

Abstract: HI-8588 -8586 products. The ESOIC package includes a metal heat sink located on the bottom surface of the device. This heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. The , TXBOUT hold each side of the ARINC bus at Ground until one of the inputs becomes a One. If for example , ESOIC (Thermally enhanced SOIC with built in heat sink). Heat sink not soldered to the PCB. 6. 8 Lead Plastic ESOIC (Thermally enhanced SOIC with built in heat sink). Heat sink soldered to the PCB. 7
HOLT Integrated Circuits
Original
DS8585 HI-858 8586 HI-8585PSI-N

smd transistor M7A

Abstract: ED-7304-1 Registration ED-7300 Recommended practice on standard for the preparation of outline drawing of , Rules for the Preparation of Outline Drawings of Integrated Circuits Number EIAJ Standard , features shall be specified. (Maximum of 3 letters) 1 Outline addition H: Heat sink W: Window A , no responsibility for any losses incurred by the customer or third parties arising from the use of , Industry Association of Japan (EIAJ). In the United States, an organization for semiconductor packages (JC
NEC
Original
smd transistor M7A ED-7304-1 smd m7a uPD4011BG ED730 EIA and EIAJ tape standards PD421000LA-10-E1 PD421000LA PD41265L-12-E1 PD41256L PD23C32000AGX- PD23C32000A

footprint jedec MS-026 TQFP

Abstract: footprint jedec MS-026 LQFP conduct the heat all the way to the surface of the IC package. For such devices, a much thicker heat sink , , with industry standards established for both the JEDEC package outline and the IPC land pattern for , has been established for both the JEDEC package outline and the IPC land pattern. Figure 2.3 , the topside of the package. Heat Spreader Design-This design includes a heat sink that is attached , advantageous, a thin strip of insulating tape in the B-stage epoxy allows the heat sink to be quite close to
Advanced Micro Devices
Original
footprint jedec MS-026 TQFP footprint jedec MS-026 LQFP JEDEC TRAY ssop footprint jedec MS-026 TQFP 44 footprint jedec MS-026 LQFP 64 pin MS-026 BED MO-015 MS-011

12SnOFC

Abstract: PMC-90 listed below in the "Affected FSIDs" section. Description of Change: Fairchild Semiconductor (Suzhou , Semiconductor's ongoing effort to increase manufacturing capacity for our various products assembled in the TO , Suzhou, Jiangsu P. R. of China. The following are the package dimensional, process and material , Package width Heat sink heigth Package height Total package height Lead pitch Lead shoulder width Lead mounting width Back metal heat sink width Back metal heat sink height Center lead cut length
Fairchild Semiconductor
Original
RF1S640SM9A FDB2532 FDB8030L RF3S49092SM9A FDB2552 FDB7042L 12SnOFC PMC-90 PMC-90 leadframe material 92.5Pb5Sn2.5Ag Tamac4 MKT-TO263A02 FDB6670AL FDB6676S FDB7030BLS FDB7045L FDI3632 HUF75329S3

MQUAD

Abstract: package (Moisture Sensitive) with Material heat sink. This conversion should not require any board layout changes since the package outline for MQUAD Testing Manufacturing Site and ED QUAD is identical (JEDEC MS , Location Thermal Characteristics Heat Sink Moisture Sensitive Package Outline Copper Silver filled epoxy , notification of this change. Please use the acknowledgement below or E-Mail to grant approval or request , Location Affected: Date Effective: Contact: Title: Phone #: Fax #: E-mail: All 8/22/00 MEANS OF
Integrated Device Technology
Original
MQUAD I0008-05 MS-018 JESD22-A112 79R3511 79R3512 79R3521

MQUAD

Abstract: package (Moisture Sensitive) with Material heat sink. This conversion should not require any board layout changes since the package outline for MQUAD Testing Manufacturing Site and ED QUAD is identical (JEDEC MS , Location Thermal Characteristics Heat Sink Moisture Sensitive Package Outline Copper Silver filled epoxy , notification of this change. Please use the acknowledgement below or E-Mail to grant approval or request , Location Affected: Date Effective: Contact: Title: Phone #: Fax #: E-mail: All 8/22/00 MEANS OF
Integrated Device Technology
Original
79R3051 79R3051E 79R3052 79R3052E 79R3081 79R3081E

Datasheet of IC 7432

Abstract: 7415 ic pin details ) Registration 1997.05 General Rules for the Preparation of Outline Drawings of Integrated Circuits ED , practice on standard for the preparation of outline drawing of semiconductor packages Manual for the , Outline Package(SOP) Unit Design Guide for the Preparation of Package Outline Drawing of Integrated , Characteristics Through Hole Type V-DIP Terminals are on one side of the package and bent for through , activities for standardization of packages, as shown in the figure below, are developed in Japan, the United
NEC
Original
Datasheet of IC 7432 7415 ic pin details data sheet IC 7432 DATASHEET OF IC 7401 7401 ic configuration draw pin configuration of ic 7402

arinc 429 serial transmitter

Abstract: HI-8592 of the device. This heat sink should be soldered down to the printed circuit board for optimum , advantage of the tri-state outputs. For even smaller board footprint, versions are also available in , resistors in series with each ARINC output are available to allow the use of external resistors for lightning protection. SLP 1 The HI-859x series of line drivers are intended for use where logic , -PIN PLASTIC SMALL OUTLINE (ESOIC) NB o The family of parts are available in Industrial -40 C to o o o
HOLT Integrated Circuits
Original
HI-8592 HI-8570 HI-8571 HI-8593PS arinc 429 serial transmitter SOIC-8 HI-3584 HI-8593 HI-8594 HI-8592PS
Showing first 20 results.