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Part Manufacturer Description Datasheet BUY
TTL-LOGIC-DATABOOK Texas Instruments TTL-LOGIC-DATABOOK visit Texas Instruments
QW030CL1 GE Critical Power QW030xx DUAL Series Power Modules: dc-dc Converters, 18 Vdc to 36 Vdc or 36 Vdc to 75 Vdc Inputs visit GE Critical Power
QW030AJ1 GE Critical Power QW030xx DUAL Series Power Modules: dc-dc Converters, 18 Vdc to 36 Vdc or 36 Vdc to 75 Vdc Inputs visit GE Critical Power
EP0300AC48TEZ GE Critical Power EP0300AC48TEZ, Compact, Ssingle Phase, Hotpluggable, Fan-cooled Rectifier and Battery Charger 300W Output at 48-58Vdc visit GE Critical Power
EBVW012A7B1Z<641-PHZ GE Critical Power EBVW012A7B Series DC-DC Converter Power Module, 34 - 75Vdc Input, 12.0 Vdc Output and 12.7A Output Current visit GE Critical Power
QW030BK1 GE Critical Power QW030xx DUAL Series Power Modules: dc-dc Converters, 18 Vdc to 36 Vdc or 36 Vdc to 75 Vdc Inputs visit GE Critical Power

oki Logic

Catalog Datasheet MFG & Type PDF Document Tags

how to re- record

Abstract: ML2500 Speech Algorythm y 8mm Utilizing OKI Logic/Memory Embedding Process MS87V1021 OKI JAPAN , MS87V1021 OKI Speech LSI New Product Introduction MS87V1021 Record & Playback LSI with Built-in DRAM (2Mbit)/Mask ROM (512Kbit) OKI Electric Industry Co., Ltd. - 1 / 16 - February 22 , Specifications (Preliminary) OKI Electric Industry Co., Ltd. - 2 / 16 - February 22, 2000 MS87V1021 Features & Benefits What's MS87V1021? That's new OKI Speech LSI which well suits to Car Radios
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how to re- record ML2500 MSM66 MSM6688L MSM66V84B MSM9888L TSOP32-P-814-0

S6 68A

Abstract: S4 68A Circuit 15 ^ 0.45 Test Points , 1& A C. Testing: Inputs are driven at 2.4 V lo r a logic *1" and 0.45 V for a logic "0" timing measurements are 1.5 V for both a logic T a n d `0". ^ CL = , circuits will m aintain the last valid logic state if no driving source is present (i.e. an unconnected pin , 1 1 0 1 0 1 0 Q 1 1 1 0 0 0 0 1 port 1 r/m r/m r/m ' mod mod mod reg reg reg OKI S em ico n d u cto r OKI ARITHMETHIC ADD = Add: Reg./memory with register to either
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S6 68A S4 68A m80c88a MSM80C88A-1ORS/GS/JS MSM80C88 MSM80C86A-10 MSM80C85AH 40-P-600 MSM80C88A-10RS

M80C88A-2

Abstract: 80C85AH SM80C86A-1 0 RS/GS/J S OKI LOGIC NOT = Invert SHL/SAL = Shift logical/arithmetic left SHR = Shift , 2.4 V for a logic '1' and 0.45 V for a logic 'O'. Timing measurements are 1.5 V for both a logic '1' , circuits will m aintain the last valid logic state if no driving source is present (i.e. an unconnected pin , OKI DATA TRANSFER MOV = Move: Register/memory to/from register Immediate to register/memory , port MSM80C86A-1ORS/GS/JS mod mod mod reg reg reg r/m r/m r/m 26/37 OKI
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80C85AH M80C88A-2 m80c85ah E200010-27-X2 MSM80C86A-10RS/GS/JS 80C86A-10 MSM80C88A-10 DIP40-P-600-2

80C85AH

Abstract: iC-lg /m r/m 0 1 0 0 0 OKI Semiconductor OKI LOGIC NOT = Invert SHL/SAL = Shift logical , , Testing: Inputs are driven at 2.4 V for a logic T " and 0.45 V for a logic "0U , Timing measurements are 1.5 V for both a logic "1"and "0". j ; C L = 100 pF Cl includes jig capacitance. Minimum Mode , 2-16, 26-32, and 34-39 (Figures 6a, 6b). These circuits will m aintain the last valid logic state if no , 0 0 1 1 1 0 0 0 0 1 port port mod mod mod reg reg reg r/m r/m r/m 1 ] OKI A
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iC-lg MSM80C86A-10RS -7 DIP40-P-600 MSM80C86A-10RS QFJ44-P-S650 MSM80C86A-10JS MSM80C86A-10GS-K

DR102

Abstract: QFP208-P-2828-K4 Control Logic OKI SEMICONDUCTOR 3 s Boundary Scan Application Note s , TDO SHIFTDR CLOCKDR Figure 9. Internal Logic of BSRINC Boundary Scan Cell OKI SEMICONDUCTOR , . Internal Logic of BSROUT Boundary Scan Cell 10 OKI SEMICONDUCTOR , boundary-scan logic to meet OKI's requirements. tpbscan The TAP Boundary SCAN program, tpbscan, adds five , netlist must already contain the scan logic. · Original user TPL ­ When OKI performs JTAG boundary-scan
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DR102 QFP208-P-2828-K4 ot2a OKI Package code STD-1149 1-800-OKI-6388

verilog code for 4 bit ripple COUNTER

Abstract: 8-bit ADC interface vhdl complete code for FPGA . SOG Logic and External Peripherals (Macro-cells) Interface RAM & ROM (Variable Size) OKI nX , Core · User Logic Figure 1. QuickCore Block Diagram OKI SEMICONDUCTOR 5 s nX 65K , Logic Data Out User Logic Output Enable Figure 4. Test-Mode Interface Logic Detail OKI , or Synthesis) Logic Simulation OKI SOG Design Environment Pre-Layout Simulation Pre-Layout , descriptions by logic synthesis tools. OKI provides the following design kits for its SOG library. 8 OKI
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verilog code for 4 bit ripple COUNTER 8-bit ADC interface vhdl complete code for FPGA generating pwm verilog code timer counters using jk flip flops D Flip Flops verilog HDL program to generate PWM

CM0002

Abstract: IC2A form (provided by OKI Application Engineering). The Pin Map form contains the logic setup information , - s OKI ASIC Mega Macrocell Usage s OKI Mega Macrocell Usage OKI mega macrocells have been implemented using OKI internal Macro Cell Development Tool (MCDT) which is based upon OKI's Pegasus layout software. The careful design and , back-annotated into OKI's simulation environment. In addition to the accurate modelling of internal layout delays
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MSM10SXXXX CM0001 CM0002 IC2A pin map

AMBA AHB to APB BUS Bridge verilog code

Abstract: toy car microcontroller User Logic APB 12 Expanded Peripheral Bus AMBATM AMBATM APB . (c) OKI Electric , OKI's System LSI Development Platform OKI's System LSI Development Platform µPLATTM µPLATTM LSI Division Silicon Solution Company Oki Electric Industry Co., Ltd. Rev.1.71e 03 Jul 2000 1 (c) OKI Electric Industry Co,.Ltd. Environment around System LSI Environment around System , (c) OKI Electric Industry Co,.Ltd. SPA (Silicon Platform Architecture) SPA (Silicon Platform
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AMBA AHB to APB BUS Bridge verilog code toy car microcontroller circuit diagram of wireless toy car control toy car circuit diagram using bluetooth verilog code for amba ahb bus AMBA APB bus protocol IEEE1394 ARM920T

CD2545

Abstract: long range gold detector circuit diagram . 15 Oki Semiconductor 10-GHz GaAs Family High-Speed Optical Communications Systems INTRODUCTION Oki's 10-GHz logic devices are manufactured using a 0.2-µm, ion-implanted process, which is similar to Oki's familiar 0.5-µm telecommunications process. However, the 0.2-µm process uses a , following table shows the digital GaAs logic processes of the 10-GHz GaAs family. GaAs Logic Processes , standard cell MESFET DCFL or SBFL PEL < 0.2 60 9 >12-Gbps hand-routed logic
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KGL4201 KGL4202 GHDD4411 GHDD4414 CD2545 long range gold detector circuit diagram gold metal detectors GAAS LOGIC 10GHZ GAAS 10-GH

MG65P

Abstract: IBM "embedded dram" SDRAM in logic products, Oki is able to integrate SDRAM and ASIC technology. The merged DRAM/ASIC , Macrocell Floor Plan 3. Place and route logic into the array transistors. - Oki Design Center engineers , hatching. Figure 9. Random Logic Place and Route Figure 10 illustrates Oki's Embedded DRAM ASIC. Oki , ) verities logic design rules [2] Oki's Link to Synthesis Floorplanning toolset (LSF) transters , Oki Semiconductor MG63P/64P/65P_ 0.25|im Embedded DRAM/Customer Structured Arrays DESCRIPTION
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MG65P IBM "embedded dram" oki cross 35x35 bga

oki cross

Abstract: b0268 embedded array architecture called the Customer Structured Array (CSA). Utilizing Oki's leadership in DRAM technologies and wide experience of embedding SDRAM in logic products, Oki is able to integrate SDRAM and ASIC , route logic into the array transistors. - Oki Design Center engineers use layout software and customer , ] [3] [4] [5] [6] Oki's Circuit Data Check program (CDC) verifies logic design rules Oki's Link , Embedded DRAM/Customer Structured Arrays DESCRIPTION Oki's 0.25 µm MG63P/64P/65P Application-Specific
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b0268 MG63P MG64P 1-800-OKI-6994

base cell

Abstract: MSM13Q [1] [2] [3] [4] [5] [6] Oki's Circuit Data Check (CDC) program verifies logic design rules , methodology is described in detail in Oki's 0.35 µm Scan Path Application Note. Combinational Logic A , ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ Oki Semiconductor MSM13Q0000/14Q0000 0.35 µm Sea of Gates Arrays DESCRIPTION Oki's 0.3 5 , four layers (MSM14Q) of metal. The semiconductor process is adapted from Oki's production-proven 64 , -layer arrays, respectively. Oki's 0.35 µm family is optimized for 3-V core operation with optimized 3-V I/O
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MSM13Q base cell floorplan io uart vhdl MSM13Q/14Q000 MSM13Q/14Q

MSM13R0000

Abstract: MSM98R000 logic. 2. Pin count is based on three downstream ports and one embedded function. Oki Semiconductor , Logic Modules to form a USB Compound Device function. Serial Interface Engine Oki's SIE handles the , . 11 Oki Semiconductor W722 USB Hub/Compound Device Controller 0.5 µm Technology Megamacro Function DESCRIPTION Oki's W722 Universal Serial Bus (USB) Hub/Compound Device Controller Megamacro Function is a featured element in Oki's 0.5 µm Sea of Gates (SOG) and Customer Structured Array (CSA
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MSM13R0000 MSM98R000 8-Port USB hub w722 8-Port USB hub circuit

L9013Q13Q

Abstract: MSM13Q ) program verifies logic design rules. Oki's Link to Synthesis Floorplanning (LSF) toolset transfers , described in detail in Oki's 0.35 µm Scan Path Application Note. Combinational Logic A FD1AS Scan , MSM13Q0000/14Q0000 0.35 µm Sea of Gates Arrays DESCRIPTION Oki's 0.3 5 µm ASIC products deliver , metal. The semiconductor process is adapted from Oki's production-proven 64-Mbit DRAM manufacturing , . Up to 66% and 90% of the raw gates can be used for the 3-layer and 4-layer arrays, respectively. Oki
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L9013Q13Q

TRANSISTOR SD 2689

Abstract: mg76 Memory Macrocell Floor Plan 3. Place and route logic into the array transistors. - Oki Design Center , hatching. Figure 3. Random Logic Place and Route Oki Semiconductor 5 MG74K/75K/76K , [1] Oki's Circuit Data Check program (CDC) verifies logic design rules [2] Oki's Test Data Check , . 11 OKI Advanced Design Center Cad Tools , . 17 Oki Semiconductor MG74K/75K/76K 0.15µm Customer Structured Arrays DESCRIPTION Oki
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TRANSISTOR SD 2689 mg76 inverter ic 3524 application HL 100 Transistor WinNT40 ambit inverter circuit

oki cross

Abstract: logic into the array transistors. - Oki Design Center engineers use layout software and customer , Check program (CDC) verifies logic design rules [2] Oki's Test Data Check program (TDC) verifies test , .8 OKI Advanced Design Center Cad Tools , .13 Oki Semiconductor MG87P3/87P4/87P5 0.25µm Standard Cell DESCRIPTION Oki's 0.25µm , Oki's production-proven 64Mbit DRAM manufacturing process. The 0.25µm SC family provides significant
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ic LM 356

Abstract: BGA and QFP Package 14x14 route logic into the array transistors. - Oki Design Center engineers use layout software and customer , program (CDC) verities logic design rules [2] Oki's Link to Synthesis Floorplanning toolset (LSF , OKI ASIC PRODUCTS teDonuoooog)^ MG113P/114P/115P/73P/74P/75P 0.25jim Sea of Gates and Customer Structured Arrays March 1998 Oki Semiconductor This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer Oki Semiconductor MG113P/114P/115P/73P/74P
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MG115P MG75P ic LM 356 BGA and QFP Package 14x14 MG113P MG73P MG74P MG113P/114P MG73P/74P MG113P/114P/115P MG7XPB22

MSC7162

Abstract: transistor bipolar driver schematic SflE T> m b72M£40 00mS2fl TM3 «OKIJ OKi bemiconauctor OKI SEMICONDUCTOR GROUP 40-BIT ANODE , hybridizing CMOS and bipolar transistors on the same chip. The logic portion such as the input stage, shift , register and latch. â'¢ Logic Supply Voltage: Vcc : +5V â'¢ Driver Supply Voltage: Vhv : +85V â'¢ Driver , CLX DIN vv POI P02 P040 SO DOUT OKI SEMICONDUCTOR GROUP Vcc Vcc Vhv Vhv LS CHG CL (1-20 , Manufacturer GROUP SfiE D â  b?24240 0014530 tTl «OKU OKI semiconductor M5C7162 PIN CONFIGURATION (TOP VIEW
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MSC7162 transistor bipolar driver schematic SSOP60-P-700-K SSOP60-P-700-L SSOP60-P-700-V1K 72M240 2424D

AMBIT inverter

Abstract: oki cross Separate power bus for output buffers Separate power bus for internal core logic and input buffers Oki , Memory Macrocell Floor Plan 3. Place and route logic into the array transistors. - Oki Design Center , hatching. Figure 3. Random Logic Place and Route 4 Oki Semiconductor , Conversion [1] Oki's Circuit Data Check program (CDC) verifies logic design rules [2] Oki's Test Data , .9 Oki Advanced Design Center Cad Tools
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AMBIT inverter MG73P/74P/75P
Abstract: Data Check program (CDC) verifies logic design rules Oki's Link to Synthesis Floorplanning toolset (LSF , Structured Arrays DESCRIPTION Oki's 0.25µm Application-Specific Integrated Circuit (ASIC) products are , and four metal layers, respectively. The semiconductor process is adapted from Oki's production-proven , to 50% less power and 30 to 50% more usable gates than traditional cell designs. The Oki 0.25µm , 21 array bases, offering a wider span of gate and I/O counts than the SOG series. Oki uses the OKI Electric Industry
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