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Part Manufacturer Description Datasheet BUY
STELLARIS-3P-ROWEB-EMFS-FS Texas Instruments Embedded File System visit Texas Instruments
SN7474N3 Texas Instruments Dual D-Type Positive-Edge-Triggered Flip-Flops With Preset And Clear 14-PDIP 0 to 70 visit Texas Instruments
SN7474N-00 Texas Instruments IC TTL/H/L SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, PLASTIC, DIP-14, FF/Latch visit Texas Instruments
SN7474J Texas Instruments TTL/H/L SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14 visit Texas Instruments
SN7474N-10 Texas Instruments TTL/H/L SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, PLASTIC, DIP-14 visit Texas Instruments
SN7474J-00 Texas Instruments TTL/H/L SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14 visit Texas Instruments

of IC 7474 in file

Catalog Datasheet MFG & Type PDF Document Tags

IC AND GATE 7408 specification sheet

Abstract: 74LS96 file. For each C N F , a Ffierarchy Inte rconnect File (.HIF) and a G raph ic Design File (.GDF) are , logic schem atic in the M A X + P L U S Graph ic Editor. Altera Corporation Page 320 Data Sheet , |d create an ED IF file with V iew log ic softw are, the fo llow ing a pplicatio ns are required: LI , ic Edito r or Text Editor and then m ap it in an LMF. Figure 3 d em onstra tes this process. D , . This d esign-specific i nform ation is also contained in the E D IF ou tpu t file after conversion, so
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sn 74373

Abstract: SN 74114 IF file with V ie w log ic's ED IF reader (E D IF N E T I) for chip- and board-level sim ulation in , nc tio n Library with the Altera-provided L ibrary M ap p in g File (.lmf) for Valid Logic users. T , in an LMF. LIBRARY user_lib % User Library Mapping File % BEGIN FUNCTION RETURNS FUNCTION RETURNS , implement complex designs in a concise, high-level description (see Figure 4). Figure 4. Sample AHDL File , third-party sim ulatio n tools. O th e r options specify the d egree of detail of the Report File (.rpt) that
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74191, 74192, 74193 circuit diagram

Abstract: IC 7402, 7404, 7408, 7432, 7400 in an LMF. LIBRARY user_lib % User Library Mapping File % BEGIN FUNCTION ALTR_A05 (A_IN, B_IN, C_IN , . Other options specify the degree of detail of the Report File (r p t) that shows how E P L D s have been , each device used in the design. A n Alteraprovided or user-created O utput M apping File (.omf) can be used to map M A X + P L U S II functions to Mentor Graphics functions in the E D IF O utput File , Q u arter-in ch c a rtrid g e tape (Q IC-24, 9 tra ck ) c o n ta in in g all P L S - W S / H P
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truth table for ic 74138

Abstract: 16CUDSLR Easy definition of in p u ts w ith state tables, vector patterns, or predefined patterns State table or , produce an in d u stry -sta n d a rd JEDEC File (.JED) for EPLD p ro g ra m m in g . T he A D P im p lem , free form entry of all syntactical elem ents. Boolean equations need n o t be e n te re d w ith a m in , generating the JEDEC File (.JED) for program m ing. An ADF is created w ith any sta n d ard text editor (in n , achine designs are entered in A ltera's State M achine File (.SMF) form at (see Figure 3). This
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or ic 7473 CMOS

Abstract: pin diagram for IC 7473 HCTS244MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS244MS is supplied in a 20 lead Weld Seal , : These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1992 , File Num ber 2133.1 7-468 Specifications , -0.5V to +7.0V Input Voltage Range, All In p u ts .-0.5V to VCC +0.5V DC Input
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or ic 7473 CMOS pin diagram for IC 7473 circuit diagram for IC 7473 ic 7472 pin diagram pin DIAGRAM OF IC 7474 7474 truth table MIL-STD-1835 CDIP2-T20 CDFP4-F20
Abstract: follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1992 File Number 2133.1 , . Alternate Group A testing In accordance with method 5005 of MIL-STD-883 may be exercised. TABLE 7. TOTAL , HCTS244MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS244MS is supplied in a 20 lead Weld Seal , ).-0.5V to +7.0V Input Voltage Range, All In p u ts .-0.5V to VCC +0.5V DC Input -
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ALU IC 74381

Abstract: encoder IC 74147 to the M essage Processor, w h ic h a u to m a tica lly h ig h lig h ts the source of an erro r in , areas of the sam e design file. If one design is d isp la ye d in tw o w in d o w s of an editor, an y , essage Processor, w h ic h can then locate them in the ap p ro p ria te design file. A successfully , locate the offend ing node in the o rig in al design file, and d isp la y the tim e at w h ic h the , Data Sheet .and More Features IJ IJ IJ J IJ J Log ic synthesis and m in im iza tio n su p p
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ALU IC 74381 encoder IC 74147 16CUDSLR 74139 truth table alu 74382 truth table for 7446 from

16CUDSLR

Abstract: 7474 D flip flop free d esign co n tain s an e rro r in a sch em atic or an A H D L text file, M A X + P L U S rep o rts the e rro r ami tak es the user to the location of the e rro r in the orig in al sch em a tic or text file. P ro p ag atio n d elay s o f critical p ath s can also be d eterm in ed from w ith in b o th the , the G rap h ic E ditor is invoked for schem atics. W h en a text or grap h ic file is saved , M A X + , files w ithin the M A X + P L U S en v iron m en t. A ny A SC II text file, in clu d in g A H D L T D F
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7474 D flip flop free sn 74373 pin diagram of ic 74190 counter schematic diagram 74161 HFJV1 MUX 74151

0221l

Abstract: APPLICATION NOTES CD 7474 IC IO N E LE C TR IC A L AND, A N D -O R , G A TE S (H A R D W IR E D ) NUMBER OF IN P U T S O UTPUT D R , X -N O R C H A R A C T E R IS T IC S S W IT C H IN G D E L A Y T IM E NUM BER OF IN P U TS OUTPUT D , ATE S (H A R D W IR E D ) C H A R A C T E R IS T IC S S W IT C H IN G D E L A Y T IM E OF IN P U T S , data. P ro d u c t* c o n fo rm to ·pacification* - - - - - - - par - the la m a of Taxas In s tru m e , Design Library Addendums MegaModule is a trademark of Texas Instruments Incorporated. In s tr u m e
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TGC100 0221l APPLICATION NOTES CD 7474 IC TGC119 bit-slice IPF 830

LEAPER-3

Abstract: 74189 In addition, the LEAPER-10 supplies the batch function with the project file of the text mode. The , environment of development. Additional, the Company has been qualified by major IC manufacturer such as ATMEL , in a wide variety of modules has dominated the priority in Leap for a long time. To meet the demands of mass production,Gang Programmer SU-2000 is the revolutionized product released in the mid 1997 , channel. The distributors of Leap are located widely in five continents. Although, more partners who can
Leap Electronic
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LEAPER-3 74189 7489 sram 89C51 interfacing with lcd display 4N34 ic 74192 pin configuration PIC16C52/54/54A PIC16C55/56/57/57A/58A PIC12C508/509 PIC16C61 PIC16C620/621/622 PIC16C71/710

IC 7474 pinout

Abstract: â'¢ Maximum Input Current of 1 j iA at 18V Over Full Pack­ l age Temperature Range; 100nA at 18V , 10V - 2.5V at VDD = 15V â'¢ Meets All Requirements of JEDEC Tentative Standard No. 13B, â'Standard Specifications for Description of â'˜Bâ'™ Series CMOS D evicesâ' Functional Diagram Applications â'¢ 3 , Description â Q2 CD4502BMS consists of six inverter/buffers with 3 state outputs. A logic â' 1â' on the OUTPUT DISABLE input produces a high impedance state in all six outputs. This feature permits
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IC 7474 pinout CD4502BM

IC 7474 pinout

Abstract: TTL 7479 · Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC · , 15V · Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices" 12 INHIBIT Functional Diagram Applications · 3 State Hex , INHIBIT 3 D1 Description D2 CD4502BMS consists of six inverter/buffers with 3 state outputs. A logic "1" on the OUTPUT DISABLE input produces a high impedance state in all six outputs. This feature
Intersil
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TTL 7479 IC 7476 pinout pin diagram of ttl 7473 pin DIAGRAM OF IC 7473 ttl 7478 features of ic 7474 ISO9000

pin diagram for IC 7476

Abstract: logic ic 7476 pin diagram FUNCTION OF LOAD CAPACITANCE Chip Dimensions and Pad Layout Dimensions in parenthesis are in , Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC · Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of , OUTPUT DISABLE 12 INHIBIT 3 D1 Description D2 CD4502BMS consists of six inverter/buffers with 3 state outputs. A logic "1" on the OUTPUT DISABLE input produces a high impedance state in all
Intersil
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pin diagram for IC 7476 logic ic 7476 pin diagram ic 7476 pin diagram IOH15

pin diagram for IC 7473

Abstract: CD4502BMS . Users should follow proper I.C. Handling Procedures. Copyright 5 File Number 3334 , Capability · 3 State Outputs D3 · Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices" 13 D5 6 11 Q5 7 10 D4 VSS · , 15V 14 Q6 Q2 · Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA , Description D2 CD4502BMS consists of six inverter/buffers with 3 state outputs. A logic "1" on the
Harris Semiconductor
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d5611 7476 ttl

IC 3-8 decoder 74138 pin diagram

Abstract: full adder using ic 74138 CELL An unprogrammed gate array is an array of b a s ic c e lls . Thus the "gates" in a gate array are , arrays include, in addition to the 1.5K, 2.3K, and 4K gates of logic, two basic sizes of static registered memories: The C4002 and C1502 have up to 2304 bits of RAM organized in an optional by-nine memory , common logic Macros. FEATURES · · · · · · 1.4 ns g a te d e la y ty p ic a l. (2 -in p u t N A N D g , M in im u m 4.75 2.2 VDDx 0 .7 - T y p ic a l 5.0 - M a x im u m 5.25 - Unit volts volts
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IC 3-8 decoder 74138 pin diagram full adder using ic 74138 full adder using Multiplexer IC 74151 pin diagram for IC 7483 for 4 bit adder chip and pin diagram of IC 7491 circuit diagram for IC 7483 full adder MB65XXXX MB66XXXX MB67XXXX

up down counter using IC 7476

Abstract: full adder using Multiplexer IC 74151 Interfacing with bus organized loglc.The AVM (MB66xxxx) series of memory arrays Include, In addition to the , subsldlartas. Nai part of this document m ay be copied or reproduced In any form or by any m eans, o r , should not exceed 90% of the total available In that block. C6600AV, C8000AV ORGANIZATION D evice , provided In place of RAM. The ROM block Is configurable for either 2048 or 4608 total bits, 1111 , -blt word sizes and larger allow division of the RAM block Into two separate RAMs. ROM can be provided In
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up down counter using IC 7476 74154 shift register IC full adder circuit using ic 74153 multiplexer sk 7443 DN 74352 74183 adder 0010S 350AVB 540AVB S50AVB

Truth Table 7485 2 bit comparator

Abstract: IC 7400 pin diagram field. Some of the available netlist formats are shown in Figure 1-5. Figure 1-3. File Menu Options , schematic editors. Since the design resides in a set of directly accessible data tables, you can interact , . General description of ACTIVE-CAD menus A general description of ACTIVE-CAD menus is provided in Using , issues Some of the design issues have been covered in several sections of the manual but with different , applied to any test point on the schematic while the simulation is in progress. Because of that, the
Automated Logic Design Company
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Truth Table 7485 2 bit comparator IC 7400 pin diagram Truth Table 7485 ic D flip flop 7474 74152 data sheet Multiplexer 74152

RCT5 rn

Abstract: 7474 counter circuit diagram that unlike AND-OR PLD architectures, more than 2 levels of logic may be implemented in the PLHS501 , (described in Section 4) includes an array of flip-flops for high performance state machine design , the NAND gate building blocks of the PLHS501. A typical 7474 type of edge-triggered D flip-flop , flip-flop are shown in Figure 1.8. However, please note that the equations of Figure 1.6 define a D , simulations each NAND gate has a maximum tpHL or tpi>i of 8ns (which is the gate delay of a NAND gate in the
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RCT5 rn 7474 counter circuit diagram d-latch by using D flip-flop 7474 8 bit barrel shifter I18N ELECTRO-87

22CV10AP

Abstract: 22cv10 rights of ICT. ICT's products are not authorized for use as critical components in life support devices , , customer service plays an important role in quality assurance. All ICT employees are a part of the customer , observe the life expectancy of each new product. In order to qualify a new product, packaged parts from a , product is addressed. (For more information see Reliability Report RR-1 in Section 6 of the Data Book , logic designs. The PEEL Array family consists of three parts in packages ranging from 24 to 44 pins in
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22CV10AP 22cv10 ict peel nte quick cross palce programmer schematic 22CV10AP* PEEL PEEL18CV8 8000-FFFF 5000-5FFF 4000-40F

spice 74ls00

Abstract: may be used or copied only in accordance with the terms of the agreement. It is against the law to , © 1988-1998 MicroCode Engineering, Inc. All Rights Reserved. Printed in the United States of America , TERMS AND CONDITIONS OF THIS AGREEMENT. IF YOU DO NOT AGREE TO THE TERMS IN THIS AGREEMENT, PROMPTLY , the backup copy at the time of transfer. Your licence terminates at the time of transfer. In no case , variety of applications, we realize that it cannot produce satisfactory results in all applications
MicroCode Engineering
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spice 74ls00
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