N-7075 NRF24E1 NRF24E1G NRF24E1-EVKIT QFN36 nRF2401/CLK1 nRF2401/DATA - Datasheet Archive

 

2.4GHz RF transceiver with nRF24E1 embedded 8051 compatible micro-controller and 9 input, 10 bit ADC FEATURES · ·

 

PRODUCT SPECIFICATION 2.4GHz RF transceiver with nRF24E1 embedded 8051 compatible micro-controller and 9 input, 10 bit ADC FEATURES · · · · · · · · · · · · · nRF2401 2.4GHz RF transceiver 8051 compatible micro-controller compatible with nRF24E2 9 input 10 bit ADC 100kSPS Single 1.9V to 3.6V supply Internal voltage regulators 2 µA standby with wakeup on timer or external pin Internal VDD monitoring Supplied in 36 pin QFN (6x6mm) package 0.18µm CMOS technology Mask programmable version available Low Bill- of Material Ease of design · · · · · · · · · · · · Wireless gamepads Wireless headsets Wireless keyboards Wireless mouse Wireless toys Intelligent sports equipment Industrial sensors PC peripherals Phone peripherals Tags Alarms Remote control APPLICATIONS Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 1 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller TABLE OF CONTENT 1 GENERAL DESCRIPTION.4 1.1 Quick Reference Data.4 1.2 Block Diagram.5 1.3 Pin Diagram.6 1.4 Glossary of Terms.8 2 ARCHITECTURAL OVERVIEW.9 2.1 Microcontroller.9 2.2 PWM.11 2.3 SPI.11 2.4 Port Logic .12 2.5 Power Management.12 2.6 RTC Wakeup Timer, Watchdog and RC Oscillator.12 2.7 XTAL Oscillator.12 2.8 AD Converter.12 2.9 Radio Transceiver.13 3 I/O PORTS .14 3.1 I/O port behavior during RESET.14 3.2 Port 0 (P0) .14 3.3 Port 1 (P1 or SPI port).16 4 nRF2401 2.4GHz TRANSCEIVER SUBSYSTEM .20 4.1 RADIO port (Port 2).20 4.2 Modes of operation .22 4.3 Device configuration.28 4.4 Data package Description.41 4.5 Important RF Timing Data.42 5 A/D CONVERTER .47 5.1 A/D converter subsystem block diagram.48 5.2 A/D converter registers.48 5.3 A/D converter usage .50 5.4 A/D Converter timing.52 5.5 Analog interface guidelines .53 6 PWM .54 7 INTERRUPTS.55 7.1 Interrupt SFRs.55 7.2 Interrupt Processing.58 7.3 Interrupt Masking .59 7.4 Interrupt Priorities.59 7.5 Interrupt Sampling.60 7.6 Interrupt Latency.60 7.7 Interrupt Latency from Power Down Mode.60 7.8 Single-Step Operation.60 Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 2 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 8 WAKEUP TIMER AND WATCHDOG.61 8.1 Tick calibration.61 8.2 RTC Wakeup timer .62 8.3 Watchdog.62 8.4 Reset.64 9 POWER SAVING MODES.65 9.1 Idle Mode .65 9.2 Stop Mode.66 9.3 Power down mode .66 10 MICROCONTROLLER.68 10.1 Memory Organization.68 10.2 Program format in external EEPROM.69 10.3 Instruction Set.70 10.4 Instruction Timing.77 10.5 Dual Data Pointers.77 10.6 Special Function Registers.78 10.7 SFR registers unique to nRF24E1 .82 10.8 Timers/Counters .84 10.9 Serial Interface.92 11 ELECTRICAL SPECIFICATIONS.102 12 PACKAGE OUTLINE .104 12.1 GREEN PACKAGE OUTLINE .104 12.2 PACKAGE OUTLINE, saw type.105 13 ABSOLUTE MAXIMUM RATINGS.106 14 Peripheral RF Information.108 14.2 PCB layout and de-coupling guidelines.109 15 Application example.110 15.1 nRF24E1 with single ended matching network.110 15.2 PCB layout example .112 16 Table of Figures.113 17 Table of Tables.114 18 DEFINITIONS .116 Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 3 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 1 GENERAL DESCRIPTION The nRF24E1 is a nRF2401 2.4GHz radio transceiver with an embedded 8051 compatible microcontroller and a 10-bit 9 input 100 kSPS AD converter. The circuit is supplied by only one voltage in range 1.9V to 3.6V. The nRF24E1 supports the proprietary and innovative modes of the nRF2401 such as ShockBurstTM and DuoCeiverTM. nRF24E1 is a superset of the nRF24E2 chip, which means that it contains all functions of nRF24E2, and that it is fully program compatible with nRF24E2. 1.1 Quick Reference Data Parameter Value Minimum supply voltage Temperature range Maximum RF output power RF receiver sensitivity Maximum RF burst data rate Supply current for microcontroller @ 16MHz @3V Supply current for ADC @100 kSPS Supply current for RF transmit @ -5dBm output power Supply current for RF receive @1000 kbps Supply current in Power Down mode max CPU clock frequency max AD conversion rate ADC Differential nonlinearity (DNL) ADC Integral nonlinearity (INL) ADC Spurious free dynamic range (SFDR) Package Unit 1.9 -40 to +85 0 -90 1000 3 0.9 10.5 19 2 20 100 ±0.5 ±0.75 65 36 pin QFN 6x6 V °C dBm dBm kbps mA mA mA mA µ MHz kSPS LSB LSB dB Table 1-1 : nRF24E1 quick reference data Type Number Description Version NRF24E1 NRF24E1 IC NRF24E1G NRF24E1G IC NRF24E1-EVKIT NRF24E1-EVKIT 36 pin QFN 6x6, saw 36 pin QFN 6x6, green package Evaluation kit A A 1.0 Table 1-2 : nRF24E1 ordering information Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 4 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 1.2 Block Diagram 4k byte RAM 1 AREF AIN0 512 byte 256 byte ROM RAM VDD_PA = 1.8V ANT1 7-channel interrupt AIN1 UART0 AIN2 AIN3 AIN4 ANT2 Timer 0 nAD10100K 10-Bit 100kSPS A/D converter nRF2401 2.4GHz Radio Tranceiver Timer 1 Timer 2 VSS_PA = 0V BIAS AIN5 CPU AIN6 8051 compatible Microcontroller AIN7 IREF 22k XC1 XTAL oscillator XC2 DVDD PWM Low power RC oscillator P0.7 (DIO9) P0.6 (DIO8) P0.5 (DIO7) P0.4 (DIO6) P0.3 (DIO5) P0.2 (DIO4) P0.1 (DIO3) P0.0 (DIO2) P1.1 (DIO1) P1.0 (DIO0) Port logic P1.2 (DIN0) 3 VSS WAKEUP timer Power mgmt Regulators Reset 4 DVDD2 VDD WATCHDOG SPI SDO SCK SDI CSN 25320 EEPROM Figure 1-1 nRF24E1 block diagram plus external components Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 5 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 1.3 Pin Diagram P1.2 (DIN0 ) AIN1 AIN2 VSS VDD VSS AIN3 AIN4 AREF 36 35 34 33 32 31 30 29 28 VDD 1 27 IREF AIN0 2 26 AIN5 DVDD2 3 25 AIN6 nRF24E1 QFN36 QFN36 6x6 P1.0/T2 (DIO0) 4 24 AIN7 P1.1 (DIO1) 5 23 VSS P0.0 (DIO2) 6 22 VDD P0.1/RXD (DIO3) 7 21 VSS_PA P0.2/TXD (DIO4) 8 20 ANT2 P0.3/INT0_N (DIO5) 9 19 ANT1 10 11 12 13 14 15 16 17 18 P0.4/INT1_N (DIO6) P0.5/T0 (DIO7) P0.6/T1 (DIO8) P0.7/PWM (DIO9) DVDD VSS XC2 XC1 VDD_PA Pin 1 2 3 Name VDD AIN0 DVDD2 4 P1.0/T2 Pin function Power Analog input Regulated power Digital I/O 5 6 7 8 P1.1 P0.0 P0.1/RXD P0.2/TXD Digital I/O Digital I/O Digital I/O Digital I/O Description Power Supply (1.9-3.6 V DC) ADC input 0 Digital Power Supply , must be connected to regulator output DVDD Port 1, bit 0 or T2 timer input or SPI clock or DIO0 Port 1, bit 1 or SPI dataout or DIO1 Port 0, bit 0 or EEPROM.CSN or DIO2 Port 0, bit 1 or UART.RXD or DIO3 Port 0, bit 2 or UART.TXD or DIO4 Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 6 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 9 10 11 12 13 14 P0.3/INT0_N P0.4/INT1_N P0.5/T0 P0.6/T1 P0.7/PWM DVDD 15 16 17 18 VSS XC2 XC1 VDD_PA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ANT1 ANT2 VSS_PA VDD VSS AIN7 AIN6 AIN5 IREF AREF AIN4 AIN3 VSS VDD VSS AIN2 AIN1 P1.2 Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Regulator output Power Analog output Analog input Regulator output RF RF Power Power Power Analog input Analog input Analog input Analog input Analog input Analog input Analog input Power Power Power Analog input Analog input Digital input Port 0, bit 3 or INT0_N interrupt or DIO5 Port 0, bit 4 or INT1_N interrupt or DIO6 Port 0, bit 5 or T0 timer input or DIO7 Port 0, bit 6 or T1 timer input or DIO8 Port 0, bit 7 or PWM output or DIO9 Digital voltage regulator output for de-coupling and feed to DVVD2 Ground (0V) Crystal Pin 2 Crystal Pin 1 DC supply (+1.8V) to RF Power Amplifier (ANT1,ANT2) only Antenna interface 1 Antenna interface 2 Ground (0V) Power Supply (1.9-3.6 V DC) Ground (0V) ADC input 7 ADC input 6 ADC input 5 Connection to external Bias reference resistor ADC reference voltage ADC input 4 ADC input 3 Ground (0V) Power Supply (1.9-3.6 V DC) Ground (0V) ADC input 2 ADC input 1 Port 1, bit 2 or SPI datain or DIN0 Table 1-3 : nRF24E1 pin function Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 7 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 1.4 Glossary of Terms Term Description ADC CLK CRC CS CE DR FS GFSK GPIO ISM kSPS MCU OD P0 (or P1) PWM PWR_DWN PWR_UP RTC RX SFR SPI SPS ST_BY TX XTAL Analog to Digital Converter Clock Cyclic Redundancy Check Chip Select Chip Enable Data Ready Full Scale Gaussian Frequency Shift Keying General Purpose In Out Industrial-Scientific-Medical kilo Samples per Second Microcontroller Unit Overdrive (8051) In / Out Port 0 (or Port 1) Pulse Width Modulation Power Down Power Up Real Time Clock Receive (8051) Special Function Register Serial Peripheral Interface Samples per Second Standby Transmit Crystal (oscillator) Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 8 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 2 ARCHITECTURAL OVERVIEW This section will give a brief overview of each of the blocks in the block diagram in Figure 1-1. 2.1 Microcontroller The nRF24E1 microcontroller is instruction set compatible with the industry standard 8051. Instruction timing is slightly different from the industry standard, typically each instruction will use from 4 to 20 clock cycles, compared with 12 to 48 for the "standard". The interrupt controller is extended to support 5 additional interrupt sources; ADC, SPI, RF receiver 1, RF receiver 2 and wakeup timer. There are also 3 timers which are 8052 compatible, plus some extensions, in the microcontroller core. An 8051 compatible UART that can use timer1 or timer2 for baud rate generation in the traditional asynchronous modes is included. The CPU is equipped with 2 data pointers to facilitate easier moving of data in the XRAM area, which is a common 8051 extension. The microcontroller clock is derived directly from the crystal oscillator. 2.1.1 Memory configuration The microcontroller has a 256 byte data ram (8052 compatible, with the upper half only addressable by register indirect addressing). A small ROM of 512 bytes, contains a bootstrap loader that is executed automatically after power on reset or if initiated by software later. The user program is normally loaded into a 4k byte RAM1 from an external serial EEPROM by the bootstrap loader. The 4k byte RAM may also (partially) be used for data storage in some applications. 2.1.2 Boot EEPROM/FLASH If the mask ROM option is not used, the program code for the device must be loaded from an external non-volatile memory. The default boot loader expects this to be a "generic 25320" EEPROM with SPI interface. These memories are available from several vendors with supply ranges down to 1.8V. The SPI interface uses the pins P1.2/DIN0 (EEPROM SDO), P1.0/DIO0 (EEPROM SCK), P1.1/DIO1 (EEPROM SDI) and P0.0/DIO2 (EEPROM CSN). When the boot is completed, the P1.2/DIN0, P1.0/DIO0 and P1.1/DIO1 pins may be used for other purposes such as other SPI devices or GPIO. 2.1.3 Register map The SFR (Special Function Registers) control several of the features of the nRF24E1. Most of the nRF24E1 SFRs are identical to the standard 8051 SFRs. However, there are additional SFRs that control features that are not available in the standard 8051. 1 Optionally this 4k block of memory can be configured as 2k mask ROM and 2k RAM or 4 k mask ROM Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 9 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller The SFR map is shown in the table below. The registers with grey background are registers with industry standard 8051 behavior. Note that the function of P0 and P1 are somewhat different from the "standard" even if the conventional addresses (0x80 and 0x90) are used Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 10 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller X000 F8 F0 E8 E0 D8 D0 C8 C0 B8 X010 X011 X100 X101 X110 X111 RCAP2L RCAP2H TL2 TH2 T1_1V2 T2_1V2 DEV_ OFFSET CK_ CTRL SPI CLK REGX _LSB ADC STATIC TICK_ DV REGX _CTRL TEST_ MODE P0_DIR P0_ALT P1_DIR P1_ALT B EIE ACC EICON PSW T2CON IP RSTREAS B0 A8 IE A0 RADIO (P2) SCON 98 90 88 80 X001 EIP PWM CON ADCCON SPI _DATA PWM DUTY ADC DATAH SPI _CTRL REGX _MSB ADC DATAL SBUF P1 EXIF MPAGE TCON TMOD TL0 TL1 TH0 TH1 CKCON SPC_FNC P0 SP DPL DPH DPL1 DPH1 DPS PCON Table 2-1 : SFR Register map 2.2 PWM The nRF24E1 has one programmable PWM output, which is the alternate function of PO.7 at pin DIO9. The resolution of the PWM is software programmable to 6, 7 or 8 bits. The frequency of the PWM signal is programmable via a 6 bit prescaler from the XTAL oscillator. The duty cycle is programmable between 0% and 100% via one 8-bit register. 2.3 SPI nRF24E1 features a simple single buffered SPI master. The 3 lines of the SPI bus (SDI, SCK and SDO) are multiplexed (by writing to register SPI_CTRL) between the GPIO pins (P1.2/DIN0, P1.0/DIO0 and P1.1/DIO1) and the RF transceiver. The SPI hardware does not generate any chip select signal. The programmer will typically use GPIO bits (from port P0) to act as chip selects for one or more external SPI devices. When the SPI interfaces the RF transceiver, the chip selects are available in an internal GPIO port, P2. Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 11 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 2.4 Port Logic The device has 1 general purpose input and 10 general purpose bi-directional pins. These are by default configured as GPIO pins controlled by the ports P0 (DIO2 to DIO9) and P1 (DIO0, DIO1, DIN0) of the microcontroller. Most of the GPIO pins can be used for multiple purposes under program control. The alternate functions include two external interrupts, UART RXD and TXD, a SPI master port, three enable/count signals for the timers and the PWM output. 2.5 Power Management The nRF24E1 can be set into a low power down mode under program control, and also the ADC and RF subsystems can be turned on or off under program control. The CPU will stop, but all RAM's and registers maintain their values. The low power RC oscillator is running, and so are the watchdog and the RTC wakeup timer (if enabled by software). The current consumption in this mode is typically 2µA. The device can exit the power down mode by an external pin (INT0_N or INT1_N) if enabled, by the wakeup timer if enabled or by a watchdog reset. 2.6 RTC Wakeup Timer, Watchdog and RC Oscillator The nRF24E1 contains a low power RC oscillator which can not be disabled, so it will run continuously as long as VDD = 1.8V. RTC Wakeup Timer and Watchdog are two 16 bit programmable timers that run on the RC oscillator LP_OSC clock. The resolution of the watchdog and wakeup timer is programmable from approximately 300µs to approximately 80ms. By default the resolution is 10ms. The wakeup timer can be started and stopped by user software. The watchdog is disabled after a reset, but if activated it can not be disabled again, except by another reset 2.7 XTAL Oscillator Both the microcontroller, ADC and RF front end run on a crystal oscillator generated clock. A range of crystals frequencies from 4 to 20 MHz may be utilised, but 16 MHz is recommended since it gives best over all performance. For details, please see Crystal Specification on page 108. The oscillator may be started and stopped as requested by software. 2.8 AD Converter The nRF24E1 AD converter has 10 bit dynamic range and linearity with a conversion time of 48 CPU instruction cycles per 10-bit result. The reference for the AD converter is software selectable between the AREF input and an internal 1.22V bandgap reference. Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 12 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller The converter has 9 inputs selectable by software. Selecting one of the inputs 0 to 7 will convert the voltage on the respective AIN0 to AIN7 pin. Input 8 enables software to monitor the nRF24E1 supply voltage by converting an internal input that is VDD/3 with the 1.22V internal reference selected. The AD converter is typically used in a start/stop mode. The sampling time is then under software control. The converter is by default configured as 10 bits. For special requirements, the AD converter can be configured by software to perform 6, 8 or 12 bit conversions. The converter may also be used in differential mode with AIN0 used as inverting input and one of the other 7 external inputs used as noninverting input. In that case the conversion time can be reduced to approximately 2 µs. 2.9 Radio Transceiver The transceiver part of the circuit has identical functionality to the nRF2401 single chip RF transceiver. It is accessed through an internal parallel port and / or an internal SPI. The data ready signals for each DuoCeiverTM receiver output can be programmed as interrupts to the microcontroller or polled via a GPIO port. nRF2401 is a radio transceiver for the world wide 2.4 - 2.5 GHz ISM band. The transceiver consists of a fully integrated frequency synthesizer, a power amplifier, a modulator and two receiver units. Output power and frequency channels and other RF parameters are easily programmable by use of the RADIO register, SFR 0xA0. RF current consumption is only 10.5 mA in TX mode (output power -5dBm) and 18 mA in RX mode. For power saving the transceiver can be turned on / off under software control. Further information about the nRF2401 chip can be found at our website http://www.nordicsemi.no. Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 13 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 3 I/O PORTS The nRF24E1 have two IO ports located at the default locations for P0 and P1 in standard 8051, but the ports are fully bi-directional CMOS and the direction of each pin is controlled by a _DIR and an _ALT bit for each bit as shown in the table below. Pin Default function DIN0 P1.2 DIO0 P1.0 DIO1 P1.1 DIO2 P0.02 DIO3 P0.1 DIO4 P0.2 DIO5 P0.3 DIO6 P0.4 DIO7 P0.5 DIO8 P0.6 DIO9 P0.7 Table 3-1 : Port functions Alternate=1 T2 (timer2 input) SPI_CTRL=01 SPI_DI SPI_SCK SPI_DO EEPROM_CSN RXD (UART) TXD (UART) INT0_N (interrupt) INT1_N (interrupt) T0 (timer0 input) T1 (timer1 input) PWM 3.1 I/O port behavior during RESET During the period the internal reset is active (regardless of whether or not the clock is running), all the port pins are configured as inputs. When program execution starts, the DIO ports are still configured as inputs and the program will need to set the _ALT and/or the _DIR register for the pins that should be used as outputs. 3.2 Port 0 (P0) P0_ALT and P0_DIR control the P0 port function in that order of priority. If the alternate function for port p0.n is set (by P0_ALT.n = 1) the pin will be input or output as required by the alternate function (UART, external interrupt, timer inputs or PWM output), except that the UART RXD direction will still depend on P0_DIR.1. To use INT0_N or INT1_N, the corresponding alternate function must be activated, P0_ALT.3 / P0_ALT.4 When the P0_ALT.n is not set, bit `n' of the port is a GPIO function with the direction controlled by P0_DIR.n. P0.0 is always a GPIO. It will be activated by the default boot loader after reset and should be connected to the CSN of the boot flash. 2 Reserved for use as EEPROM_CSN, works as GPIO P0.0 independent of the "Alternate setting" Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 14 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller Pin 10 P0.0 P0.0 Out (DIO2) P0.1 RXD Out (DIO3) P0.2 TXD Out (DIO4) P0.3 INT0_N In (DIO5) P0.4 INT1_N In (DIO6) P0.5 T0 In (DIO7) P0.6 T1 In (DIO8) P0.7 PWM Out (DIO9) Table 3-2 : Port 0 (P0) functions Data in P0_ALT.n,P0_DIR.n 11 00 P0.0 In P0.0 Out P0.0 In RXD In P0.1 Out P0.1 In TXD Out P0.2 Out P0.2 In INT0_N In P0.3 Out P0.3 In INT1_N In P0.4 Out P0.4 In T0 In P0.5 Out P0.5 In T1 In P0.6 Out P0.6 In PWM Out P0.7 Out P0.7 In 01 Port 0 is controlled by SFR-registers 0x80, 0x94 and 0x95 listed in the table below. Addr SFR (hex) 80 94 R/W #bit R/W R/W 8 8 Init value (hex) FF FF Name Function P0 P0_DIR Port 0, pins DIO9 to DIO2 Direction for each bit of Port 0 0: Output, 1: Input Direction is overridden if alternate function is selected for a pin. 95 R/W 8 00 P0_ALT Select alternate functions for each pin of P0, if corresponding bit in P0_ALT is set, as listed in Table 3-2 : Port 0 (P0) functions, P0.0 has no alternate function,as it is intended as CS for external boot flash memory. It will function as a GPIO bit regardless of P0_ALT.0 Table 3-3 : Port 0 control and data SFR-registers Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 15 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 3.3 Port 1 (P1 or SPI port) The P1 port consists of only 3 pins, one of which is an hardwired input. The function is controlled by SPI_CTRL. When SPI_CTRL is 01, the port is used as a SPI master port. The GPIO bits in port P0 may be used as chip select(s). For timing diagram, please see Figure 3-1 : SPI interface timing. When not used as SPI port, P0_ALT.0 will force P1.0 to be the timer T2 input, P1.1 is now a GPIO. When P0_ALT.0 is 0, also P1.0 is a GPIO. P1.2 (DIN0) is always an input. Pin SPI_CTRL = 01 In SPI_CTRL != 01 P1_ALT.n = 0 P1_DIR.n = 0 P1_DIR.n = 1 P1.0 In P1.0 Out In3 P1.1 In P1.1 Out In P1.2 In P1.2 In P1_ALT.n = 1 P1.0 SCK Out T2 (DIO0) P1.1 SDO Out P1.1 (DIO1) P1.2 SDI In P1.2 (DIN0) Table 3-4 : Port 1 (P1) functions Port 1 is controlled by SFR-registers 0x90, 0x96 and 0x97, and only the 3 lower bits of the registers are used. Addr SFR (hex) 90 96 R/W #bit R/W R/W 3 3 Init value (hex) FF FF Name Function P1 P1_DIR Port 1, pins DIN0, DIO1 and DIO0 Direction for each bit of Port 1 0: Output, 1: Input Direction is overridden if alternate function is selected for a pin, or if SPI_CTRL=01. bit0, DIN0 is always input. 3 P1.1 is actually under control of P1_DIR.1 even when P1_ALT.1 is 1, since there is no alternate function for this pin. Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 16 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 97 R/W 3 00 P1_ALT Select alternate functions for each pin of P1 if corresponding bit in P1_ALT is set, as listed in Table 3-4 : Port 1 (P1) functions If SPI_CTRL is `01', the P1 port is used as SPI master data and clock : 2 -> SDI ­ input to nRF24E1 from slave 1 -> SDO ­ output from nRF24E1 to slave 0 -> SCK ­ output from nRF24E1 to slave Table 3-5 : Port 1 control and data SFR-registers Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 17 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller P1 may also be configured as a SPI master port , and is then controlled by the 3 SFR registers 0xB2, 0xB3, 0xB4 as shown in the table below. Addr SFR (hex) B2 B3 R/W #bit R/W R/W 8 2 Init Name (hex ) 0 SPI_DATA 0 SPI_CTRL Function SPI data input/output 00 -> SPI not used no clock generated 01 -> SPI connected to port P1 (as for booting) another GPIO must be used as chip select (see also Table 3-4 : Port 1 (P1) functions) 10 -> SPI connected to RADIO transmitter/receiver 1 for TX or RX or for transceiver configuration 11 -> SPI connected to RADIO receiver 2 for RX Chip select is a bit of RADIO register (see Table 4-2 : RADIO register ) B4 R/W 2 0 SPICLK Divider factor from CPU clock to SPI clock 00: 1/8 of CPU clock frequency 01: 1/16 of CPU clock frequency 10: 1/32 of CPU clock frequency 11: 1/64 of CPU clock frequency The CPU clock is the oscillator generated clock described in Crystal Specification page 108 Table 3-6 : SPI control and data SFR-registers 3.3.1 SPI interface operation Whenever SPI_DATA register is written to, a sequence of 8 pulses is started on SCK, and the 8 bits of SPI_DATA register are clocked out on SDO with msb first. Simultaneously 8 bits from SDI are clocked into SPI_DATA register. Ouput data is shifted on negedge SCK, and input data is read on posedge SCK. This is illustrated in Figure 3-1 : SPI interface timing. When the 8 bits are done, SPI_READY interrupt (EXIF.5) goes active, and the 8 bits from SDI may be read from SPI_DATA register. The EXIF.5 bit must be cleared before starting another SPI transaction by writing to SPI_DATA register again. SCK, SDO and SDI may be external pins or internal signals, as defined in SPI_CTRL register. Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 18 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller End of write to SPI_DATA register SCK SDO MSB LSB SDI MSB LSB SPI_READY interrupt thSDI tdSCK tdSDO t cSCK tsSDI Figure 3-1 : SPI interface timing tcSCK : SCK cycle time, as defined by SPICLK register. tdSCK : time from writing to SPI_DATA register to first SCK pulse, tdSCK = tcSCK / 2 tdSDO : delay from negedge SCK to new SDO output data, may vary from -40ns to 40ns tsSDI : SDI setup time to posedge SCK, tsSDI > 45ns. thSDI : SDI hold time to posedge SCK, thSDI > 0ns. tdready : time from last SCK pulse to SPI_READY interrupt goes active tdready = 7 CPU clock cycles Note that the above delay, setup and hold time numbers only apply for SPI connected to Port 1; as when SPI is connected to the Radio, SCK,SDO,SDI are all internal signals, not visible to the user. Minimum time between two consecutive SPI transactions will be : 8.5 tcSCK + tdready + tSW where tSW is the time taken by the software to process SPI_READY interrupt, and write to SPI_DATA register. Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 19 of 119 June 2004 tdready PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 4 nRF2401 2.4GHz TRANSCEIVER SUBSYSTEM 4.1 RADIO port (Port 2) The transceiver is controlled by the RADIO port. The RADIO port uses the address normally used by port P2 in standard 8051. However since the radio transceiver is on chip, the port is not bi-directional. The power on default values in the port "latch" also differs from traditional 8051 to match the requirements of the radio transceiver subsystem. Operation of the transceiver is controlled by SFR registers RADIO and SPI_CTRL: Addr SFR (hex) A0 B3 R/W #bit R/W 8 Init value (hex) 80 R/W 2 0 Name Function RADIO General purpose IO for interface to nRF2401 radio transceiver subsystem SPI_CTRL 00 -> SPI not used 01 -> SPI connected to port P1 (boot) 10 -> SPI connected to nRF2401 CH1 11 -> SPI connected to nRF2401 RX CH2 Table 4-1 : nRF2401 2.4GHz transceiver subsystem control registers - SFR 0xA0 and 0xB3 The bits of the RADIO register correspond to similar pins of the nRF2401 single chip, as shown in Table 4-2 : RADIO register . In the documentation the pin names are used, so please note that setting or reading any of these nRF2401 pins, means to write or read the RADIO SFR register accordingly. Please also note that in the transceiver documentation the notation MCU means the onchip 8051 compatible microcontroller. RADIO register bit Read : 7: 0 (not used) 6: DR2, data ready from receiver 2 (available also as interrupt) 5: CLK2, clock for receiver 2 data out 4: DOUT2, data out from receiver 2 3: 0 (not used) 2: DR1, data ready from receiver 1 (available also as interrupt) 1: CLK1, clock for receiver 1 data out corresponding pin name on single chip nRF2401 2.4GHz Transceiver DR2 CLK2 DOUT2 DR1 CLK1 Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 20 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 0: DATA, data out from receiver 1 DATA Write : 7: PWR_UP, power on radio PWR_UP 6: CE, Activate RX or TX mode CE 5: CLK2, clock for receiver 2 data out CLK2 4: Not used 3: CS, Chip select configuration mode CS 2: Not used 1: CLK1, clock for data input or receiver 1 data out CLK1 0: DATA, configuration or TX data input DATA Table 4-2 : RADIO register - SFR 0xA0, default initial data value is 0x80. Note : Some of the pins are overridden when SPI_CTRL=1x, see Table 4-3 : Transceiver SPI interface. 4.1.1 Controlling the transceiver via SPI interface. It is more convenient to use the built-in SPI interface to do the most common transceiver operations as RF configuration and ShockBurstTM RX or TX. Please see Table 3-6 : SPI control and data SFR-registers for use of SPI interface. The radio port will be connected in different ways to the SPI hardware when SPI_CTRL is `1x'. When SPI_CTRL is `0x', all radio pins are connected directly to their respective port pins. SPI signal SPI_CTRL=10 (binary) CS RADIO_wr.6 (CE) for ShockBurstTM (active high) RADIO_wr.3 (CS) for Configuration SCK nRF2401/CLK1 nRF2401/CLK1 SDI nRF2401/DATA nRF2401/DATA SDO nRF2401/DATA nRF2401/DATA ShockBurstTM data RADIO_rd.2 (DR1) ready Table 4-3 : Transceiver SPI interface. SPI_CTRL=11 RADIO_wr.6 (CE) nRF2401/CLK2 nRF2401/CLK2 nRF2401/DOUT2 nRF2401/DOUT2 not used RADIO_rd.6 (DR2) Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 21 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller SPI_CTRL RADIO register nRF2401 Tranceiver read bitno write -7 PWR_UP DR2 6 CE CLK2 5 CLK2 DOUT2 4 3 CS DR1 2 CLK1 1 CLK1 DATA 0 DATA input output -PWR_UP CE DR2 CLK2 CLK2 DOUT2 CS DR1 CLK1 CLK1 DATA DATA 3 2 2 SPI interface MUX MUX MUX SCK SDO SDI MUX 2 3 Figure 4-1 : Transceiver interface 4.1.2 RADIO port behavior during RESET During the period the internal reset is active (regardless of whether or not the clock is running), the RADIO outputs that control the nRF2401 transceiver subsystem are forced to their respective default values (RADIO.3=0 (CS), RADIO.6=0 (CE) RADIO.7=1 (PWR_UP). When program execution starts, these ports will remain at those default levels until the programmer actively changes them by writing to the RADIO register. 4.2 Modes of operation 4.2.1 Overview The nRF2401 subsystem can be set in the following main modes depending on three control pins: Mode Active (RX/TX) Configuration Stand by Power down PWR_UP CE CS 1 1 1 0 1 0 0 X 0 1 0 X Table 4-4 nRF2401 subsystem main modes Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 22 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 4.2.2 Active modes The nRF2401 subsystem has two active (RX/TX) modes: · · ShockBurstTM Direct Mode (not supported by nRF24E1) The device functionality in these modes is decided by the content of a configuration word. This configuration word is presented in the configuration section. Please note that Direct mode is not supported, as this will require a more powerful CPU than 8051. 4.2.3 ShockBurstTM The ShockBurstTM technology uses on-chip FIFO to clock in data at a low data rate and transmit at a very high rate thus enabling extremely power reduction. When operating the nRF2401 subsystem in ShockBurstTM, you gain access to the high data rates (1 Mbps) offered by the 2.4 GHz band without the need of a costly, high-speed microcontroller (MCU) for data processing. By putting all high speed signal processing related to RF protocol on-chip, the nRF24E1 offers the following benefits: · · · Highly reduced current consumption Lower system cost (facilitates use of less expensive microcontroller) Greatly reduced risk of `on-air' collisions due to short transmission time The nRF2401 subsystem can be programmed using a simple 3-wire interface where the data rate is decided by the speed of the CPU. By allowing the digital part of the application to run at low speed while maximizing the data rate on the RF link, the ShockBurstTM mode reduces the average current consumption in applications considerably. 4.2.3.1 ShockBurstTM principle When the nRF2401 subsystem is configured in ShockBurstTM, TX operation is conducted in the following way (10 kbps for the example only). 10 kbps effective 8051 MCU nRF2401 subsyst. FIFO ShockBurstTM 1Mbps Figure 4-2Clocking in data with CPU and sending with ShockBurstTM technology Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 23 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller Without ShockBurstTM, running at speed dictated by 10Kbs MCU 10mA period 10mA period 0 20 40 60 10Kbs MCU with ShockBurst TM 80 100 120 140 160 180 200 220 Time mS Figure 4-3 RF Current consumption with & without ShockBurstTM technology Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 24 of 119 June 2004 240 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller NO nRF2401 in ShockBurst TM TX (CE=hi)? YES Data content of registers: uController Loading ADDR and PAYLOAD data ADDR PAYLOAD Maximum 256 bits nRF2401 Calculating CRC ADDR PAYLOAD CRC NO CE=Low? YES nRF2401 Adding Preamble nRF2401 Sending ShockBurst TM Package (250 or 1000kbps) YES Preamble ADDR PAYLOAD CRC Input FIFO not Empty NO Sending completed? Figure 4-4 Flow Chart ShockBurstTM Transmit of nRF2401 subsystem 4.2.3.2 ShockBurstTM Transmit: 4.2.3.2.1 CPU interface pins: CE, CLK1, DATA 1. When the application CPU has data to send, set CE high. This activates nRF2401 on-board data processing. 2. The address of the receiving node (RX address) and payload data is clocked into the nRF2401 subsystem. The application protocol or CPU sets the speed L -> H to start A/D conversion. This bit is internally synchronized to the ADC clock Ignored if ADCRUN is set. Set to have the A/D converter run continuously CSTARTN is ignored in this case Set to 0 to put A/D converter in power down state Select reference for A/D converter 0: Use internal band gap reference (nominally 1.22V) 1: Use external pin AREF for reference Ignored if ADCSEL=8. Select input AIN0 to AIN7 ADCSEL=8 will select internal VDD/3, and also automatically select internal bandgap reference For n=0.7, ADCSEL=n will select input pin AINn Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 48 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller Table 5-1 : ADCCON register, SFR 0xA1, default initial data value is 0x80. 5.2.2 Bit(s) 7 ADCSTATIC register, SFR 0xA4 Function Enable differential measurements, AIN0 must be used as inverting input and one of the other inputs AIN1 to AIN7, as selected by ADCSEL, must be used as noninverting input. 6 SLEEP Set A/D converter in a reduced power mode 5 CLK8 0 : ADCCLK frequency = CPU clock divided by 32 1 : ADCCLK frequency = CPU clock divided by 8 4­2 ADCBIAS Control A/D converter bias current No need to change for nRF24E1 operation 1-0 ADCRES Select A/D converter resolution 00: 6-bit, result in ADCDATAH 5-0 01: 8-bit, result in ADCDATAH 10: 10-bit, result in ADCDATAH,ADCDATAL.7-6 11: 12-bit, result in ADCDATAH,ADCDATAL.7-4 Table 5-2 : ADCSTATIC register, SFR 0xA4, default initial data value is 0x0A. 5.2.3 Bit(s) 7-0 5.2.4 Bit(s) 7-4 Name DIFFM ADCDATAH register, SFR 0xA2 Name ADCDATAH Function Most significant 8 bits of A/D converter result. For 6-bit conversions ADCDATAH.7-6 is `00' ADCDATAL register, SFR 0xA3 Name ADCDATAL Function Least significant part of A/D converter result when resolution is 12 or 10 bits, leftjustified. For 10-bit conversions ADCDATAH.5-4 is `00' 3 not used 2 ADCUF Underflow in conversion. Data is all 0's 1 ADCOF Overflow in conversion. Data is all 1's 0 ADCRNG Overflow or underflow in conversion (ADCUF | ADCOF) Table 5-3 : ADC data SFR-registers, SFR 0xA2 and 0xA3. Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 49 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 5.3 A/D converter usage 5.3.1 End of conversion. A signal ADC_EOC is available in the EXIF.4 bit (Interrupt 2 flag) and it is set to 1 by A/D converter when a conversion (single step or continuous mode) is completed, see Table 7-4 : EXIF Register ­ SFR 0x91. For timing of ADC_EOC, see Figure 5-3 and Figure 5-4 5.3.2 Measurements with external reference When EXTREF (ADCCON.4) is set to 1 and ADCSEL (ADCCON.3-0) selects an input AIN i ( i.e. AIN 0 to AIN 7), the result in ADCDATA is directly proportional to the ratio between the voltage on the selected input, and the voltage on pin AREF. AIN i voltage = AREF voltage * ADCDATA / 2*N Where N is the number of bits set in ADCRES (ADCSTATIC.1-0) and ADCDATA is the resulting bits in ADCDATAH (and ADCDATAL if N > 8). For differential measurements a simular equation apply : (AIN i - AIN 0)voltage = AREF voltage * (ADCDATA -2*(N-1) / 2*N This mode of operation is normally selected for sources where the voltage is depending on the supply voltage (or another variable voltage), like shown in Figure 5-2 below. The resistor R1 is selected to keep AREF = 1.5V for the maximum VDD voltage. Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 50 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller SUPPLY R1 VDD AREF nRF24E1 R2 AIN0 R3 AIN1 Figure 5-2 Typical use of A/D with 2 ratiometric inputs 5.3.3 Measurements with internal reference When EXTREF (ADCCON.4) is set to 0 and ADCSEL (ADCCON.3-0) selects an input AIN i (i.e. AIN 0 to AIN 7), the result in ADCDATA is directly proportional to the ratio between the voltage on the selected input, and the internal bandgap reference (nominally 1.22V). if single ended input : AINi voltage = 1.22 V * ADCDATA / 2*N if differential input : (AINi - AIN 0) voltage = 1.22 V * (ADCDATA -2*(N-1) / 2*N Where N is the number of bits set in ADCRES (ADCSTATIC.1-0) and ADCDATA is the result bits in ADCDATAH (and ADCDATAL if N > 8). This mode of operation is normally selected for sources where the voltage is not depending on the supply voltage. Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 51 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 5.3.4 Supply voltage measurement When ADCSEL (ADCCON.3-0) is set to 8, the ADC will use the internal bandgap reference (nominally 1.22V), and the input is 1/3 of the voltage on the VDD pins. The result in ADCDATA is thus directly proportional to the VDD voltage. VDD voltage = 3.66 V * ADCDATA / 2*N Where N is the number of bits set in ADCRES (ADCSTATIC.1-0) and ADCDATA is the result bits in ADCDATAH (and ADCDATAL if N > 8). 5.4 A/D Converter timing ADCCLK CSTARTN input signal sampled tConv ADC_EOC ADCDATA any previously converted value is held until new ADC_EOC Figure 5-3 : Timing diagram single step conversion. ADCRUN=0, and conversion is started at first posedge ADCCLK after CSTARTN has gone high. A pulse is generated on ADC_EOF when the converted value is available on the ADCDATA bus. Conversion time tConv depends on resolution, tConv = N/2 + 3 clock cycles, where N is number of resolution bits. In the figure a 10 bit conversion is shown. Minimum width of a CSTARTN pulse is 1 clock cycle. If a new CSTARTN pulse comes before previous conversion has finished, the previous conversion will be aborted. Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 52 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller ADCCLK input signal sample n n+1 n+2 tConv ADC_EOC tCycle ADCDATA sample n-1 sample n Figure 5-4 : Timing diagram continuous mode conversion. ADCRUN=1, and CSTARTN is ignored. Cycle time tCycle is the time between each conversion. tCycle = N/2 +1 clock cycles, where N is number of resolution bits. The figure is showing 10 bit conversions. 5.5 Analog interface guidelines The input impedance of analog inputs should preferably be in range 100-1000 O, and in any case be less than 10 kO. Small capacitors on inputs (e.g. 200pF) are recommended for decoupling, see also Figure 15-1 for application example. If AIN inputs goes beyond the selected reference voltage, the ADC will clip and the result will be the maximum code. Absolute maximum for any AIN voltage is 2.0V. Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 53 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 6 PWM The nRF24E1 PWM output is a one-channel PWM with a 2 register interface. The first register, PWMCON, enables PWM function and PWM period length, which is the number of clock cycles for one PWM period, as shown in the table below. The other register, PWMDUTY, controls the duty cycle of the PWM output signal. When this register is written, the PWM signal will change immediately to the new value. This can result in 4 transitions within one PWM period, but the transition period will always have a "DC value" between the "old" sample and the "new" sample. The table shows how PWM frequency (or period length) and PWM duty cycle are controlled by the settings in the two PWM SFR-registers. For a crystal frequency of 16 MHz, PWM frequency range will be about 1-253 kHz. PWMCON[7:6] PWM frequency 0 (PWM module inactive) 0 1 63 (PWMCON [5 : 0] + 1) 1 f XO 127 ( PWMCON [5 : 0] + 1) 1 f XO 255 ( PWMCON [5 : 0] + 1) 00 PWMDUTY (duty cycle) PWMDUTY [5 : 0] 63 PWMDUTY [6 : 0] 127 PWMDUTY 255 f XO 01 10 11 PWM is controlled by SFR 0xA9 and 0xAA. Addr SFR (hex) A9 AA R/W #bit Init (hex) Name Function PWM control register 7-6: Enable / period length select 00: Disable PWM 01: Period length is 6 bit 10: Period length is 7 bit 11: Period length is 8 bit 5-0: PWM frequency prescale factor (see table above) PWM duty cycle (6 to 8 bits according to period length) R/W 8 0 PWMCON R/W 8 0 PWMDUTY Table 6-1 : PWM control registers - SFR 0xA9 and 0xAA Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 54 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 7 INTERRUPTS nRF24E1 supports the following interrupt sources: Interrupt signal INT0_N Description External interrupt, active low, configurable as edge-sensitive or levelsensitive, at Port P0.3 TF0 Timer 0 interrupt INT1_N External interrupt, active low, configurable as edge-sensitive or levelsensitive, at Port P0.4 TF1 Timer 1 interrupt TF2 or EXF2 Timer 2 interrupt TI or RI Receive/transmit interrupt from Serial Port int2 Internal ADC_EOC (end of AD conversion) interrupt int3 Internal SPI_READY interrupt int4 Internal RADIO.DR1 interrupt (a packet is ready from receiver 1) int5 Internal RADIO.DR2 interrupt (a packet is ready from receiver 2) wdti Internal RTC wakeup timer interrupt Table 7-1 : nRF24E1 interrupt sources 7.1 Interrupt SFRs The following SFRs are associated with interrupt control: - IE ­ SFR 0xA8 ( Table 7-2) - IP ­ SFR 0xB8 ( Table 7-3) - EXIF ­ SFR 0x91 ( Table 7-4) - EICON ­ SFR 0xD8 ( Table 7-5) - EIE ­ SFR 0xE8 ( Table 7-6) - EIP ­ SFR 0xF8 ( Table 7-7) The IE and IP SFRs provide interrupt enable and priority control for the standard interrupt unit, as with industry standard 8051. The EXIF, EICON, EIE, and EIP registers provide flags, enable control, and priority control for the extended interrupt unit. Table 7-2 explains the bit functions of the IE register. Bit IE.7 IE.6 IE.5 Function EA - Global interrupt enable. Controls masking of all interrupts. EA = 0 disables all interrupts (EA overrides individual interrupt enable bits). When EA = 1, each interrupt is enabled or masked by its individual enable bit. Reserved. Read as 0. ET2 - Enable Timer 2 interrupt. ET2 = 0 disables Timer 2 interrupt (TF2). ET2 = 1 enables interrupts generated by the TF2 or EXF2 flag. Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 55 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller IE.4 ES - Enable Serial Port interrupt. ES = 0 disables Serial Port interrupts (TI and RI). ES = 1 enables interrupts generated by the TI or RI flag. IE.3 ET1 - Enable Timer 1 interrupt. ET1 = 0 disables Timer 1 interrupt (TF1). ET1 = 1 enables interrupts generated by the TF1 flag. IE.2 EX1 - Enable external interrupt 1. EX1 = 0 disables external interrupt 1 (INT1_N). EX1 = 1 enables interrupts generated by the INT1_N pin. IE.1 ET0 - Enable Timer 0 interrupt. ET0 = 0 disables Timer 0 interrupt (TF0). ET0 = 1 enables interrupts generated by the TF0 flag. IE.0 EX0 - Enable external interrupt 0. EX0 = 0 disables external interrupt 0 (INT0_N). EX0 = 1 enables interrupts generated by the INT0_N pin. Table 7-2 : IE Register ­ SFR 0xA8 Table 7-3 explains the bit functions of the IP register. Bit IP.7 IP.6 IP.5 Function Reserved. Read as 1. Reserved. Read as 0. PT2 - Timer 2 interrupt priority control. PT2 = 0 sets Timer 2 interrupt (TF2) to low priority. PT2 = 1 sets Timer 2 interrupt to high priority. IP.4 PS - Serial Port interrupt priority control. PS = 0 sets Serial Port interrupt (TI or RI) to low priority. PS = 1 sets Serial Port interrupt to high priority. IP.3 PT1 - Timer 1 interrupt priority control. PT1 = 0 sets Timer 1 interrupt (TF1) to low priority. PT1 = 1 sets Timer 1 interrupt to high priority. IP.2 PX1 - External interrupt 1 priority control. PX1 = 0 sets external interrupt 1 (INT1_N) to low priority. PT1 = 1 sets external interrupt 1 to high priority. IP.1 PT0 - Timer 0 interrupt priority control. PT0 = 0 sets Timer 0 interrupt (TF0) to low priority. PT0 = 1 sets Timer 0 interrupt to high priority. IP.0 PX0 - External interrupt 0 priority control. PX0 = 0 sets external interrupt 0 (INT0_N) to low priority. PT0 = 1 sets external interrupt 0 to high priority. Table 7-3 : IP Register ­ SFR 0xB8 Table 7-4 explains the bit functions of the EXIF register. Bit EXIF.7 EXIF.6 Function IE5 - Interrupt 5 flag. IE5 = 1 indicates that a rising edge was detected on the RADIO.DR2 signal.(see ch. 5.1.RADIO) IE5 must be cleared by software. Setting IE5 in software generates an interrupt, if enabled. IE4 - Interrupt 4 flag. IE4 = 1 indicates that a rising edge was detected on the RADIO.DR1 signal.(see ch. 5.1.RADIO) IE4 must be cleared by software. Setting IE4 in software generates an interrupt, if enabled. Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 56 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller EXIF.5 IE3 - Interrupt 3 flag. IE3 = 1 indicates that the internal SPI module has sent or received 8 bits, and is ready for a new command. IE3 must be cleared by software. Setting IE3 in software generates an interrupt, if enabled. EXIF.4 IE2 - Interrupt 2 flag. IE2 = 1 indicates that a rising edge was detected on the ADC_EOC signal. (see ch.5.3.1 End of conversion.) IE2 must be cleared by software. Setting IE2 in software generates an interrupt, if enabled. EXIF.3 Reserved. Read as 1. EXIF.2-0 Reserved. Read as 0. Table 7-4 : EXIF Register ­ SFR 0x91 Table 7-5 explains the bit functions of the EICON register. Bit EICON.7 EICON.6 EICON.5 EICON.4 EICON.3 Function Not used. Reserved. Read as 1. Reserved. Read as 0. Reserved. Read as 0. WDTI - RTC wakeup timer interrupt flag. WDTI = 1 indicates a wakeup timer interrupt was detected. WDTI must be cleared by software before exiting the interrupt service routine. Otherwise, the interrupt occurs again. Setting WDTI in software generates a wakeup timer interrupt, if enabled. Reserved. Read as 0. EICON.20 Table 7-5 : EICON Register ­ SFR 0xD8 Table 7-6 explains the bit functions of the EIE register. Bit EIE.7-5 EIE.4 Function Reserved. Read as 1. EWDI - Enable RTC wakeup timer interrupt. EWDI = 0 disables wakeup timer interrupt (wdti). EWDI = 1 enables interrupts generated by wakeup. EIE.3 EX5 - Enable interrupt 5. EX5 = 0 disables interrupt 5 (RADIO.DR2). EX5 = 1 enables interrupts generated by the RADIO.DR2 signal. EIE.2 EX4 - Enable interrupt 4. EX4 = 0 disables interrupt 4 (RADIO.DR1). EX4 = 1 enables interrupts generated by the RADIO.DR1 signal. EIE.1 EX3 - Enable interrupt 3. EX3 = 0 disables interrupt 3 (SPI_READY). EX3 = 1 enables interrupts generated by the SPI_READY signal. EIE.0 EX2 - Enable interrupt 2. EX2 = 0 disables interrupt 2 (ADC_EOC). EX2 = 1 enables interrupts generated by the ADC_EOC signal. Table 7-6 : EIE Register ­ SFR 0xE8 Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 57 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller Table 7-7 explains the bit functions of the EIP register. Bit EIP.7-5 EIP.4 Function Reserved. Read as 1. PWDI - RTC wakeup timer interrupt priority control. WDPI = 0 sets wakeup timer interrupt (wdti) to low priority. PS = 1 sets wakeup timer interrupt to high priority. EIP.3 PX5 - interrupt 5 priority control. PX5 = 0 sets interrupt 5 (RADIO.DR2) to low priority. PX5 = 1 sets interrupt 5 to high priority. EIP.2 PX4 - interrupt 4 priority control. PX4 = 0 sets interrupt 4 (RADIO.DR1) to low priority. PX4 = 1 sets interrupt 4 to high priority. EIP.1 PX3 - interrupt 3 priority control. PX3 = 0 sets interrupt 3 (SPI_READY) to low priority. PX3 = 1 sets interrupt 3 to high priority. EIP.0 PX2 - interrupt 2 priority control. PX2 = 0 sets interrupt 2 (ADC_EOC) to low priority. PX2 = 1 sets interrupt 2 to high priority. Table 7-7 : EIP Register ­ SFR 0xF8 7.2 Interrupt Processing When an enabled interrupt occurs, the CPU vectors to the address of the interrupt service routine (ISR) associated with that interrupt, as listed in Table 7-8. The CPU executes the ISR to completion unless another interrupt of higher priority occurs. Each ISR ends with an RETI (return from interrupt) instruction. After executing the RETI, the CPU returns to the next instruction that would have been executed if the interrupt had not occurred. Interrupt Description INT0_N TF0 INT1_N TF1 TI or RI External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial Port transmit or receive Timer 2 interrupt ADC_EOC interrupt SPI_READY interrupt RADIO.DR1 interrupt RADIO.DR2 interrupt RTC wakeup timer TF2 or EXF2 int2 int3 int4 int5 wdti Natural Priority (lowest number gives highest priority) 1 2 3 4 5 Interrupt Vector 6 8 9 10 11 12 0x2B 0x43 0x4B 0x53 0x5B 0x63 0x03 0x0B 0x13 0x1B 0x23 Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 58 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller interrupt Table 7-8 : Interrupt Natural Vectors and Priorities An ISR can only be interrupted by a higher priority interrupt. That is, an ISR for a low-level interrupt can be interrupted only by a high-level interrupt. The CPU always completes the instruction in progress before servicing an interrupt. If the instruction in progress is RETI, or a write access to any of the IP, IE, EIP, or EIE SFRs, the CPU completes one additional instruction before servicing the interrupt. 7.3 Interrupt Masking The EA bit in the IE SFR (IE.7) is a global enable for all interrupts. When EA = 1, each interrupt is enabled/masked by its individual enable bit. When EA = 0, all interrupts are masked. Table 7-9 provides a summary of interrupt sources, flags, enables, and priorities. Interrupt INT0_N TF0 INT1_N TF1 TI or RI Description External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial Port transmit or receive Flag TCON.1 TCON.5 TCON.3 TCON.7 SCON.0 (RI), SCON.1 (TI) Enable IE.0 IE.1 IE.2 IE.3 IE.4 Control IP.0 IP.1 IP.2 IP.3 IP.4 TF2 or EXF2 Timer 2 interrupt T2CON.7 (TF2), T2CON.6 (EXF2) EXIF.4 EXIF.5 EXIF.6 EXIF.7 EICON.3 IE.5 IP.5 EIE.0 EIE.1 EIE.2 EIE.3 EIE.4 EIP.0 EIP.1 EIP.2 EIP.3 EIP.4 int2 int3 int4 int5 wdti ADC_EOC interrupt SPI_READY interrupt RADIO.DR1 interrupt RADIO.DR2 interrupt RTC wakeup timer interrupt Table 7-9 : Interrupt Flags, Enables, and Priority Control 7.4 Interrupt Priorities There are two stages of interrupt priority assignment: interrupt level and natural priority. The interrupt level (high, or low) takes precedence over natural priority. All interrupts can be assigned either high or low priority. In addition to an assigned priority level (high or low), each interrupt has a natural priority, as listed in Table 7-8. Simultaneous interrupts with the same priority level (for example, both high) are resolved according to their natural priority. For example, if Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 59 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller INT0_N and int2 are both programmed as high priority, INT0_N takes precedence. Once an interrupt is being serviced, only an interrupt of higher priority level can interrupt the service routine of the interrupt currently being serviced. 7.5 Interrupt Sampling The internal timers and serial port generate interrupts by setting their respective SFR interrupt flag bits. The CPU samples external interrupts once per instruction cycle, at the rising edge of CPU_clk at the end of cycle C4. The INT0_N and INT1_N signals are both active low and can be programmed through the IT0 and IT1 bits in the TCON SFR to be either edge-sensitive or level-sensitive. For example, when IT0 = 0, INT0_N is level-sensitive and the CPU sets the IE0 flag when the INT0_N pin is sampled low. When IT0 = 1, INT0_N is edge-sensitive and the CPU sets the IE0 flag when the INT0_N pin is sampled high then low on consecutive samples. To ensure that edge-sensitive interrupts are detected, the corresponding ports should be held high for four clock cycles and then low for four clock cycles. Level-sensitive interrupts are not latched and must remain active until serviced. 7.6 Interrupt Latency Interrupt response time depends on the current state of the CPU. The fastest response time is five instruction cycles: one to detect the interrupt, and four to perform the LCALL to the ISR.The maximum latency (thirteen instruction cycles) occurs when the CPU is currently executing an RETI instruction followed by a MUL or DIV instruction. The thirteen instruction cycles in this case are: one to detect the interrupt, three to complete the RETI, five to execute the DIV or MUL, and four to execute the LCALL to the ISR. For the maximum latency case, the response time is 13 x 4 =52clock cycles. 7.7 Interrupt Latency from Power Down Mode. nRF24E1 may be set into Power Down Mode by writing 0x2 or 0x3 to SFR 0xB6, register CK_CTRL. The CPU will then perform a controlled shutdown of clock and power regulator. The system can only be restarted from pins INT0_N or INT1_N, or an RTC wakeup or a Watchdog reset. In this case the CPU cannot respond until the clock and power regulator have restarted, which may take 3 to 4 LP_OSC cycles. This delay may vary from 0.6ms to 4 ms depending on processing, temperature and supply voltage. In the same way, the shutdown also takes from 2 to 3 LP_OSC cycles, which will be in the range of 0.4 - 3ms. 7.8 Single-Step Operation The nRF24E1 interrupt structure provides a way to perform single-step program execution. When exiting an ISR with an RETI instruction, the CPU will always execute at least one instruction of the task program. Therefore, once an ISR is Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 60 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller entered, it cannot be re-entered until at least one program instruction is executed. To perform single-step execution, program one of the external interrupts (for example, INT0_N) to be level-sensitive and write an ISR for that interrupt that terminates as follows: JNB TCON.1,$ ; JB TCON.1,$ ; RETI ; wait for high on INT0_N wait for low on INT0_N return for ISR The CPU enters the ISR when INT0_N goes low, then waits for a pulse on INT0_N. Each time INT0_N is pulsed, the CPU exits the ISR, executes one program instruction, then re-enters the ISR. 8 WAKEUP TIMER AND WATCHDOG 8.1 Tick calibration The "TICK" is an interval that is nominally 10ms long. This interval is the unit of resolution both for the watchdog and the RTC wakeup timer. The LP_OSC clock source of the "TICK" is very inaccurate, and may vary from 6ms to 30ms depending on processing, temperature and supply voltage. That means that Watchdog and RTC may not be used for any accurate timing functions. The accuracy can be improved by calibrating the TICK value at regular intervals. The register TICK_DV controls how many LP_OSC periods elapse between each TICK. The frequency of the LP_OSC (between 1 kHz and 5 kHz) can be measured by timer2 in capture mode with t2ex enabled (EXEN2=1). The signal connected to t2ex has exactly half the frequency of LP_OSC. The 16-bit difference between two consecutive captures in SFR-registers{RCAP2H,RCAP2L} is proportional to the LP_OSC period. For details about timer2 see ch. 10.8.3 and Figure 10-5 : Timer 2 ­ Timer/Counter with Capture TICK is controlled by SFR 0xB5. Addr SFR B5 R/W #bit R/W 8 Init hex 1D Name Function TICK_DV Divider that's used in generating TICK from LP_OSC frequency. fTICK = fLP_OSC / (1 + TICK_DV) The default value gives a TICK of 10ms nominal as default. Table 8-1 : TICK control register - SFR 0xB5 Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 61 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 8.2 RTC Wakeup timer The RTC is a simple 16 bit down counter that produces an interrupt and reloads automatically when the count reaches zero. This process is initially disabled, and will be enabled with the first write to the timer latch. Writing the timer latch will always be followed by a reload of the counter. The counter may be disabled again by writing a disable opcode to the control register. Both the latch and the counter value may be read by giving the respective codes in the control register, see description in Table 8-2 This counter is used for a wakeup sometime in the future (a relative time wakeup call). If `N' is written to the counter, the first wakeup will happen from somewhere between `N+1' and `N+2' "TICK" from the completion of the write, thereafter a new wakeup is issued every "N+1" "TICK" until the unit is disabled or another value is written to the latch. The wakeup timer is connected to the WDTI interrupt of the CPU. The programmer may poll the EICON.3 flag or enable the interrupt. If the oscillator is stopped, the wakeup interrupt will restart the oscillator regardless of the state of EIE.4 interrupt enable. The nRF24E1 do not provide any "absolute time functions". Absolute time functions in nRF24E1 can well be handled in software since our RAM is continuously powered even when in sleep mode. There will be an application note with the required code to implement the complete absolute time function using some 100 bytes of code and 12 IRAM locations (with 2 alarms). 8.3 Watchdog The watchdog is activated upon writing 0x08 to its control register SFR 0xAD. It can not be disabled by any other means than a reset. The watchdog register is loaded by writing a 16bit value to the two 8-bit data registers (SFR 0xAB and 0xAC) and then the writing the correct opcode to the control register. The watchdog will then count down towards 0 and when 0 is reached the complete microcontroller will be reset . To avoid the reset, the software must load new values into the watchdog register sufficiently often. Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 62 of 119 June 2004 PRODUCT SPECIFICATION nRF24E1 2.4 GHz Radio Transceiver with Microcontroller 8-bit CPU register REGX_CTRL 8-bit CPU register REGX_MSB 8-bit CPU register REGX_LSB 16-BIT 16-BIT BUS Load Load 16-BIT 16-BIT DOWN COUNTER Load Zero 16-BIT 16-BIT REGISTER 16-BIT 16-BIT DOWN COUNTER Zero WAKEUP INT TICK WATCHDOG_RESET Figure 8-18-2 : RTC and watchdog block diagram RTC and Watchdog are controlled by SFRs 0xAB, 0xAC and 0xAD. These 3 registers REGX_MSB, REGX_LSB and REGX_CTRL are used to interface the blocks running on the slow LP_OSC clock. The 16-bit register {REGX_MSB, REGX_LSB} can be written or read as two bytes from the CPU. Typical sequences are: Write: Wait until not busy. Write REGX_MSB, Write REGX_LSB, Write REGX_CTRL Read: Wait until not busy. Write REGX_CTRL, Wait until not busy. Read REGX_MSB, Read REGX_LSB Note : please also wait until not busy before accessing SFR 0xB6 CK_CTRL (page 66) Addr SFR (hex) AB R/W # b i t R/W 8 AC R/W 8 Init (hex) 0 0 Name Function REGX_ MSB REGX_ LSB Most significant part of 16 bit register for interface to Watchdog and RTC Least significant part of 16 bit register for interface to Watchdog and RTC Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 63 of 119 June 2004 PRODUCT SPEC