500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

mxic

Catalog Datasheet MFG & Type PDF Document Tags

block diagram for automatic room power control layout

Abstract: 28F2100B 128K words of 16 bits switchable. MXIC's Flash memories offer the most cost-effective and reliable read , ) controls. MXIC's Flash memories augment EPROM function a lity w ith in -c irc u it e le c tric a l era sure , algorithms. The hig he st degree of la tch-up p ro te ctio n is achieved with MXIC's proprietary non-epi , time of the MX28F21ÛÛB is less than 5 seconds. MX28F21OOB AUTOMATIC ERASE ALGORITHM MXIC's , cycle, addresses are latched on the falling edge, and data is latched on the rising edge of WE . MXIC's
-
OCR Scan
block diagram for automatic room power control layout 28F2100B 16K-B 96K-B 128K-B MX28F2100B 44-PIN X28F21

WINBOND APPLICATION NOTE

Abstract: WINBOND Serial flash cross reference same package type as Winbond, ST, SST, Atmel and MXIC. They are fully pin-to-pin compatible. The , , Atmel and MXIC's pins. Spansion provides SO-8 208 mil and WSON 8-pin packages for the 8-MB S25FL080A , 4M-8M SPI Cross Reference Spansion®, STM®, SST®, MXIC, Atmel® & Winbond® Application Note By , and are produced by a number of Flash manufactures including: Spansion, SST, ST, MXIC, Atmel and , manufactures and can be used to replace the following devices: ST M25P40/80, SST SST25VF040B/080B, MXIC
Spansion
Original
AT25F4096 M25P40 MX25L8005 W25P80 WINBOND APPLICATION NOTE WINBOND Serial flash cross reference mxic spi flash MXIC SPI Flash MXIC serial Flash MX25L400/800 S25FL040A S25FL008A M25P80

26C1024

Abstract: (Multiple-Time Programmable Read Only Memory) organized as 64K words of 16 bits each. MXIC's MTP ROMs offer the , bus contention, the MX26C1024A has separate chip enable (CE) and output enable (OE ) controls. MXIC's , levels during erase and program ming, while maintaining maximum EPROM compat ibility. MXIC MTP ROMTM tech n o lo g y re lia b ly stores memory contents after 100 erase and program cy cles. The MXIC cell is , package, 44 lead PLCC, 40 TSOP (I) package. 1 REV. 1.5, JUN 11, 1998 MXIC PIN CONFIGURATIONS
-
OCR Scan
26C1024 40-PIN X26C1024A
Abstract: : PM0403 1 MXIC 3.0 3.1 MX98742 SYSTEM DIAGRAM REPEATER WITH A BUILT-IN BRIDGE Figure 3-1 , MXIC 131 S IG D E T A /L K G D /C O L A MX98742 I, TTL TX Mode : Signal Detect Port A. This , . Mux'd with TX pin SIGDET A. 5 MXIC MX98742 Table 5-3. Port A Meddia Independent Interface , signals. If 7-Wire mode is selected, this is the 10MHz recov­ ered clock. 7 MXIC 70 S IG D E , /10 B. Mux'd with TX mode pin SIGDET B. 8 MXIC MX98742 Table 5-7. Buffer SRAM Interface -
OCR Scan
10BASE 160-P

PM-0254

Abstract: MXIc bits switchable. MXIC's Flash memories offer the most cost-effective and reliable read/write , ) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and , latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for , maintaining maximum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 10,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming
-
OCR Scan
MX28F4100 Q0-Q15 PM-0254 MX28F41OO PM0254 Q15/A-1 Q13ZZ

nrzi to nrz circuit diagram

Abstract: MXIC MX REV. 1.4, SEP. 15, 1997 MXIC 2.1.1 100 BASE-TX HUB APPLICATION MX98704 8 ports 100 , MXIC 3.0 PIN ASSIGMENT 3.1 PIN ASSIGNMENT-52 LEAD PLASTIC LEADED CHIP CARRIER RT LP RSCLK GND , z HI X I- o o >w 3 MXIC 4.0 PIN DESCRIPTIONS MX Physicial Data Transceiver (PDTR , MXIC PIN (PLCC) 25 26 27 28 29 30 31 32 33 MX98704 PIN NAME Test GND VDD GND VDD GND OP3 SYMCLK , 43 44 45 VDD GND VDD I I I 5 MXIC 5.0 FUNCTIONAL DESCRIPTION Functional block diagram
-
OCR Scan
nrzi to nrz circuit diagram MXIC MX nrzi to nrz converter circuit diagram 125-M 125-MH 25-MH PM0351 10/100-TX MX98704QC

28F002-T

Abstract: 28F002BX-T/B Yes Intel 28F002BL-T/B Yes MXIC 28F002T/B Yes* H/W Pin 12* WP# donâ'˜ t use (DU , MXIC: JP close Pin 12 JP WP# 1. Icc current during deep power-down mode is 0.20 uA typical , different pin configuration between Intel 28F002BX and MXIC 28F002 5 APPLICATION NOTE 2-2 Intel 28F002 V.S. MXIC 28F002BX (Boot Block Handling) RP# Intel 28F002BV 2.0 ~ 6.5V - standard read mode , locked MXIC 28F002 0 ~ 6V - boot block locked 11.4 ~ 12.6V - boot block unlock -0.3 ~ 0.8V - READ
Macronix International
Original
28F002-T 28F200-T 28F200-B 28F002-B 28F020 MX28F2100T

mxic

Abstract: MX29L811 MX29L811 includes 16 sectors of 64KB(65,536 Bytes or 32,768 words). MXIC's Flash memories offer the most , chip enable CE, output enable (OE), and write enable (WE) controls. MXIC's Flash memories augment , operation of the device. Reading data out of the device is similar to reading from an EPROM. MXIC Flash technology reliably stores memory contents even after 10,000 cycles. The MXIC's cell is designed to , highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up
Macronix International
Original
MXIC flash MX29L1611 8/512K 48-TSOP
Abstract: MXIC MX8325- 1 BLOCK DIAGRAM 14.318MHZ CPUCLK 1/2 CPUCLK 33/48MHZ 24MHZ BOUTOO , MXIC MX8325- 1 PIN DESCRIPTION (For MX8355-03) SYMBOL PIN TYPE PIN NUMBER DESCRIPTION , ), internal pull high (20mA) 3 MXIC MX8325- 1 FREQUENCY TABLE MS0=1, 33/48 SELECT=H MS0=1, 33 , =5V V 2.4 V for buffers only Ohms MXIC MX8325- 1 CAPACITANCE TA = 25°C, f = 1.0 , Frequency 14.318 14.318 5 14.318 MHz MXIC M X8325-1 WAVEFORMS ORDERING -
OCR Scan
28-PIN MX8325-1 80486DX 80486DX2 80486DX4 80486S

0423-J

Abstract: PM-0254 -mega bit Flash memory organ ized as 512K bytes of 8 bits or 256K words of 16 bits switchable. MXIC's Flash , MX28F4100 has separate chip enable (CE) and output enable (OE ) controls. MXIC's Flash memories augment , with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps , . MXIC Flash technology reliably stores memory con tents even after 10,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combina tion
-
OCR Scan
0423-J 4M-BITIS12K 015/A-1 A0-A17 Q0-Q14

mxic

Abstract: PM-0254 ized as 512K bytes of 8 bits or 256K words of 16 bits switchable. MXIC's Flash memories offer the most , (CE) and output enable (OE ) controls. MXIC's Flash memories augment EPROM functional ity with , /Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi , during erase and programming, while maintain ing maximum EPROM compatibility. MXIC Flash technology reliably stores memory con tents even after 10,000 erase and program cycles. The MXIC cell is designed to
-
OCR Scan
MX28F41QO MXS8F4100 X28F4100

MX28F1OOOC

Abstract: -mega bit Flash memory or ganized as 128K bytes of 8 bits each. MXIC's Flash memories offer the most , chip enable (CE) and output enable (OE ) controls. MXIC's Flash memories augment EPRO M functional ity , is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to , maximum EPRO M compatibility. MXIC Flash technology reliably stores memory con tents even after 10,000/1,000 erase and program cy cles. The MXIC cell is designed to optimize the erase and programming
-
OCR Scan
MX28F1OOOC MX28F1000C MX28F1000P PM0364 X28F1000C A0-A16

MX28F2000

Abstract: The MX28F2000 is a 2-mega bit Flash memory organ ized as 256K bytes of 8 bits each. MXIC's Flash , MX28F2000 hag separate chip enable (CE) and output enable (OE ) controls. MXIC's Flash memories augment EPRO , protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up , , while maintaining maxi mum EPRO M compatibility. MXIC Flash technology reliably stores memory con tents even after 10,000 erase and program cycles. The MXIC cell is designed to optimize the erase and
-
OCR Scan
SM-BITI28BK 16-KB 96-KB 128-KB PM0147

768KHZ

Abstract: MX93011 , JUL 5, 1996 MXIC MX93Û1 1 A 2.0 FUNCTION BLOCK DIAGRAM m < ^ n n x x ol £o x fg X ro ZD , state ZR high Impedance state with soft latch 6 MXIC MX93Û11A 3.2 PIN TYPE SUMMARY : INPUT : CMOS , \ is invalid the MX93011A will bring HOLDA\ to high and resume normal operation. 8 MXIC MX93à , , BZ BACC, RET, RETI, Interrupt, hardware reset program counter 12 MXIC MX93011A 5.1 TABLE OF 10 , pins, respectively. 14 MXIC MX93Û11A 6.4 SVR : Shift Variable Register (mapped to 10 register 03
-
OCR Scan
MX93011 768KHZ X321 mxic dsp instruction set MX9301 MX93Q11A 100-PIN

16Mb

Abstract: Flash Word program Chip/Sector (8K,4K,4K,16K,32K*15) words erase 100% drop in replace MXIC , MXIC MX29LV160 2.7~3.6V Byte/Word program Chip/Sector (8K,4K,4K,16K,32K*31) words erase , erase Chip erase SST SST25LF040A 4Mb SPI Spansion MXIC S25FL004A MX25L8005 , Spansion 8Mb SPI MXIC Winbond ST MX25L8005 W25P32 M25PE80 100% Drop in replace 100 , bytes) program 64k bytes Sector erase Chip erase 50MHz Spansion 16Mb SPI MXIC
-
Original
F49L800A MX29LV800 F49L160A SST39VF160 SST25VF016 MX25L1605 16Mb Flash SPANSION s29al016 W25X040 s29al016 s29al008 SST39LF080/80 SST39VF080/08 S29AL008 M29W800

48-pin TSOP I flash memory

Abstract: ized as 256K bytes of 8 bits or 128K words of 16 bits switchable. MXIC's Flash memories offer the most , chip enable (CE) and output enable (OE ) controls. MXIC's Flash memories augment EPRO M functional ity , auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's , supply levels during erase and programming, while maintain ing maximum EPRO M compatibility. MXIC Flash technology reliably stores memory con tents even after 10,000 erase and program cycles. The MXIC cell is
-
OCR Scan
48-pin TSOP I flash memory IN/IX28F2100 MX28F2100 015/A

MX28F1000

Abstract: macronix flash 12.0v -mega bit Flash memory organ ized as 128K bytes of 8 bits each. MXIC's Flash memories offer the most , chip enable (CE) and output enable (OE ) controls. MXIC's Flash memories augment EPROM functional ity , degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is , maintaining m axi mum EPROM compatibility. MXIC Flash technology reliably stores memory con tents even after 10,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming
-
OCR Scan
MX28F1000 macronix flash 12.0v MX28F1

mx29lv160

Abstract: SA30 . 1. The Difference Architectures : The difference between MXIC's MX29LV160T/B - boot sectored device , . Thus, 512 sectors or 32 blocks compose the whole flash. For MXIC's devices, the bottom or top 32Kwords , address format is A14A0 (5555H and 2AAAH), it's not necessary to modify when migrating to MXIC's because , to Vcc through a resistor to complete the reset when power on stage. The Ready/Busy# pin on MXIC , completion of program or erase cycles. It's a signal output pin with open drain on MXIC device, ignore it
Macronix International
Original
SA30 SA33 MX29LV SST39LF/VF160 SST39LF160/VF160 SST39LV160/VF160 SST39LF/VF

B0000H-BFFFFH

Abstract: memory organized as 1M bytes of 8 bits or 512K words of 16 bits. MXIC's Flash memories offer the most , ) and output enable (OE) controls. MXIC's Flash memories augment EPROM functionality with in-circuit , degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is , programming, while maintaining maximum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and
Macronix International
Original
B0000H-BFFFFH MX29F800T/B 32K-B 64K-B
Abstract: /N: PM0334 are trademarks of Rambus Inc. REV. 1.4, APR. 15, 1996 MXIC MX8335 FUNCTIONAL , =0.01uF, C2=0.1 uF, and C3=47uF. 2 MXIC MX8335 â  FIG 1 INTFRFACF CIRCUITRY 1 9 3 o , CLKOUT 2.4 30 CONDITIONS V 35 15 3 MXIC MX8335 AC CHARACTERISTICS TA* = 0Â , PART NO. PACKAGE MX8335MC 8-PIN SOP WAVE FROMS 4 Eaual loadina MXIC MX8335 -
OCR Scan
200MH 267MH 200-267M
Showing first 20 results.