Top Results
| Part | Manufacturer | Description | Datasheet | BUY |
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| POWEREST | Texas Instruments | Power Estimation Tool (PET) |  |
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| LM3S2793-IBA80-C5T | Texas Instruments | MICROCONTROLLER | |
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| TMS320F28064UPZT | Texas Instruments | MICROCONTROLLER | |
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| TMS320F28068UPZPS | Texas Instruments | MICROCONTROLLER | |
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| TMS320F28067UPNT | Texas Instruments | MICROCONTROLLER | |
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| TMS320F28067UPZT | Texas Instruments | MICROCONTROLLER | |
microcontroller based automatic power factor cont
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CMOS 4000 Series family databookAbstract: MC1 4000 SERIES MOTOROLA DATABOOK 4-1 PSD4XX Family Key Features (Cont.) t Low power operation is achieved by using a Power , the clock to the ZPLD. Also available is an automatic power down mode using the ALE signal. A Sleep , into standby mode. t Power management unit with automatic standby and sleep modes. t Security mode , microcontroller SRAM and also to store backup information that is necessary after a system power down. Backup , input (CSI) to the peripheral device, the PMU includes an Automatic Power Down unit (APD) that will |
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intel 80c196 microcontrollerAbstract: psd4xx 7-1 PSD4XX Family Key Features (Cont.) t Low power operation is achieved by using a Power , the clock to the ZPLD. Also available is an automatic power down mode using the ALE signal. A Sleep , into standby mode. t Power management unit with automatic standby and sleep modes. t Security mode , microcontroller SRAM and also to store backup information that is necessary after a system power down. Backup , input (CSI) to the peripheral device, the PMU includes an Automatic Power Down unit (APD) that will |
WaferScale Integration Original |
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WSI MagicPro II ProgrammerAbstract: clock to the ZPLD. Also available is an automatic power down mode using the ALE signal. A Sleep mode is , can automatically switch into standby mode. Power management unit with automatic standby and sleep , Select input (CSI) to the peripheral device, the PMU includes an Automatic Power Down unit (APD) that , . I/O pin 2. ZPLD I/O pin* 3. Latched Address Out - A6 Multiple functions 1. Automatic Power Down , Programmable Peripheral PSD4XX Family Field-Programmable Microcontroller Peripherals Key |
- OCR Scan |
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ac-dc converter full wave type schematic diagramAbstract: Vicor 37052-601 Applications · Telecom (WiMAX, Power Amplifiers, Optical Switches) · Automatic Test Equipment (ATE) · LED , , operating from a rectified universal AC input to generate an isolated 48 Vdc output bus with power factor , rate Input current (peak) Source line frequency range Power factor Input inductance, maximum Input , , unless otherwise noted. See associated figures for general trend data. Power Factor vs. Load and VIN , 0.90 0.88 0.86 0.84 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 Efficiency (%) Power Factor |
Vicor Original |
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PSD4xxAbstract: 413A2 non-multiplexed) microcontrollers that is easy to use. The part's integration, small form factor, low power , , the Automatic Power-Down (APD) unit of the PMU can be setup to enable the PSD to enter Power Down , the clock input to the ZPLDs · ZPLDs to enter a special low power mode (Sleep Mode), based on Turbo , . Latched Address Out A6 Multiple functions 1. Automatic Power Down Clock Input 2. I/O pin 3. ZPLD I/O , PSD4XX Architecture (cont.) 9.1.1.5 The ZPLD Power Management The ZPLD implements a Zero Power Mode |
WaferScale Integration Original |
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PF175B480C033FP-00Abstract: ac-dc converter full wave type schematic diagram Applications · Telecom (WiMAX, Power Amplifiers, Optical Switches) · Automatic Test Equipment (ATE) · LED , , operating from a rectified universal AC input to generate an isolated 48 Vdc output bus with power factor , rate Input current (peak) Source line frequency range Power factor Input inductance, maximum Input , , unless otherwise noted. See associated figures for general trend data. Power Factor vs. Load and VIN , 0.90 0.88 0.86 0.84 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 Efficiency (%) Power Factor |
Vicor Original |
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PSD411A2-C-70JAbstract: psd4xx non-multiplexed) microcontrollers that is easy to use. The part's integration, small form factor, low power , , the Automatic Power-Down (APD) unit of the PMU can be setup to enable the PSD to enter Power Down , the clock input to the ZPLDs · ZPLDs to enter a special low power mode (Sleep Mode), based on Turbo , . Latched Address Out A6 Multiple functions 1. Automatic Power Down Clock Input 2. I/O pin 3. ZPLD I/O , PSD4XX Architecture (cont.) 9.1.1.5 The ZPLD Power Management The ZPLD implements a Zero Power Mode |
WaferScale Integration Original |
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l64724-75Abstract: l64002 Channel Data Output Interface 2.7 Analog-to-Digital Converter (ADC) Interface 2.8 Microcontroller , 3.7 Group 5: Self-Tuning Microcontroller Registers 3.8 Group 6: Reserved (Internal Use Only) 3.9 , Recovery 5.7 Carrier Recovery Loop 5.8 Automatic Gain Control (AGC) 5.9 Output Control 5.10 External , On-chip Microcontroller E.1 L64724 Microcontroller Instruction Set E.2 Microcontroller Address Map E , -Pin PQFP/MQFP Pinout 100-Pin PQFP/MQFP Mechanical Drawing 100-Pin PQFP/MQFP Mechanical Drawing (Cont |
LSI Logic Original |
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l64724-75 l64002 L64005 str 6554 str w 6554 a L64007 L64724TM I14030 DB14-000032-03 D-33181 D-85540 |
PSD4xxAbstract: difference between 68hc12 and 80c196 non-multiplexed) microcontrollers that is easy to use. The part's integration, small form factor, low power , the PSD4XX enables the user to control the power consumption on selected functional blocks, based on , Automatic Power-Down (APD) unit of the PMU can be setup to enable the PSD to enter Power Down Mode or , the clock input to the ZPLDs · ZPLDs to enter a special low power mode (Sleep Mode), based on Turbo , functions 1. Automatic Power Down Clock Input 2. I/O pin 3. ZPLD I/O pin* 4. Latched Address Out A7 |
STMicroelectronics Original |
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CLDCC68 TQFP68 PSD4xx difference between 68hc12 and 80c196 plcc 68 PLCC 68 intel ZPSD411A2-C-70J PLDCC68 |
TQFP68Abstract: psd4xx non-multiplexed) microcontrollers that is easy to use. The part's integration, small form factor, low power , the PSD4XX enables the user to control the power consumption on selected functional blocks, based on , Automatic Power-Down (APD) unit of the PMU can be setup to enable the PSD to enter Power Down Mode or , the clock input to the ZPLDs · ZPLDs to enter a special low power mode (Sleep Mode), based on Turbo , Out A6 Multiple functions 1. Automatic Power Down Clock Input 2. I/O pin 3. ZPLD I/O pin* 4 |
STMicroelectronics Original |
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PSD411A2-C-70J psd403a2-c-90 |
| Abstract: .) Low power operation is achieved by using a Power Management Unit (PMU) that enables automatic , automatic power down mode using the ALE signal. A Sleep mode is available that consumes only 10 pA standby , SRAM that can automatically switch into standby mode. â¡ Power management unit with automatic , microcontroller SRAM and also to store backup information that is necessary after a system power down. Backup , input (CSI) to the peripheral device, the PMU includes an Automatic Power Down unit (APD) that will |
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68HC11 68HC16 683XX |
CMOS 4000 Series family databookAbstract: cmos 4000 series databook ZPSD4XXV versions is achieved by using a Power Management Unit (PMU) that enables automatic stand-by modes , automatic power down mode using the ALE signal. A Sleep mode is also available that consumes only 1 µA , switch into standby mode. Power management unit with automatic standby and sleep modes. Security mode , generate a Chip Select input (CSI) to the peripheral device, the PMU includes an Automatic Power Down unit , . Automatic Power Down Clock Input 2. I/O pin 3. ZPLD I/O pin* 4. Latched Address Out A7 I SRAM |
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CMOS 4000 Series family databook cmos 4000 series databook MC1 4000 SERIES MOTOROLA DATABOOK signal conditioning circuit for pt100 intel 80c196 microcontroller PIN DIAGRAM OF 80186 |
intel 80196 microcontrollerAbstract: 80196 internal architecture diagram functions required for a microcontroller based system. The supervisory features include: System power , the peripheral functions inherent in microcontroller based applications including: EPROM, SRAM , automatically switching to standby power. t A page register expands the microcontroller address space by a , automatically detect a lack of microcontroller activity and put the PSD into power down mode. t The devices , Flip-Flops (cont.) Selects mode between MCU I/O or Address Out PMMR0 B1 Power Management |
WaferScale Integration Original |
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intel 80196 microcontroller 80196 internal architecture diagram 80C251 8031 8-Bit Microcontroller 8031 MICROCONTROLLER architecture PSD701 |
csioAbstract: psd5xx by using a Power Management Unit (PMU) that enables automatic stand-by modes in the EPROM, SRAM, and ZPLDs. It also disables the clock to the ZPLD. Also available is an automatic power down mode , power component when the chip is changing states. The result is a programmable microcontroller , into standby mode. Power management unit with automatic standby and sleep modes. Security mode , generate a Chip Select input (CSI) to the peripheral device, the PMU includes an Automatic Power Down unit |
WaferScale Integration Original |
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csio psd5xx PT100 CL PSD413A2 8/16-B |
i80c196Abstract: .) Low power operation is achieved by using a Power Management Unit (PMU) that enables automatic stand-by , automatic power down mode using the ALE signal. A Sleep mode is available that consumes only 10 pA standby , of standby SRAM that can automatically switch into standby mode. Power management unit with automatic , PSD4XX enables the user to control the power consumption on selected functional blocks based on system , PMU includes an Automatic Power Down unit (APD) that will turn off the PSD4XX (into standby or sleep |
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i80c196 60PD0 59PD1 58PD2 56PD4 53PD7 48PB0 |
intel 80251Abstract: MOTOROLA Neuron Chip selected functional blocks based on system requirements. The PMU includes an Automatic Power Down unit , the peripheral functions inherent in microcontroller based applications including: EPROM, SRAM , provides all the supervisory functions required for a microcontroller based system. The supervisory , is lost by automatically switching to standby power. t A page register expands the microcontroller , The device can automatically detect a lack of microcontroller activity and put the PSD into power |
WaferScale Integration Original |
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intel 80251 MOTOROLA Neuron Chip 68HC12 80386EX 8051XA PSD701S5 PSD7XXS5-70 PSD7XXS5-90 PSD7XXS5-15 |
CMOS 4000 Series family databookAbstract: 80196 internal architecture diagram Power Management Unit (PMU) that enables automatic stand-by modes in the EPROM, SRAM, and ZPLDs. It also disables the clock to the ZPLD. Also available is an automatic power down mode using the ALE , power component when the chip is changing states. The result is a programmable microcontroller , into standby mode. Power management unit with automatic standby and sleep modes. Security mode , microcontroller SRAM and also to store backup information that is necessary after a system power down. Backup |
WaferScale Integration Original |
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motorola cmos databook ZPSD412A0 |
| Abstract: page register that can be used to expand the microcontroller address space by a factor of 256 , . The PMU can automatically detect a lack of microcontroller activity and put the PSD913F1 into Power , the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power Down unit (APD) that will turn off device functions due to microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce power consumption. The PSD913F1 |
WaferScale Integration Original |
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800-TEAM-WSI |
80196 instruction setAbstract: 80C31 instruction set microcontroller address space by a factor of 256. t Internal programmable Power Management Unit (PMU) that , based on system requirements. The PMU includes an Automatic Power Down unit (APD) that will turn off device functions due to microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce , microcontroller activity and put the PSD913F1 into Power Down Mode. t Erase/Write cycles: · Flash memory , power. Power pins GND 1,16,26 (cont.) Ground pins *The pin numbers in this table are |
STMicroelectronics Original |
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PQFP52 PLCC52 80196 instruction set 80C31 instruction set J1850 PSD913F1-V PSD913F1-A |
| Abstract: functional blocks based on system requirements. The PMU includes an Automatic Power Down unit (APD) that will turn off device functions due to microcontroller inactivity. The APD unit has a Power Down Mode , . 70 9.5.1 Automatic Power Down (APD) Unit and Power Down M o d e , factor of 256. â¡ Internal programmable Power Management Unit (PMU) that supports a low power mode called Power Down Mode. The PMU can automatically detect a lack of microcontroller activity and |
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PSD833F2/ZPSD833F2 PSD834F2/ZPSD834F2 PSD813F 3F2-15JI PSD833F2-15M PSD833F2-15MI |
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