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microcontroller based automatic power factor cont

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: 4-1 PSD4XX Family Key Features (Cont.) t Low power operation is achieved by using a Power , the clock to the ZPLD. Also available is an automatic power down mode using the ALE signal. A Sleep , into standby mode. t Power management unit with automatic standby and sleep modes. t Security mode , microcontroller SRAM and also to store backup information that is necessary after a system power down. Backup , input (CSI) to the peripheral device, the PMU includes an Automatic Power Down unit (APD) that will -
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68HC11 68HC16 683XX CMOS 4000 Series family databook MC1 4000 SERIES MOTOROLA DATABOOK 4000 SERIES MOTOROLA DATABOOK motorola power transistor to-126 intel 80c196 microcontroller 80196 internal architecture diagram
Abstract: 7-1 PSD4XX Family Key Features (Cont.) t Low power operation is achieved by using a Power , the clock to the ZPLD. Also available is an automatic power down mode using the ALE signal. A Sleep , into standby mode. t Power management unit with automatic standby and sleep modes. t Security mode , microcontroller SRAM and also to store backup information that is necessary after a system power down. Backup , input (CSI) to the peripheral device, the PMU includes an Automatic Power Down unit (APD) that will WaferScale Integration
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psd4xx PSD413A2
Abstract: clock to the ZPLD. Also available is an automatic power down mode using the ALE signal. A Sleep mode is , can automatically switch into standby mode. Power management unit with automatic standby and sleep , Select input (CSI) to the peripheral device, the PMU includes an Automatic Power Down unit (APD) that , . I/O pin 2. ZPLD I/O pin* 3. Latched Address Out - A6 Multiple functions 1. Automatic Power Down , Programmable Peripheral PSD4XX Family Field-Programmable Microcontroller Peripherals Key -
OCR Scan
WSI MagicPro II Programmer
Abstract: Applications · Telecom (WiMAX, Power Amplifiers, Optical Switches) · Automatic Test Equipment (ATE) · LED , , operating from a rectified universal AC input to generate an isolated 48 Vdc output bus with power factor , rate Input current (peak) Source line frequency range Power factor Input inductance, maximum Input , , unless otherwise noted. See associated figures for general trend data. Power Factor vs. Load and VIN , 0.90 0.88 0.86 0.84 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 Efficiency (%) Power Factor Vicor
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Vicor 37052-601 PF175B480C033FP-00 EN61000-3-2
Abstract: non-multiplexed) microcontrollers that is easy to use. The part's integration, small form factor, low power , , the Automatic Power-Down (APD) unit of the PMU can be setup to enable the PSD to enter Power Down , the clock input to the ZPLDs · ZPLDs to enter a special low power mode (Sleep Mode), based on Turbo , . Latched Address Out ­ A6 Multiple functions 1. Automatic Power Down Clock Input 2. I/O pin 3. ZPLD I/O , PSD4XX Architecture (cont.) 9.1.1.5 The ZPLD Power Management The ZPLD implements a Zero Power Mode WaferScale Integration
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413A2 psd403a2-c-90 80C196 PSD401A1C90 PSD402A2-C-70J 800-TEAM-WSI
Abstract: Applications · Telecom (WiMAX, Power Amplifiers, Optical Switches) · Automatic Test Equipment (ATE) · LED , , operating from a rectified universal AC input to generate an isolated 48 Vdc output bus with power factor , rate Input current (peak) Source line frequency range Power factor Input inductance, maximum Input , , unless otherwise noted. See associated figures for general trend data. Power Factor vs. Load and VIN , 0.90 0.88 0.86 0.84 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 Efficiency (%) Power Factor Vicor
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PFM converter
Abstract: non-multiplexed) microcontrollers that is easy to use. The part's integration, small form factor, low power , , the Automatic Power-Down (APD) unit of the PMU can be setup to enable the PSD to enter Power Down , the clock input to the ZPLDs · ZPLDs to enter a special low power mode (Sleep Mode), based on Turbo , . Latched Address Out ­ A6 Multiple functions 1. Automatic Power Down Clock Input 2. I/O pin 3. ZPLD I/O , PSD4XX Architecture (cont.) 9.1.1.5 The ZPLD Power Management The ZPLD implements a Zero Power Mode WaferScale Integration
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PSD411A2-C-70J PSD411A2-C-70L plcc 68 PSD411A2-C-90JI PSD413A2-C-70L PSD413A1-C-15J
Abstract: Channel Data Output Interface 2.7 Analog-to-Digital Converter (ADC) Interface 2.8 Microcontroller , 3.7 Group 5: Self-Tuning Microcontroller Registers 3.8 Group 6: Reserved (Internal Use Only) 3.9 , Recovery 5.7 Carrier Recovery Loop 5.8 Automatic Gain Control (AGC) 5.9 Output Control 5.10 External , On-chip Microcontroller E.1 L64724 Microcontroller Instruction Set E.2 Microcontroller Address Map E , -Pin PQFP/MQFP Pinout 100-Pin PQFP/MQFP Mechanical Drawing 100-Pin PQFP/MQFP Mechanical Drawing (Cont LSI Logic
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l64724-75 l64002 L64005 str 6554 str w 6554 a L64007 L64724TM I14030 DB14-000032-03 D-33181 D-85540
Abstract: non-multiplexed) microcontrollers that is easy to use. The part's integration, small form factor, low power , the PSD4XX enables the user to control the power consumption on selected functional blocks, based on , Automatic Power-Down (APD) unit of the PMU can be setup to enable the PSD to enter Power Down Mode or , the clock input to the ZPLDs · ZPLDs to enter a special low power mode (Sleep Mode), based on Turbo , functions 1. Automatic Power Down Clock Input 2. I/O pin 3. ZPLD I/O pin* 4. Latched Address Out ­ A7 STMicroelectronics
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CLDCC68 TQFP68 ZPSD411A2-C-70J PLCC 68 intel difference between 68hc12 and 80c196 PSD403A1-C-90UI ST psd413a1-c-90ji PLDCC68
Abstract: non-multiplexed) microcontrollers that is easy to use. The part's integration, small form factor, low power , the PSD4XX enables the user to control the power consumption on selected functional blocks, based on , Automatic Power-Down (APD) unit of the PMU can be setup to enable the PSD to enter Power Down Mode or , the clock input to the ZPLDs · ZPLDs to enter a special low power mode (Sleep Mode), based on Turbo , Out ­ A6 Multiple functions 1. Automatic Power Down Clock Input 2. I/O pin 3. ZPLD I/O pin* 4 STMicroelectronics
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Abstract: .) Low power operation is achieved by using a Power Management Unit (PMU) that enables automatic , automatic power down mode using the ALE signal. A Sleep mode is available that consumes only 10 pA standby , SRAM that can automatically switch into standby mode. â¡ Power management unit with automatic , microcontroller SRAM and also to store backup information that is necessary after a system power down. Backup , input (CSI) to the peripheral device, the PMU includes an Automatic Power Down unit (APD) that will -
OCR Scan
Abstract: ZPSD4XXV versions is achieved by using a Power Management Unit (PMU) that enables automatic stand-by modes , automatic power down mode using the ALE signal. A Sleep mode is also available that consumes only 1 uA , switch into standby mode. Power management unit with automatic standby and sleep modes. Security mode , generate a Chip Select input (CSI) to the peripheral device, the PMU includes an Automatic Power Down unit , . Automatic Power Down Clock Input 2. I/O pin 3. ZPLD I/O pin* 4. Latched Address Out ­ A7 I SRAM -
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cmos 4000 series databook signal conditioning circuit for pt100 psd5xx PIN DIAGRAM OF 80186 8k x 8 sram design using flip flops 5 to 32 decoder using 4 t0 16 decoders
Abstract: functions required for a microcontroller based system. The supervisory features include: ­ System power , the peripheral functions inherent in microcontroller based applications including: EPROM, SRAM , automatically switching to standby power. t A page register expands the microcontroller address space by a , automatically detect a lack of microcontroller activity and put the PSD into power down mode. t The devices , Flip-Flops (cont.) Selects mode between MCU I/O or Address Out PMMR0 B1 Power Management WaferScale Integration
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intel 80196 microcontroller 80C251 PSD701 AD0-AD15 8051XA 80386EX
Abstract: by using a Power Management Unit (PMU) that enables automatic stand-by modes in the EPROM, SRAM, and ZPLDs. It also disables the clock to the ZPLD. Also available is an automatic power down mode , power component when the chip is changing states. The result is a programmable microcontroller , into standby mode. Power management unit with automatic standby and sleep modes. Security mode , generate a Chip Select input (CSI) to the peripheral device, the PMU includes an Automatic Power Down unit WaferScale Integration
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csio PT100 CL 8/16-B
Abstract: .) Low power operation is achieved by using a Power Management Unit (PMU) that enables automatic stand-by , automatic power down mode using the ALE signal. A Sleep mode is available that consumes only 10 pA standby , of standby SRAM that can automatically switch into standby mode. Power management unit with automatic , PSD4XX enables the user to control the power consumption on selected functional blocks based on system , PMU includes an Automatic Power Down unit (APD) that will turn off the PSD4XX (into standby or sleep -
OCR Scan
i80c196 60PD0 59PD1 58PD2 56PD4 53PD7 48PB0
Abstract: selected functional blocks based on system requirements. The PMU includes an Automatic Power Down unit , the peripheral functions inherent in microcontroller based applications including: EPROM, SRAM , provides all the supervisory functions required for a microcontroller based system. The supervisory , is lost by automatically switching to standby power. t A page register expands the microcontroller , The device can automatically detect a lack of microcontroller activity and put the PSD into power WaferScale Integration
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intel 80251 MOTOROLA Neuron Chip 68HC12 PSD701S5 PSD7XXS5-70 PSD7XXS5-90 PSD7XXS5-15
Abstract: Power Management Unit (PMU) that enables automatic stand-by modes in the EPROM, SRAM, and ZPLDs. It also disables the clock to the ZPLD. Also available is an automatic power down mode using the ALE , power component when the chip is changing states. The result is a programmable microcontroller , into standby mode. Power management unit with automatic standby and sleep modes. Security mode , microcontroller SRAM and also to store backup information that is necessary after a system power down. Backup WaferScale Integration
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motorola cmos databook ZPSD412A0
Abstract: page register that can be used to expand the microcontroller address space by a factor of 256 , . The PMU can automatically detect a lack of microcontroller activity and put the PSD913F1 into Power , the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power Down unit (APD) that will turn off device functions due to microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce power consumption. The PSD913F1 WaferScale Integration
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Abstract: microcontroller address space by a factor of 256. t Internal programmable Power Management Unit (PMU) that , based on system requirements. The PMU includes an Automatic Power Down unit (APD) that will turn off device functions due to microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce , microcontroller activity and put the PSD913F1 into Power Down Mode. t Erase/Write cycles: · Flash memory ­ , power. Power pins GND 1,16,26 (cont.) Ground pins *The pin numbers in this table are STMicroelectronics
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PQFP52 PLCC52 80196 instruction set 80C31 instruction set J1850 PSD913F1-V PSD913F1-A
Abstract: functional blocks based on system requirements. The PMU includes an Automatic Power Down unit (APD) that will turn off device functions due to microcontroller inactivity. The APD unit has a Power Down Mode , . 70 9.5.1 Automatic Power Down (APD) Unit and Power Down M o d e , factor of 256. â¡ Internal programmable Power Management Unit (PMU) that supports a low power mode called Power Down Mode. The PMU can automatically detect a lack of microcontroller activity and -
OCR Scan
PSD833F2/ZPSD833F2 PSD834F2/ZPSD834F2 PSD813F 3F2-15JI PSD833F2-15M PSD833F2-15MI
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