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EL5102IS-T7 Intersil Corporation 1 CHANNEL, VIDEO AMPLIFIER, PDSO8, 0.150 INCH, SOIC-8 visit Intersil
HSP45102SC-40 Intersil Corporation 1-BIT, DSP-NUM CONTROLLED OSCILLATOR, PDSO28 visit Intersil
EL5102ISZ-T7 Intersil Corporation 1 CHANNEL, VIDEO AMPLIFIER, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOIC-8 visit Intersil
HA7-5102-2 Intersil Corporation DUAL OP-AMP, 2500uV OFFSET-MAX, 60MHz BAND WIDTH, CDIP8 visit Intersil
HSP45102SI-3396 Intersil Corporation 12-Bit NCO 28 SOIC, 40MHz, COMM; SOIC28; Temp Range: See Datasheet visit Intersil Buy
ISL15102IRZ Intersil Corporation Single Port, PLC Differential Line Driver; QFN24; Temp Range: -40° to 85°C visit Intersil

mcr 5102

Catalog Datasheet MFG & Type PDF Document Tags

mcr 5102

Abstract: JIS-C-5143 MCR Humidity Load Life Test In accordance with JIS-C-5102 test conditions, the following , MCR Series Tantalum Chip Surface Mount Low Impedance 125C Maximum Temperature Actual Size The MCR series are new low impedance tantalum chip capacitors available from UCC/NCC. These capacitors have a standard 20% tolerance and are available in the D case size. The MCR series capacitors are , additional technical information and specifications. TANTALUM CHIP MCR Summary of Specifications
United Chemi-Con
Original

mcr 5102

Abstract: JIS-C-5143 MCR Humidity Load Life Test In accordance with JIS-C-5102 test conditions, the following , MCR Series Tantalum Chip Surface Mount Low Impedance 125C Maximum Temperature Actual Size The MCR series are new low impedance tantalum chip capacitors available from UCC/NCC. These capacitors have a standard 20% tolerance and are available in the D case size. The MCR series capacitors are , additional technical information and specifications. TANTALUM CHIP MCR Summary of Specifications
United Chemi-Con
Original
Abstract: MCR Series ⢠Tantalum Chip ⢠Surface Mount ⢠Low Impedance ⢠â'«Ø‡521Ø'â'¬C Maximum Temperature Actual Size The MCR series are new low impedance tantalum chip capacitors available from UCC/NCC. These capacitors have a standard Ø"20% tolerance and are available in the D case size. The MCR , www.chemi-con.com 107 MCR TANTALUM CHIP Summary of Specifications MCR Series MCR Specifications , ¦ ( DF ) Low and High Temperature Characteristics In accordance with JIS-C-5102 test conditions United Chemi-Con
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MCR 5102 converter

Abstract: mcr 5102 =100K150MF Leakage current (MA) max. ­ 55 P10 8(10) 10 12 +85 P10 +125 P15 Test Conditions Refer JIS C 5102. 7. 7. After 5 minutes of applying rated voltage at 20C Refer JIS C 5102. 7. 9. f=120Hz 20C ( ) : Applies for R.V. 4Vdc Shall meet the table values. Refer JIS C 5102. 7.12 . ( ) : Applies for R.V. 4Vdc , of table 2. Refer JIS C 5102. 9.10 page. 85C, Rated voltage, 1,000hrs. f=100kHz 20C f , CAPACITORS ?PART NUMBERING SYSTEM 10 MCR 107 M D TER Taping code : TER is standard Case code : P Rated
Nippon Chemi-Con
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MCR 5102 converter mcr 5102 01CVMA 7K10MF 15K68MF 125CV 10K35V E1002B

MCR 5102 converter

Abstract: mcr 5102 . Shall not exceed the values of table 2. Test Conditions Refer JIS C 5102. 7. 7. After 5 minutes of applying rated voltage at 20C Refer JIS C 5102. 7. 9. f=120Hz 20C ( ) : Applies for R.V. 4Vdc Shall meet the table values. Refer JIS C 5102. 7.12 . ( ) : Applies for R.V. 4Vdc Endurance Refer JIS C 5102. 9.10 page. 85C, Rated voltage, 1,000hrs. Equivalent series resistance (ESR) Rated ripple , ) CAT. No. E1002C CHIP TYPE TANTALUM SOLID ELECTROLYTIC CAPACITORS ?PART NUMBERING SYSTEM 10 MCR
Nippon Chemi-Con
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150MF

MCR 5102 converter

Abstract: mcr 5102 values of table 2. Test Conditions Refer JIS C 5102. 7. 7. After 5 minutes of applying rated voltage at 20C Refer JIS C 5102. 7. 9. f=120Hz 20C ( ) : Applies for R.V. 4Vdc Shall meet the table values. Refer JIS C 5102. 7.12 . ( ) : Applies for R.V. 4Vdc Endurance Refer JIS C 5102. 9.10 page. 85C , CHIP TYPE TANTALUM SOLID ELECTROLYTIC CAPACITORS ?PART NUMBERING SYSTEM 10 MCR 107 M D TER Taping
Nippon Chemi-Con
Original
E1002D

mcr 5102

Abstract: 5102. 7. 7. After 5 minutes of applying rated voltage at 20C Refer JIS C 5102. 7. 9. f=120Hz 20C ( ) : Applies for R.V. 4Vdc Shall meet the table values. Refer JIS C 5102. 7.12 . ( ) : Applies for R.V. 4Vdc Refer JIS C 5102. 9.10 page. 85C, Rated voltage, 1,000hrs. f=100kHz 20C f=100kHz 20C ?DIMENSIONS , TANTALUM SOLID ELECTROLYTIC CAPACITORS ?PART NUMBERING SYSTEM 10 MCR 107 M D TER Taping
Nippon Chemi-Con
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E1002E
Abstract: C 5102. Capacitance change tan Leakage current Within ±10% of initial value Initial specified , 6 7 8 9 10 11 12 13 14 UU T 1 C 1 0 0 MCR 1 GS A ± 0.2 A ± 0.2 D D ±0.5 B ± 0.2 X2P 10 Nichicon
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Z--25 Z--40 ZT/Z20 8100N

mcr 5102

Abstract: 5102. Capacitance change tan Leakage current Within ± 10% of initial value Initial specified , 13 14 U Z R 1 C 1 0 0 MCR 1 GB Taping code D A B C E 4 1.8 4.3 4.3 1.0 5 2.1 5.3 5.3 1.3 (mm
Nichicon
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mcr 5102

Abstract: characteristics requirements listed at right. Black print on the case top. JIS C 5141 and JIS C 5102. Capacitance , 1 0 0 MCR 1 GB Taping code D A B C E 4 1.8 4.3 4.3 1.0 5 2.1 5.3 5.3 1.3 (mm) 6.3 2.4 6.6 6.6 2.2
Nichicon
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mcr 5152

Abstract: PLL 5121 5-102 6.1.3.3 PCON-Control Register (ECP Mode , .5-132 7.1.8 MCR(A,B)- MODEM CONTROL REGISTER
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OCR Scan
mcr 5152 PLL 5121 FLOPPY pinout 24 82091AA

mcr 5102

Abstract: UM82C450 set that the controller is ready to send data. This signal is set low by writing logic 1 to MCR (1 , signal is set low by writing logic 1 to MCR (0) and reset to high by Reset. w . â a rev â  â'"â'¢ Â , MCR (3) of each associated channel is programmed low (logic 0). 59 INT2 0 Line Printer Interrupt , 1 0 0 MCR Modem Control Register X 1 0 1 LSR Line Status Register X 1 1 0 MSR Modem Status , . LSR (7): This bit is always 0. The Modem Control Register (MCR) controls the Interface with the modem
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OCR Scan
UM82C451 UM82C450 UM82C452 ib7a pin shourd UM82C4 SLTN

mcr 5102

Abstract: TDA 4844 , B or C functions as IRQx to the PC bus. IRQx is enabled by setting MCR bit-3 to logic 1 and the , bit-6, MCR bits-1 & 2, FCTR bits 0-3 and IER bit-6. 2) RS485 half-duplex direction control, see FCTR bit-5, MCR bit-2 and MSR bits 4-7. RTS# output must be asserted before auto RTS flow control can , deasserted and will resume when this pin is asserted again. See EFR bit-7, MCR bit-2 and IER bit-7. DTR , logic 1. The software infrared enable bit (MCR bit6) will have full enable/disable control after the
Exar
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XR16L651 16C450 16C550 ST16C580 ST16C650A TDA 4844 16L651 32-BYTE XR16L6511

FIFO memory

Abstract: . IRQx is enabled by setting MCR bit-3 to logic 1 and the desired interrupt(s) in the interrupt enable , functions: 1) automatic hardware flow control, see EFR bit-6, MCR bits-1 & 2, FCTR bits 0-3 and IER bit-6. 2) RS485 half-duplex direction control, see FCTR bit-5, MCR bit-2 and MSR bits 4-7. RTS# output must be , again. See EFR bit-7, MCR bit-2 and IER bit-7. Data Terminal Ready or general purpose output (active low , 0 instead of normal logic 1. The software infrared enable bit (MCR bit6) will have full enable
Exar
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FIFO memory ST16C450/550/580/650A

mcr 5102

Abstract: , B or C functions as IRQx to the PC bus. IRQx is enabled by setting MCR bit-3 to logic 1 and the , control, see EFR bit-6, MCR bits-1 & 2, FCTR bits 0-3 and IER bit-6. 2) RS485 half-duplex direction control, see FCTR bit-5, MCR bit-2 and MSR bits 4-7. RTS# output must be asserted before auto RTS flow , when this pin is deasserted and will resume when this pin is asserted again. See EFR bit-7, MCR bit , infrared enable bit (MCR bit6) will have full enable/disable control after the power up. Reset Input. When
Exar
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Abstract: , B or C functions as IRQx to the PC bus. IRQx is enabled by setting MCR bit-3 to logic 1 and the , control, see EFR bit-6, MCR bits-1 & 2, FCTR bits 0-3 and IER bit-6. 2) RS485 half-duplex direction control, see FCTR bit-5, MCR bit-2 and MSR bits 4-7. RTS# output must be asserted before auto RTS flow , stopped when this pin is deasserted and will resume when this pin is asserted again. See EFR bit-7, MCR , normal logic 1. The software infrared enable bit (MCR bit6) will have full enable/disable control after Exar
Original

mcr 5102

Abstract: ST16C654DCQ64 (connected to VCC) or the 4X is selected when CLKSEL is a logic 0 (connected to GND). MCR bit-7 can override the state of this pin following reset or initialization (see MCR bit7). This pin is not available on 64 pin packages which provide MCR bit-7 selection only. -CS 16 13 - I Chip Select , pins provide individual channel interrupts, INT A-D. INT A-D are enabled when MCR bit-3 is set to a , , this pin can be used in conjunction with MCR bit-3 to enable or disable the three state interrupts
Exar
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ST16C654 ST16C554 ST68C554 ST16C654CQ64 ST16C654DCQ64 16C454 ST16C654/654D 64-BYTE

mcr 5102

Abstract: M68000 Register (5-102 , .6-2 6.3.1 Module Configuration Register (
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OCR Scan
M68300 MC68349 M68000 MC68681 8332 memory pipeline synchronization CPU030 CPU32

BL35P12

Abstract: mcr 20-100 KBIM MCR SCR WDTR R W R W R W W KBE7 KBIE X OTP OPTION 5.2.1 A PORTA PORTAPort A Data , 1PA7:PA0 10Kohm 0PA7:PA0 I/O 5.2.8 MCR MCRMiscellanceous Control Register Register MCR 38K LVRPB Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 MCR $0C KBIE KBIC LVRE PBP PBB1 PBB0 bit 1 OUTC bit 0 , 5.10.1.7 16 16 CPU 16 N K 5.10.1.8 8 PC -128 +127 5.10.2 MCU 65 BL3502S 61 1/ 2 3 4 5
Shanghai Belling
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BL35P12 BL2220 mcr 20-100 400K4MH 200MIL/SOP20 300MIL/SSOP20/DIP20 150MIL

557 timer connections

Abstract: M68000 Configuration Register (5-102 , .6-22 6.7.1 Module Configuration Register (
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OCR Scan
MC68340 557 timer connections M68SGG
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