NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: is the Disk Active/Slave Present signal in the Master/ TTL I/O Slave handshake protocol. 3mA , pulled up signal is used to configure this device as a Master TTL Input or a Slave. When the pin is , This input/output is the Pass Diagnostic signal in the Master/Slave TTL I/O handshake protocol. 3mA , connector and Interface · Configures to Master or Slave IDE device · Replaces IDE hard drive for , -IOIS16 -IOIS16 A1 -PDIAG A0 A2 -CE1 -CE2 -DASP GND GND VCC FDB2 Master/Slave Jumper Pins A-F Key ... | Original |
6 pages, |
SLFLD35-320C ide 2.5 DASP SLFLD35-032C SLFLD35-064C SLFLD35-096C SLFLD35-128C SLFLD35-160C SLFLD35-1GBC SLFLD35-224C SLFLD35-256C 40 pins ide connector 800MB 800MB abstract |
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| Abstract: , Single 5V TTL Comparators MAX910/MAX911 MAX910/MAX911 High-Speed, Threshold-Programmable Voltage Comparator s MAX912/MAX913 MAX912/MAX913 Sinlge, Dual, Ultra-Fast, Low-Power, Precision TTL Comparators MAX915/MAX916 MAX915/MAX916 Ultra-High-Speed, Master/Slave TTL Comparators MAX921/MAX922/MAX923/MAX924 MAX921/MAX922/MAX923/MAX924 Single/Dual, Ultra-Low-Power, Single-Supply , Op Amp MXL1013/MXL1014 MXL1013/MXL1014 Dual/Quad, Precision Op Amps MXL1016/MXL1116 MXL1016/MXL1116 Ultra-Fast, Precision TTL ... | Original |
571 pages, |
toshiba Motherboards laptop layout toshiba notebook schematic diagram free MAX4420 MAX1771 equivalent spice model MM74C945 CCTV MINI CAMERA CIRCUIT laptop motherboard circuit diagram digital voltmeter using DVM IC 7107 smps Power Supply Schematic Diagram High Current Battery Charger philips semiconductor data handbook MAX038 MAX038EVKIT MAX038 abstract |
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| Abstract: a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bits or more width systems. The MHS MASTER/SLAVE dual port approach in memory system applications results in full speed, error free operation without the need for additional discrete logic. Master and slave devices , data bus to 16 bits or more using master/slave devices when using more than one device. D On chip , (MASTER) : BUSY is open drain output and requires pull up resistor M 671421 (SLAVE) : BUSY is input 2. ... | Original |
2 pages, |
671321l M671321/M671421 M671321/671421 M67132/M67142 M671321/M671421 abstract |
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| Abstract: designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bits or more width systems. The MHS MASTER/SLAVE dual port approach in memory system applications results in full speed, error free operation without the need for additional discrete logic. Master and slave devices provide two independent ports with separate control, address and I/O pins that permit , bus to 16 bits or more using master/slave devices when using more than one device. D On chip ... | Original |
2 pages, |
671321/M 671321/M abstract |
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| Abstract: a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bits or more width systems. The MHS MASTER/SLAVE dual port approach in memory system applications results in full speed, error free operation without the need for additional discrete logic. Master and slave devices , data bus to 16 bits or more using master/slave devices when using more than one device. D On chip , (MASTER) : BUSY is open drain output and requires pull up resistor M 671421 (SLAVE) : BUSY is input 2. ... | Original |
2 pages, |
M67132 "Dual-Port RAM" M671321/M671421 M671321/671421 M67132/M67142 M671321/M671421 abstract |
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| Abstract: FAIRCHILD TTL/SSI • 9N73/5473 9N73/5473, 7473 . 9N107/54107 9N107/54107, 74107 DUAL JK MASTER/SLAVE FLIP-FLOP WITH , Master/Slave flip-flops with a separate clear and a separate clock for each flip-flop. Inputs to the , coupling transistors which connect the master and slave sections. The sequence of operation is as follows: 1) Isolate slave from master. 2) Enter information from J and K inputs to master. 3) Disable J and K inputs. 4) Transfer information from master to slave. DIP (TOP VIEW) LOGIC AND CONNECTION DIAGRAM 9N73 ... | OCR Scan |
2 pages, |
9N73 7473 dual JK 74107 TTL 74107 5473 Flip-Flop 7473 7473 ttl 7473 ttl 7473 9N73/5473 9N107/54107 9N73/5473 abstract |
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| Abstract: FAIRCHILD TTL/SSI . 9N72/5472 9N72/5472, 7472 JK MASTER/SLAVE FLIP-FLOP WITH AND INPUTS DESCRIPTION - The TTL/SSI 9N72/5472 9N72/5472, 7472 is a JK Master/Slave flip-flop with AND gate inputs. The AND gate inputs for entry , the coupling transistors which connect the master and slave sections. The sequence of operation is as follows: 1) Isolate slave from master. 2) Enter information from AND gate inputs to master. 3) Disable AND gate inputs. 4) Transfer information from master to slave. LOGIC AND CONNECTION DIAGRAM DIP (TOP VIEW ... | OCR Scan |
2 pages, |
7472 FAIRCHILD 7472 Connection diagram 9N72 7472 truth table 7472 Flip-Flop 9N72/5472 9N72/5472 abstract |
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| Abstract: FAIRCHILD TTL/SSI . 9N76/5476 9N76/5476, 7476 DUAL JK MASTER/SLAVE FLIP-FLOP WITH SEPARATE PRESETS, CLEARS AND CLOCKS DESCRIPTION - The TTL/SSI 9N76/5476 9N76/5476, 7476 is a Dual JK Master/Slave flip-flop with separate presets, separate clears and separate clocks. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of operation is as follows: 1) Isolate slave from master. 2) Enter ... | OCR Scan |
2 pages, |
7476 JK ic 7476 ttl 7476 Connection diagram 9N76 7476 fairchild IC 7476 JK 7476 master slave circuit diagram with IC 7476 7476 J-K Flip-Flop ttl 7476 Flip-Flop 7476 7476 VCC input of ic 7476 9N76/5476 9N76/5476 9N76/5476 abstract |
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| Abstract: , (Authorization) (Pairing). . Slave, Master. UART, , , PIN- . , . , Master/Slave. RF . 50 ( ). SMD- . Bluetooth-, -. , , , , . (Master/ Slave) , (Reset) . , , . , «» UART UART. (GPIO4 Master GPIO5 Slave) , , «». Bluetooth, Master (, , USB-, ) (SPP). : · BT-20 BT-20 (Slave) ( , Master, ); · ... | Original |
3 pages, |
ZV43 rainsun MTS2BTSMI BLUEtooth csr PAN1550 CSR Bluetooth EDR bluetooth RS232 SPK-EBM001A Bluetooth bt-20 ZV4301 BT-20 RS-232 bluetooth uart ttl BlueCore4 bluetooth ttl datasheet abstract |
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| Abstract: word widths of 16-bits or more can easily be created by using the Master/Slave chip select and cascading more than one device • On-chip arbitration logic • Single BE pin for Master or Slave operation , dual-port or as a combination Master/Slave dual-port for 16-bit or more word width systems. By grounding the Busy Output Enable (BE) pin to designate it as the Master and programming all others high as Slaves , Battery backup operation: 2 volts data retention • TTL compatible, single 5V (± 10% power supply • ... | OCR Scan |
1 pages, |
DUAL-PORT STATIC RAM MS6138 MS6138 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| Analog Switch 1372.pdf DG300A DG300A DG300A DG300A Dual SPST, TTL-Compatible, CMOS Analog Switch 1554.pdf DG301A DG301A DG301A DG301A Dual SPST, TTL-Compatible, CMOS Analog Switch 1554.pdf DG302A DG302A DG302A DG302A Dual SPST, TTL-Compatible, CMOS Analog Switch 1554.pdf DG303A DG303A DG303A DG303A Dual SPST, TTL-Compatible, CMOS Analog Switch 1554.pdf DG304A DG304A DG304A DG304A , TTL-Output ADC 1638.pdf MAX1160EVKIT MAX1160EVKIT MAX1160EVKIT MAX1160EVKIT Evaluation Kit for the MAX1160 MAX1160 MAX1160 MAX1160 1737.pdf MAX1161 MAX1161 MAX1161 MAX1161 10-Bit, 20Msps, TTL-Output ADC 1639.pdf MAX1161EVKIT MAX1161EVKIT MAX1161EVKIT MAX1161EVKIT Evaluation Kit for the MAX1161 MAX1161 MAX1161 MAX1161 1737.pdf MAX www.datasheetarchive.com/files/design-elektronik/maxim.htm |
Design Elektronik | 19/10/1998 | 318.58 Kb | HTM | maxim.htm |
| Designed for NuBus TM Interface Applications Supports Master, Slave, and Master/Slave Applications ; typical configurations include master-only, slave-only, and master/slave. Additionally, it provides extra five major signal groups: byte decode signals, data/address interface-control signals, master/slave signals required to multiplex and de-multiplex the NuBus TM data/address lines. The master/slave inputs control the master- and slave-state machines. The NuBus TM card-slot signals interface with the NuBus TM www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/datasht/schs010.htm |
Texas Instruments | 01/06/1998 | 6.83 Kb | HTM | schs010.htm |
| Permits control of slave units from the Mux488/64 master or from a parallel (LPT) port or 8-bit per unit, and by up to 1024 single-ended channels via a master/slave architecture. In addition to /64 series master/slave architecture enables a single IEEE 488 address or RS-232-C RS-232-C RS-232-C RS-232-C port to control a total of 16 multiplexers (1 master unit and 15 slave units) with as many as 1024 single-ended or 512 , LPT port, or digital I/O port. Mux/64 slaves can be controlled only from the Mux488/64 master unit www.datasheetarchive.com/files/iotech/iotechca/docs/wcd00001/wcd00112.htm |
Iotech | 16/12/1998 | 7.95 Kb | HTM | wcd00112.htm |
| ) connector: Provides easy access to 32 TTL digital alarm outputs and 8 digital input lines Master/slave on/off switch CA-35-1 CA-35-1 CA-35-1 CA-35-1 master/slave cable (included with both Exp/10A and Exp/11A expansion -to-access switches for selecting Exp/10A slave ID Master/slave (DB25) connectors: Provides connection from Exp/11A Rear Panel Master/slave (DB25) connectors: Provides connection from the Temp acquisition with TTL input signal TTL output (BNC) connector: TTL output signal occurs for each www.datasheetarchive.com/files/iotech/iotechca/docs/wcd00004/wcd00466.htm |
Iotech | 16/12/1998 | 5.96 Kb | HTM | wcd00466.htm |
| Please enable Javascript in your browser. National P/N DM54L73 DM54L73 DM54L73 DM54L73 - Dual Master-Slave J Products > Military/Aerospace > Logic > Low Power TTL > DM54L73 DM54L73 DM54L73 DM54L73 DM54L73 DM54L73 DM54L73 DM54L73 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs Generic P/N 54L73 54L73 54L73 54L73 clock is low the slave is isolated from the master. On the positive transition of the clock, the data Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs 88 Kbytes 6-Jan-98 View www.datasheetarchive.com/files/national/htm/nsc02487-v2.htm |
National | 14/09/2000 | 10.74 Kb | HTM | nsc02487-v2.htm |
| Configurations The Mux488/64 master and Mux/64 slave accept up to 64 single-ended or 32 differential inputs 488 control (Mux488/64 master only) Master/slave (DB15 female) connector: used to daisy settings, command set, channel grouping, output configuration, and master/slave operation Analog System Configurations Master/Slave IEEE 488 Based System Master/Slave RS-232 RS-232 RS-232 RS-232 Based System with ), TTL levels Mux/64 Control Interface: 8-bit (7 data plus strobe), TTL levels Slave Control Output www.datasheetarchive.com/files/iotech/iotechca/docs/wcd00003/wcd00321.htm |
Iotech | 16/12/1998 | 15.12 Kb | HTM | wcd00321.htm |
| L10 - Triple 3-Input NAND Gate DM54L72 DM54L72 DM54L72 DM54L72 - AND-Gated Master-Slave J-K Flip-Flop with Preset, Clear and Complementary Outputs DM54L73 DM54L73 DM54L73 DM54L73 - Dual Master-Slave J-K Flip-Flops with Clear and Complementary National Semiconductor Products Catalog: Military/Aerospace: Logic: Low Power TTL [Information as of 02-Apr-98] Click on Selection Guide below to compare products, or use Parametric Search Engine . National Semiconductor Products Logic (231) Low Power TTL (9 www.datasheetarchive.com/files/national/docs/wcd00044/wcd04440.htm |
National | 03/04/1998 | 5.81 Kb | HTM | wcd04440.htm |
| -Gated Master-Slave J-K Flip-Flop with Preset, Clear and Complementary Outputs $14.60 Cerpack 14 Full production DM54L73 DM54L73 DM54L73 DM54L73 Dual Master-Slave J-K Flip-Flops with Clear National Semiconductor Selection Guide: Military/Aerospace: Logic: Low Power TTL [Information as of 02-Apr-98] Result on Low Power TTL : (9 Records Found) Base Part Number Title Price Package Type No. of Pins Status DM54L00 DM54L00 DM54L00 DM54L00 Quad 2-Input NAND Gate $13 www.datasheetarchive.com/files/national/docs/wcd00044/wcd0443f.htm |
National | 03/04/1998 | 5.83 Kb | HTM | wcd0443f.htm |
| memory Supports master/slave mode for system expansion up to 256 channels from either a single -channel requirements, the Control488/16 series offers a master/slave architecture that supports expansion up to times. System Configurations The Control488/16 series master/slave architecture enables a single IEEE 488 address or RS-232-C RS-232-C RS-232-C RS-232-C port to control a total of 16 control units (1 master unit and 15 slave Control/16 master unit, an LPT port, or a digital I/O interface. For safety, slave unit default www.datasheetarchive.com/files/iotech/iotechca/docs/wcd00001/wcd00115.htm |
Iotech | 16/12/1998 | 18.58 Kb | HTM | wcd00115.htm |
| Structure OUTPUT SLAVE LATCH OUTPUT MASTER LATCH INPUT LATCH INTERNAL DATA BUS I/O PIN PUSH-PU LL TRISTATE OUTPUT SLAVE LATCH INTERNAL DAT A BUS I/O P IN OP EN DRAIN TTL (or Schmitt Trig ger)PUSH-PULL TO P ST9+ / I-O PORTS / 2 ® ST9+ I/O PORTS Configuration Analog Input CMOS or TTL level Schmitt Trigger FUNCTION CMOS: Vil (max) : 0.3 Vcc Vih (min) = 0.7 Vcc TTL: Vil (max) : 0.7 Volt OD HI-Z HI-Z PP OD HI-Z PXn Input Type TTL or Schmitt Trigger TTL or Schmitt Trigger TTL or www.datasheetarchive.com/download/48289847-845297ZC/07_iopr.zip (07_iopr.pdf) |
STMicroelectronics | 20/10/2000 | 40.29 Kb | ZIP | 07_iopr.zip |