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AXA016A0X3-SR12 GE Critical Power 12V Austin SuperLynxTM 16A: Non-Isolated DC-DC Power Module, 10Vdc –14Vdc input; 0.75Vdc to 5.5Vdc output; 16A Output Current, 100Ω Resistor between Sense and Output Pins visit GE Critical Power
AXA016A0X3-SR12Z GE Critical Power 12V Austin SuperLynxTM 16A: Non-Isolated DC-DC Power Module, 10Vdc –14Vdc input; 0.75Vdc to 5.5Vdc output; 16A Output Current, 100Ω Resistor between Sense and Output Pins visit GE Critical Power
QW030AJ1 GE Critical Power QW030xx DUAL Series Power Modules: dc-dc Converters, 18 Vdc to 36 Vdc or 36 Vdc to 75 Vdc Inputs visit GE Critical Power
QW030CL1 GE Critical Power QW030xx DUAL Series Power Modules: dc-dc Converters, 18 Vdc to 36 Vdc or 36 Vdc to 75 Vdc Inputs visit GE Critical Power
EBVW012A7B1Z<641-PHZ GE Critical Power EBVW012A7B Series DC-DC Converter Power Module, 34 - 75Vdc Input, 12.0 Vdc Output and 12.7A Output Current visit GE Critical Power
EP0300AC48TEZ GE Critical Power EP0300AC48TEZ, Compact, Ssingle Phase, Hotpluggable, Fan-cooled Rectifier and Battery Charger 300W Output at 48-58Vdc visit GE Critical Power

logic ic 7476 pin diagram

Catalog Datasheet MFG & Type PDF Document Tags

logic ic 7476 pin diagram

Abstract: and pin diagram of IC 7476 FLIP-FLOP LOGIC DIAGRAM MODE SELECT- TRUTH TABLE OPERATING MODE ®D Asynchronous Set Asynchronous , 54/7476 54H/74H76 54LS/74LS76 DESCRIPTION The "76'' is a Dual JK Flip-Flop w ith individ ual J, K, Clock, Set and Reset inputs. The 7476 and 74H76 are positive pulse triggered flip-flops. JK inform ation , levels as shown in the Truth Table. LOGIC SYMBOL 2 7 4- J SD Q -15 9 , PACKAGES PIN CONF. Fig A Fig A Fig A Fig A Fig A Fig A (See Section 9 for further Package and Ordering
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74LS76 logic ic 7476 pin diagram and pin diagram of IC 7476 logic ic 7476 flip-flop pin diagram 7476 truth table pin diagram for IC 7476 pin configuration of 74LS76 IC N7476N N74H76N N74LS76N N74H76F N74LS76F

logic ic 7476 pin diagram

Abstract: logic ic 74LS76 pin diagram Width-ns (Typ) Enable/Clock to Q Delay-ns (Typ) Data to Q Delay ns (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram 9314 D EV IC E NO . 4xD 4xD 4xD 4x(RS) 4xD 1 4xD i- 4xD 4xD , Dissipation mW (Typ) Logic/Connection Diagram X X X X X X X cn 05 O ro ro o , C D Packag (s) C O C D FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE ,
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logic ic 74LS76 pin diagram 74LS107 ic 74109 74109 dual JK 74LS109 IC 74196 54LS/74LS77 54LS/74LS75 54LS/74LS197 93L14 54LS/74LS196 54LS/74LS279

7476 truth table

Abstract: 2526-N,! DESCRIPTION PIN CONFIGURATION The 2526 is a high speed 5 184-bit Static Read-Only , Address 10 3 Address 9 BLOCK DIAGRAM Address 1 [7 O u tp u t Enable Address 5 VGG O u tp , IRPW t AD *AG *A1 *A2 ! oe TIMING DIAGRAM NOTE: Ati Times Measured from 50% Points, tr = , CODE CONVERSION DECIMAL ADDRESS " V NOTES: 1. BCD IC to A S C II in leftmost column, Baudot to , ' Blank Name 2 Data Cards Card No. 1 Column 1-9 10 11-19 20 21-29 73 74-76 77
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0I0I00I0I 0I00I0T0T NQISM3AN03 N-92S

74LS76P

Abstract: 74LS76D 76 CO NNECTIO N DIAGRAM PINOUT A /54/7476 0 / / o / c ^ ^S4H/74H76 Gf / ci 7 ^ 54LS/74LS76£ v , both Q and Q HIGH LOGIC SYMBOL The 'LS76 is a dual JK, negative edge-triggered flip -flo p also , PIN PKGS Plastic DIP (PI Ceramic DIP (D) Flatpak (F) ? 3 ? 8 COMMERCIAL GRADE Vcc = +5.0 V , MILITARY GRADE Vcc = +5.0 V ±10%, Ta = -55° C to +125°C PKG TYPE 9B Vcc = Pin 5 GND = Pin 13 OUT , 3 for U.L. definitions PIN NAMES J l, J2. K l, «2 C P , CPz C o i, C d 2 SOI, §02 Q i, Q i. 02. O
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74LS76P 74LS76D IC 7476 pinout 7476PC 74LS76 pinout IC 74LS76 54/74LS 54/74H CLS76

logic ic 7476 pin diagram

Abstract: , Three-State, Non-Inverting D ecem 1992 ber Pinouts Features 20 PIN C ER AM IC DUAL-IN-LINE M , to the A bus. The logic level at the direction input (DIR)_determines the data direction. The output enable input (OE) puts the I/O port in the high-impedance state when high. 20 PIN C ER AM IC , ', and VO < 0.5V is recognized as a logic â'0 â' . 7-476 Specifications HCS245MS TA B LE 2. AC , burn-in. 2. Each pin except VCC and GND will have a resistor of 680£2 ± 5% for dynam ic burn-in
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IL-STD-1835 CDIP2-T20 MIL-STD-1835 CDFP4-F20 HCS245M

logic ic 7476 pin diagram

Abstract: and pin diagram of IC 7476 , the d ata from the m aster is transferred to th e slave. The logic state of J and K inputs m ust not , edge of the clock pulse. A low logic level on the preset or clear inputs will se t or reset the outputs regardless o f th e logic levels of the other inputs. Features Alternate M ilitary/A erospace device , specifications. Connection Diagram D ual-ln-Line Package K1 16 Q1 15 Q1 14 GND 13 K2 12 Q2 11 Q2 10 J2 9 , , D M 5476J, D M 5476W or DM 7476N See Package N um ber J16A , N 16E or W 16A H = High Logic Level
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circuit diagram with IC 7476 IC 7476 JK Features of IC 7476 DM7476

logic ic 7476 pin diagram

Abstract: radiation hardened, high-speed, CMOS/SOS Logic Family. 20 PIN CERAMIC FLAT PACK MIL-STD-1835 DESIGNATOR , V VIL 0 V GND 0 V 7-479 LOGIC NOTE: Each pin except VCC and GND will have , December 1992 Pinouts Features 20 PIN CERAMIC OUAL-IN-UNE MIL-STD-1835 DESIGNATOR CDIP2-T20, LEAD , 5 16 AK 1 7 14 LOGIC The Harris HCS245MS is a Radiation Hardened Non-Invert­ ing , the A bus. The logic level at the direction input (DIR) determines the data direc­ tion. The output
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logic ic 7476 pin diagram

Abstract: HCS245MS as a logic "0". 7-476 Specifications HCS245MS TABLE 2. AC ELECTRICAL PERFORMANCE , , Non-Inverting December 1992 Features Pinouts 20 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR , from the A bus to the B bus or from the B bus to the A bus. The logic level at the direction input , high-impedance state when high. 20 PIN CERAMIC FLAT PACK MIL-STD-1835 DESIGNATOR CDFP4-F20, LEAD FINISH C , operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS245MS
Harris Semiconductor
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4 bit synchronous ic 7476

Abstract: logic ic 7476 pin diagram determined by the SCLK. REV. PrH FUNCTIONAL BLOCK DIAGRAM S CL K CO NT RO L LO G IC S DA TA CS A D 7476/A D 7477 G ND PRODUCT HIGHLIGHTS 1. First 10-/12-Bit ADCs in a SOT-23 package. 2 , ( 2 .50 ) RY A IN AL IM IC L N RE CH A P E AT T D PIN 1 0 .03 7 (0 .9 5 ) B S C 0 , 10-/12-B IT S UC CE S SIV E AP P RO X IM A TIO N AD C T /H RY A IN AL IM IC L N RE CH A , Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input
Analog Devices
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4 bit synchronous ic 7476 INTERNAL DIAGRAM OF IC 7476 logic diagram of ic 7476 applications IC 7476 AD7476 AD7476ART AD7476/AD7477 MC68HC16 68HC16
Abstract: le in 13" reel. U se suffix = SCX. Connection Diagram Logic Symbol Pin A ssignm ent for D , Logic Diagram DETAIL A DS009593-4 P lease note th a t th is dia g ra m is pro vid e d o n ly fo r , a g a tio n delays. w w w .fa ir c h ild s e m i.c o m 2 Unit Loading/Fan Out 74F Pin Nam , R C H II_ D E M IC O N D U C T O R t 74F779 8-Bit Bidirectional Binary Counter with , current 80 m A typ G uaranteed 4000V m inim um ESD protection Available in S O IC (300 mil only -
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74F779PC 74F779SC DS009593

74hc595n

Abstract: 74HC595M "X " to th e o rd e rin g code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP , Semiconductor Corporation D S005342.prf www.fairchildsenii.com MM74HC595 Logic Diagram (positive , of the storage register. The 74H C logic fam ily is speed, fu nction, and pin-out com patible w ith the standard 74LS logic fam ily. All inputs are protected from dam age due to static discharge by , -Lead Sm all O utline Integrated C ircuit (SO IC), JED E C M S-013, 0 .300" W ide 16-Lead Small O utline
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74hc595n 74HC595M MM74HC595N 74hc595w M74HC595N MS-001
Abstract: Tape and Reel. Specify by appending suffix "X" to the ordering code. Logic Symbols Connection Diagram RAM 1 6 X 4 *o - *i a2 0' 0 A- A 15 -G 1 . ^ 3 - 3 CS- ^ 1 EN , w ww .fairchildsem i.com 74F189 Unit Loading/Fan Out U.L. Pin Names Ao~A3 CS WE Do- D3 O 0 , Data High Im pedance WE L H X Write Read Inhibit Block Diagram D0 D1 D 2 D 3 WE · CS w w , .5 V G round Pin Input Voltage (Note 2) Input C urrent (Note 2) Voltage Applied to O utput in HIGH -
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74F189SC 74F189SJ 74F189PC DS009493

logic ic 7476 pin diagram

Abstract: pin diagram for IC 7476 irc u it (S O IC ), J E D E C M S -0 1 3 , 0 .3 0 0 W id e 1 6 -L e a d P la s tic D u a l-ln -L in e P a c k a g e (P D IP ), J E D E C M S -0 0 1 , 0 .3 0 0 W id e Logic Symbols Connection Diagram , u g h c a s c a d in g Logic Diagram w w w.fairchildsenii. com 74F583 Absolute Maximum , s t rip p le c a rry fo r e c o n o m ic a l e x p a n s io n S u m o u tp u t d e la y tim e 1 6.5 , - s2GND - - " " A0 Bo - s 0 Si 9 - S 3 Unit Loading/Fan Out 74F Pin Nam es A0
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74F583SC 74F583PC

IC 7474 pinout

Abstract: is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Logic Diagram TRUTH TABLE DISABLE INHIBIT , Low Logic 1 = High Z = High Im pedance X = Donâ'™t Care FIGURE 1. LOGIC DIAGRAM O F 1 O F 6 , Specifications for Description of â'˜Bâ'™ Series CMOS D evicesâ' Functional Diagram Applications â'¢ 3 , Description â Q2 CD4502BMS consists of six inverter/buffers with 3 state outputs. A logic â' 1â' on , common busing of the outputs, thus simplifying system design. A Logic â'1â' on the INHIBIT input
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IC 7474 pinout CD4502BM

circuit diagram with IC 7476

Abstract: 600/DG34-1021-36-1012-F ADVANCE I^ IC R D N 32K, 64K X MT2LSYT3272B2, MT4LSYT6472B2 72 SYNCHRONOUS SRAM MODULE , , REGISTERED INPUTS AND BURST COUNTER PIN ASSIGNMENT (Top View) 160-Lead, Dual Read-out DIMM (SF-1) 32K x 72 , include the output enable (OE) and the clocks (CLK0 and CLK1) and burst mode (MODE). The PIN# SYMBOL PIN# 41 1 Vss 42 2 DQ0 3 Vcc2 43 44 4 DÛ2 DQ4 45 5 0Q6 46 6 7 47 DQP0 Vss 48 8 9 009 49 DQ11 50 10 11 , NC Vss PIN* 81 62 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106
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600/DG34-1021-36-1012-F 160-L MT2LSYT3272B2G-10 MT4LSYT6472B2G-10 256KB 512KB A3-A18

INTERNAL DIAGRAM OF IC 7476

Abstract: D4029BC a p p e n d in g th e suffix le tte r "X " to th e orde rin g code. Connection Diagram Pin A ssig nm ents for DIP, SO IC and SOP JA M INPUTS V DD CLOCK 15 UP/DOWN B IN A R Y / DECADE PRESET EN , Semiconductor Corporation DS005960.prf www.fairchildsenii.com CD4029BC Logic Diagram CARRY w w , escription 16-Lead Sm all O utline Integrated C ircuit (SO IC), JED EC M S-013, 0 .300" W ide body 16-Lead Sm , . com 4 CD4029BC Logic Waveforms Decade M ode 5 www.fairchildsenii.com CD4029BC
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D4029BC 4029bc cd4029bcn 7476 up down counter LD 7476 PS 7476 counter 4029BC
Abstract: available in Tape and Reel. Specify by appending suffix "X" to the ordering code. Logic Symbols Connection Diagrams Pin Assignment for DIP and SOIC Ao 1 cs- 2 W Ë- 3 16 - VC C 15 " Al 14 - a 2 13 - , www.fairchildsenii.com 74F189 Unit Loading/Fan Out Pin Names Description U.L. HIGH/LOW A 0- A 3 CS WE D o_ D3 0 , plem ent o f Stored Data High Im pedance Block Diagram D0 D1 D2 D3 A 0 -A1 - , RatingSfNote S torage Tem perature A m bient Tem perature under Bias Junction Tem perature under Bias V CC Pin -
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S-001

truth table for ic 74138

Abstract: 16CUDSLR cycles Elim ination of un u sed gates A utom atic pin and p art assignm ents SALSA logic m inim ization , ation. Figure 1. A+PLUS Block Diagram A+PLUS Simulation Virtual Logic Analyzer (V LA) Functional , Sim ulator (FS1M) V irtual Logic A nalyzer (VLA) Log ic M a p II p rog ra m m i ng so ft w a re D ocum , PLCAD-SUPREME & PLS-SUPREME A+PLUS Programmable Logic Development System & Software September , Description A+PLUS is a co m prehensive CAE system for designing logic w ith A ltera Classic EPLDs. A+PLUS
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truth table for ic 74138 16CUDSLR ALU IC 74183 IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table

pin diagram for IC 7476

Abstract: logic ic 7476 pin diagram failures, VDD = 10V ± 0.5V Logic Diagram INVERTER/BUFFER NO. 1 TRUTH TABLE VDD DI , NETWORK X = Don't Care VSS FIGURE 1. LOGIC DIAGRAM OF 1 OF 6 IDENTICAL INVERTER/BUFFERS Test , `B' Series CMOS Devices" 12 INHIBIT D2 8 9 Q4 Functional Diagram Applications · 3 , with 3 state outputs. A logic "1" on the OUTPUT DISABLE input produces a high impedance state in all , Logic "1" on the INHIBIT input switches all six outputs to logic "0" if the OUTPUT DISABLE input is a
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ic 7476 pin diagram or ic 7473 CMOS ttl 7478 IOH15 TTL 7479 ISO9000

IC 7474 pinout

Abstract: TTL 7479 0.5V Logic Diagram INVERTER/BUFFER NO. 1 TRUTH TABLE VDD DI * DISABLE Dn Qn 0 , Care VSS FIGURE 1. LOGIC DIAGRAM OF 1 OF 6 IDENTICAL INVERTER/BUFFERS Test Circuit and Waveform , Description of `B' Series CMOS Devices" 12 INHIBIT Functional Diagram Applications · 3 State Hex , logic "1" on the OUTPUT DISABLE input produces a high impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic "1" on the INHIBIT input
Intersil
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pin diagram of ttl 7473 pin DIAGRAM OF IC 7473 features of ic 7474 7473 cmos 7474 ic chip ic 7473
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