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Part Manufacturer Description Datasheet BUY
TTL-LOGIC-DATABOOK Texas Instruments TTL-LOGIC-DATABOOK visit Texas Instruments
SN7474N-10 Texas Instruments TTL/H/L SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, PLASTIC, DIP-14 visit Texas Instruments
SN7474N3 Texas Instruments Dual D-Type Positive-Edge-Triggered Flip-Flops With Preset And Clear 14-PDIP 0 to 70 visit Texas Instruments
SN7474J Texas Instruments TTL/H/L SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14 visit Texas Instruments
SN7474J-00 Texas Instruments TTL/H/L SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14 visit Texas Instruments
SN7474N-00 Texas Instruments IC TTL/H/L SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, PLASTIC, DIP-14, FF/Latch visit Texas Instruments

logic ic 7474 pin diagram

Catalog Datasheet MFG & Type PDF Document Tags

pin DIAGRAM OF IC 7474

Abstract: ic 7474 pin diagram 7474, LS74A, S74 LOGIC DIAGRAM MODE SELECT - FUNCTION TABLE IN PU TS O P E R A T IN G M O D E , Signetics 7474, LS74A, S74 Flip-Flops Dual D-Type Flip-Flop Product Specification Logic , delay time for reliable operation. T Y PE 7474 74L S 74A 74S 74 NOTE: T Y P IC A L f , AX 25M H z 33M H z 100M H z T Y P IC A L SU PP LY C U R R E N T (T O T A L ) 17m A 4m A 30m A For inform , and -0 .4 m A i|L PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 4 10 Roi I
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pin DIAGRAM OF IC 7474 ic 7474 pin diagram 7474 ic pin configuration IC 7474 pin configuration pin IC 7474 logic ic 7474 pin diagram 7474N 74S74N N741S 1N916 1N3064
Abstract: half-stepping and micro­ stepping. The relationship between the logic input signals at pin 7 and 9 in , until a current reverse command is given. By reversing the logic level of the phase input (pin 8 , LSTTL-compatible logic input, a current sensor, a monostable and an output stage with built-in protection diodes , AB SO LU TE M AXIM UM RA TING S (Note 1) Voltage Logic Supply, V c c , .45V Input Voltage Logic Inputs (Pins 7, 8, 9 -
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UC1717 UC3717 UC3717S UC3717N UC1717J UC1717SP

logic ic 7476 pin diagram

Abstract: logic ic 74LS76 pin diagram Width-ns (Typ) Enable/Clock to Q Delay-ns (Typ) Data to Q Delay ns (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram 9314 D EV IC E NO . 4xD 4xD 4xD 4x(RS) 4xD 1 4xD i- 4xD 4xD , Dissipation mW (Typ) Logic/Connection Diagram X X X X X X X cn 05 O ro ro o , C D Packag (s) C O C D FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE ,
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logic ic 7476 pin diagram logic ic 74LS76 pin diagram 74LS107 ic 74109 74109 dual JK 74LS109 54LS/74LS77 54LS/74LS75 54LS/74LS197 93L14 54LS/74LS196 54LS/74LS279

74LS74 truth table

Abstract: 7474PC (Each Half) INPUT @ tn D L H OUTPUTS @ tn + 1 IO O L H PIN PKGS Plastic DIP (P) C eram ic DIP (D , 14 (41 GND = Pin 7 (11) 11 13 C- 02 4-81 NATIONAL SENICOND {LOGIC} DEE D | h S D U E E , NATIONAL SENICOND -CLOGIO D2E D | LSDllES D0b371S 2 | T-46-07-09 74 CO NNECTIO N DIAGRAM S PINO UT A 54/7474 54H/74H74 54S/74S74 54LS/74LS74 DUAL D-TYPE POSITIVE EDGETRIG GERED FLIP-FLOP , i = Bit tim e a fte r c lo c k pulse. H L LO G IC SYMBOL ORDERING CODE: See Section 9 COM M
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74LS74 truth table 7474PC 74LS74PC DE flip-flop 7474 logic diagram of ic 7474 74ls74 pin configurations 5474DM 54H74DM 54S74DM 54LS74DM 54S74FM 54/74H

pin DIAGRAM OF IC 7474 d flip flop

Abstract: western digital FD1771 Interface (Refer to Figure 1-1 FD1771 Block Diagram) The FD1771 hand les si ngle density frequency , identifies the presence of a logic 1 bit; the absence of this pulse is interpreted as a logic 0 bit. The , missing clock bits (logic 0) as shown below: The F01771 generates all controls to position the read , . The particular motor interface is chosen by hardwiring the external pin, 3PM. ALL REFERENCE TO , ~_~ (IFUs~D) FD1771 SYSTEM BLOCK DIAGRAM FIG1 COR P OR A , I 0 IV c·a
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pin DIAGRAM OF IC 7474 d flip flop western digital FD1771 ic D flip flop 7474 digital ic 7474 internal circuit diagram 74ls161 counter floppy disk Stepping Motors connection D1771
Abstract: 1992 Features Pinouts - r - S L r C T \ 20 PIN CERAMIC DUAL-IN-LINE MIL-STD , Max - VIH = VCC/2 Min gnd 20 PIN CERAMIC FLAT PACK MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD , . This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS244MS is , . Class 1 Thermal Im pedance. flj» 8^ Weld Seal D IC , functional tests VO 2 4.0V is recognized as a logic T , and VO s 0.5V is recognized as a logic "0". 7-469 -
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CDIP2-T20

TC430

Abstract: external DIAGRAM OF IC 7474 Diode Driver Differential Line Driver PIN Diode Driver Level Shifting Driver FUNCTIONAL DIAGRAM V DD , speed-up capacitors. ORDERING INFORMATION Part No. TC430C PA TC430IJA TC430M JA Package 8-Pin Plastic 8-Pin CerDIP 8-Pin CerDIP Temperature Range 0 °C to +70°C - 2 5 ° C t o +85°C - 55°C to + 1 25°C PIN CONFIGURATION d ig ita l r r GROUND INPUT [ 2 LL TC430 T ] nc 3 »0 1 © VssE n c |7 jO V DD 7] v02< ° > BONDING DIAGRAM 6-26 2030 £-09 TELEDYNE
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external DIAGRAM OF IC 7474 teledyne tsc QGD73 Q0073 74S74

or ic 7473 CMOS

Abstract: pin diagram for IC 7473 VT VW GND Tri-State High Timing Diagram and Load Circuit LOGIC V V V V V V DUT TEST POINT C , , Tri-State Pinouts 20 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C TOP VIEW , 2A1 ÏÜ 1Y 3 Ï 3 2A0 E 2Y2 [T 1A 2Ü 2Y1 E 1A3E 2YÛ E GND [10 20 PIN CERAMIC FLAT PACK , radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS244MS is supplied in a 20 lead Weld Seal , : These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling
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or ic 7473 CMOS pin diagram for IC 7473 circuit diagram for IC 7473 ic 7472 pin diagram 7474 truth table ic 7473 pin diagram
Abstract: ) 20 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C TOP VIEW â'¢ Dose , radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS244MS is supplied in a 20 lead Weld Seal , 20 PIN CERAMIC FLAT PACK MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C TOP VIEW TnEi , follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1992 File Number 2133.1 , . 2. For functional tests VO a 4.0V is recognized as a logic â'1", and VO < 0.5V is recognized as a -
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82303

Abstract:   Integrated Card Setup Port (96H) B 100.pin Plastic Quad Flat Package The 82303 Local Channel Support , reduce system cost, design effort, and form factor constraints by replacing 50 IC devices in an equivalent IBM system. The 82303 integrates most all logic required to implement a parallel port. This port , only logic not integrated is that which di­ rectly drives the physical parallel port connector , devices in an equivalent IBM system. Included as an appendix to this data sheet is a func­ tional logic
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82303 P103RD P103W P101RD M60STR

INTERNAL DIAGRAM OF IC 7474

Abstract: ALI m1541 a1 selection - enable/disable each output pin - mode as tri-state, test, or normal Power Management Capability 48 MHz for USB support Internal Crystal Load Capacitors 48-pin SSOP package Spread Spectrum , 1 1 100 66.6 33.3 CONNECTION DIAGRAM IMISG750 BLOCK DIAGRAM XIN REF REF , ) SDRAM_FB AGP (1:2) AGP0 SDATA SCLK CONTROL LOGIC PLL2 4 SDRAM (8:11) VDDA 48 MHz , Product PIN DESCRIPTION Pin Number Pin Name PWR I/O TYPE 4 XIN VDD I OSI
International Microcircuits
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ALI-M1541 INTERNAL DIAGRAM OF IC 7474 ALI m1541 a1 ALI m1541 internal circuit of ic 7474 M1541 SG750 IMISG750CYB SG750CYB

INTERNAL DIAGRAM OF IC 7474

Abstract: ic 7474 pin diagram buffers are stopped in low state putting the IC in shutdown mode. This is a bidirectional pin. During , selection - enable/disable each output pin - mode as tri-state, test, or normal Power Management Capability 48 MHz for USB support Internal Crystal Load Capacitors 48-pin SSOP package Spread Spectrum Technology for EMI reduction BLOCK DIAGRAM XIN REF REF XOUT VDDC CPU (0:2) 3 SW15 , LOGIC PLL2 4 SDRAM (8:11) VDDA S1 S0 CPU AGP PCI 0 0 0 60 60
International Microcircuits
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48MHZ

ALI m1541

Abstract: ALI m1541 a1 Jumperless frequency selection - enable/disable each output pin - mode as tri-state, test, or normal Power Management Capability 48 MHz for USB support Internal Crystal Load Capacitors 48-pin SSOP package Spread Spectrum Technology for EMI reduction BLOCK DIAGRAM XIN REF REF XOUT VDDC SW15 PCI_STP , CONNECTION DIAGRAM IMISG748 VDD REF/SW15 VSS XIN XOUT VDDP PCI_F/S1 PCI0/S2 VSS PCI1 PCI2 PCI3 , ALI-M1541 chipset with AGP on Pentium® Boards. Approved Product PIN DESCRIPTION Pin Number Pin Name
International Microcircuits
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ALI chipset M1541 SG748 IMISG748CYB SG748CYB

ALI m1541

Abstract: ALI m1541 a1 are stopped in low state putting the IC in shutdown (static) mode. This is a bidirectional pin. During , enable/disable each output pin - mode as tri-state, test, or normal Power Management Capability 48 MHz for USB support Internal Crystal Load Capacitors 48-pin SSOP package Spread Spectrum Technology for , 30.0 33.3 CONNECTION DIAGRAM IMISG748 VDD REF/SW15 VSS XIN XOUT VDDP PCI_F/S1 PCI0/S2 VSS PCI1 , 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 · · · · · BLOCK DIAGRAM XIN REF XOUT
International Microcircuits
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M1541 a1 ic 7474 with timing diagram PCI 6601

ALi M6759 A1

Abstract: ALI M6759 l l l l 8051 instruction set compatible 8 bit microcontroller 8051/8052 compatible pin out , programming 44 pin PLCC or QFP package General Description The M6759 is an 8032/8052 instruction , . -Proprietary, Confidential, Preliminary- Product Brief M6759: 8 bit MTP Micro-controller Pin , .2 P0.3 44-pin PLCC Package RST RXD NC TXD /INT0 /INT1 T0 T1 1 40 M6759 29 7 , .3 P1.2 P1.1 P1.0 NC VCC P0.0 P0.1 P0.2 P0.3 44-pin QFP Package M6759 12 23 /WR
Acer Laboratories
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ALi M6759 A1 ALI M6759 M6759 A1 ACER LABORATORIES INC 7474 pin out diagram 8052 basic 1830-B 6759DS02

IC 7400

Abstract: pin DIAGRAM OF IC 7474 d flip flop (pin 22) is set to logic "1" (see Timing Diagram). The Start Convert must now be brought high again for , Diagram. 11. One TTL load is defined as sinking 40^ with a logic "1" applied and sour-cing 1.6mA with a , , MN5614, MN5615 and MN5617 require an external -10.000V reference. BLOCK DIAGRAM PIN DESIGNATIONS Start , 's internal Digital to Analog Converter (D/A). See Block Diagram. Holding the A/D's Start Convert (pin 1) low , FEATURES â'¢ 24 Pin Hermetically Sealed Leadless Package â'¢ Fast 13/^sec Conversion Time â
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IC 7400 pin configuration of d flip flip 7474 IC-7400 IC7400 7474 D flip flop free IC TTl 7474 free MIL-STD-883 MN5610 12-BIT MN5616

INTERNAL DIAGRAM OF IC 7474

Abstract: HM 9820 Programmable registers featuring: - Jum perless frequency selection - enable/disable each output pin - mode as , Capacitors 48-pin SSOP package S p rea d S p e c tru m T e c h n o lo g y fo r EMI re d i tion S2 0 0 0 0 1 , PCI 30 33.4 25 37.5 25 27.77 30.0 33.3 CONNECTION DIAGRAM IMISG750 'v ~- ^ 48 47 46 45 44 43 42 , C R IP T IO N Pin N u m b er 4 5 7 Pin N a m e XIN XOUT S1 PCI_F PW R VDD VDD VDDP VDDP IO I o I, PU , an externally generated reference signal. If an external input refernce is used, Pin 5 is left
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HM 9820 AU-M1541 750CYB

8052 basic

Abstract: 7474 pin out diagram compatible 8 bit microcontroller 8051/8052 compatible pin out Complete static design, wide range of , consumption ROM Code Protection 4.5V~5.5V operation voltage, 12V programming 44 pin PLCC or QFP package , : 8 bit MTP Micro-controller Pin Configuration T2EX T2 NC VCC AD0 AD1 AD2 AD3 P1.4 P1.3 P1.2 P1.1 P1.0 NC VCC P0.0 P0.1 P0.2 P0.3 44-pin PLCC Package RST RXD NC TXD /INT0 , .3 44-pin QFP Package M6759 12 23 /WR /RD XTAL2 XTAL1 GND NC A8 A9 A10 A11 A12
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7474 pin configuration features of ic 7474 7474 pin diagram 8052 pin structure 3030 micro controller 7474 14 PIN

ic D flip flop 7474

Abstract: IC 7474 truthtable Logic Diagram November 1993 3 OUTPUT BUFFERS O1, O3 O4, O6 O5, O7 Philips , input/output pin arrangement. Also recognizing that all logic functions could be built from the , Philips Semiconductors Programmable Logic Devices Designing with programmable macro logic INTRODUCTION TO PROGRAMMABLE MACRO LOGIC DESIGN CONCEPTS Programmable Macro Logic (PML), an extension of the Programmable Logic Array (PLA) concept combines a programming or fuse array with an array of
Philips Semiconductors
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PLHS501 IC 7474 truthtable philips for ic 7474 7474 D flip-flop circuit diagram PLHS502 IC 7474 flipflop 7474 D flip-flop

IC 7474 pinout

Abstract: is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Logic Diagram TRUTH TABLE DISABLE INHIBIT , Low Logic 1 = High Z = High Im pedance X = Donâ'™t Care FIGURE 1. LOGIC DIAGRAM O F 1 O F 6 , Specifications for Description of â'˜Bâ'™ Series CMOS D evicesâ' Functional Diagram Applications â'¢ 3 , Description â Q2 CD4502BMS consists of six inverter/buffers with 3 state outputs. A logic â' 1â' on , common busing of the outputs, thus simplifying system design. A Logic â'1â' on the INHIBIT input
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IC 7474 pinout CD4502BM
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