NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: , and Carry-in to Carry-out propagation delay of 2.2ns. The 10180 is designed to be used in special purpose adder/subtractor or in high-speed multiplier arrays. All unused inputs can be left open due to , Product Specification ECL Products 10180 Adder/Subtractor Dual 2-Bit Adder/Subtractor FEATURES • , 10180 is a high-speed, low power, general purpose adder/subtractor. Inputs tor each adder are: Carry-in , GE s) F, coin E ... | OCR Scan |
5 pages, |
10180N 10180F highspeed multiplier datasheet abstract |
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| Abstract: provided: the product XY and the product XY ±8. Because of the internal adder/subtractor, a speed advantage is gained when using the 'F784 over using a separate adder and multiplier chip. (Refer to Figure B). , control the internal adder/subtractor stage. The multiplier word is then applied to the Y input in a serai , arithmetic to be performed. A serial adder/subtractor enables constants to be added to the product. Typically , understanding of logic operations and should not be used to estimate propagation delays. figure a 4-561 Powered ... | OCR Scan |
6 pages, |
F385 F384 74F10 4 bit serial subtractor 54F/74F784 54F/74F784 abstract |
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| Abstract: adder/subtractor and is particularly useful as a companion part to the SN 54 LS384/SN LS384/SN 74 LS384 LS384 serial/parallel two's-com-plement multiplier. The 'LS385 LS385 contains four independent adder/subtractor elements with , logic diagram (each adder/subtractor, positive logic) J3J- CLK - A 5, 15, 16) ^ (2,9, 12, 19) v (4 , positive-edge triggered and controls the sum and carry flip-flops according to the function table. SN54LS38S SN54LS38S . , , SN74LS385 SN74LS385 QUADRUPLE SERIAL ADDERS/SUBTRACTORS schematics of inputs and outputs logic symbol''' ... | OCR Scan |
4 pages, |
SN74LS385 SN54LS385 SDLS170 LS385 LS384/SN LS384 SN54LS385 abstract |
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| Abstract: available. Therefore, an adder may be used as a subtractor in many applications and the need for SSI circuits , be truncated to eight bits by using the rounding input(s) to add one in either the 27 adder for , input to 27 adder RS = (XM±YM)R = signed rounding input to 26 adder Rounding input levels and results , Additional inputs, Rs and R0 for the 'F558 or R for the 'F557, allow the addition of a bit for rounding to , Description The 'F557 and 'F558 multipliers are 8x8 combinatorial logic arrays capable of multiplying numbers ... | OCR Scan |
7 pages, |
F283 block diagram of 8 bit array multiplier 74f557 54F/74F557 54F/74F558 54F/74F557 abstract |
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| Abstract: Referring to the Logic Diagram, the multiplicand (Xo - X7) latches are enabled to receive new data when PL , incorporated into the Carry logic. The cells â- â- use the Carry-save technique to avoid the complexity and delays , a2 a, ao clear adder/subtractor and registers Y.®Y.- , cp m k sum_ d a cp Co IT" June 1987 , device • Asynchronous Parallel Load (PL) input clears the internal flip-flop to the start condition and enables the X latches to accept new multiplicand data DESCRIPTION The 'F384 is an 8-bit sequential logic ... | OCR Scan |
7 pages, |
N74F384N N74F384D F384 74F384 carry save adder 74F384 abstract |
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| Abstract: to the sum of the clock-to-data valid time of the slave device and data set-up time of the master , equal to the sum of the clock-to-address valid time of the master device and address set-up time of , ideal, meaning that the signal switches from a LOW to HIGH logic level and HIGH to LOW logic level , depending on VIH and VIL. VIH VIL LOW HIGH LOW Figure 13. Valid Logic Levels Timing Diagram , time greater than the setup time before the rising clock edge and still be valid. The input adder ... | Original |
23 pages, |
TMS320C6416-6E3 CYD18S72V-100BBC CYD18S72V-133BBC tcam AN5010 timing analysis example tcam cypress TMS3206416 cypress tcam AN5010 abstract |
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| Abstract: multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point , effective weighting of the sign bit is 220 Adder/Subtractor Stage The 31-bit real and imaginary results , option is selected and the adder/subtractor contains a 32-bit word, then an invalid result will be , cycle of each pass and for the lay time between passes. It instructs the control logic to update the , equipment using such information and to ensure that any publication or data used is up to date and has not ... | Original |
15 pages, |
PDSP16318A PDSP16116A PDSP16116 MIL-883 FULL SUBTRACTOR using 41 MUX DS3707 PDSP16116 abstract |
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| Abstract: 32 bit Adder/Subtractors and all the control logic required to support Block Floating Point , 31 bit Real and Imaginary results from the Multipliers are passed to two 32 bit Adder / Subtractors. The Adder calculates the imaginary result (Xr x Yi) + (Xi x Yr) and the Subtractor calculates the , selected and the Adder / Subtrac-tors contain a 32 bit word, then an invalid result will be passed to the , ROUND control is used to round the most significant 16 bits of the Adder/Subtractor result prior to ... | OCR Scan |
16 pages, |
PDSP16330 PDSP16318 PDSP16116 PDSP1601 mark CEY 64 point radix 4 FFT 32 bit adder IC to design 2 by 2 binary multiplier PDSP16330 plessey PDSP16116 abstract |
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| Abstract: PDSP16116 PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic , effective weighting of the sign bit is 220 Adder/Subtractor Stage The 31-bit real and imaginary results , is selected and the adder/subtractor contains a 32-bit word, then an invalid result will be passed , cycle of each pass and for the lay time between passes. It instructs the control logic to update the , fully determine the performance and suitability of any equipment using such information and to ensure ... | Original |
17 pages, |
subtractor using TTL CMOS PDSP16318A PDSP16116A PDSP16116 GG144 DS3707 4 bit binary full adder and subtractor PDSP16116 abstract |
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| Abstract: /Subtracters and all the control logic required to support Block Floating Point Arithmetic as used in FFT , Functions Adder / Subtractor Stage The 31 bit Real and Imaginary results from the Multipliers are passed , ) and the Subtractor calculates the Real result (Xr x Yr) - (Xi x Yi). Each Adder / Subtractor , edge. ROUND The ROUND control is used to round the most significant 16 bits of the Adder/Subtractor , between passes. It instructs the control logic to update the value of the global weighting register and ... | OCR Scan |
14 pages, |
radix-2 PDSP16510 PDSP16350 PDSP16318A PDSP16256 PDSP16116A PDSP16116 ALU of 4 bit adder and subtractor PDSP16116/A PDSP16116 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| designer to easily view HDL source, RTL schematics (block diagram) and the Gate-level schematic at the Resource Sharing allowing Synplify to share logic resources and yielding improved area results ) for Xilinx XC4000 XC4000 XC4000 XC4000, bypassing XBLOX completely. Infers counters, adders, subtractors, etc., and . Supports passing input setup and output transition time preferences to Xilinx. Cleanly supports techniques. Synplify also includes a language sensitive editor with syntax and synthesis checker to www.datasheetarchive.com/files/xilinx/docs/wcd0002d/wcd02d2c.htm |
Xilinx | 17/07/1998 | 8.23 Kb | HTM | wcd02d2c.htm |
| -flops. CLBs are arranged in columns and rows on the FPGA device. The goal is to place logic in columns on the manufactured and delivered to the end user. Gate arrays are another type of IC whose logic is defined during a file for design mapping, placement, and routing. Guided design allows logic to be modified or templates to aid you in common VHDL and Verilog constructs, common logic functions, and architecture primitives (flip-flops or latches) that implements high-level functions, such as adders, subtractors, and www.datasheetarchive.com/files/xilinx/docsan/fsu/app1.htm |
Xilinx | 12/11/1998 | 23.1 Kb | HTM | app1.htm |
| version of a file for design mapping, placement, and routing. Guided design allows logic to be modified or -flops or latches, that implements high-level functions, such as adders, subtractors, and dividers. Soft is a set of combinatorial and sequential logic elements arranged to operate in a predefined sequence state, and the logic network performs the operations to determine the next state. See also Â"symbolic ) and automatically creates a lower level of logic abstraction using a library containing primitives www.datasheetarchive.com/files/xilinx/docsan/fqs/app1.htm |
Xilinx | 12/11/1998 | 27.48 Kb | HTM | app1.htm |
| following: • translates the design netlist • maps the logic to CLBs (FPGAs) • places and routes the design 9500 devices. For information on how to create and process XC9500 XC9500 XC9500 XC9500 designs using this software, refer to , Xilinx Foundation Series, and ZERO+ are trademarks of Xilinx, Inc. The Programmable Logic Company and The any time, in order to improve reliability, function or design and to supply the best product possible to give an overview of the features and additions to Xilinx's newest product-Foundation 1.4. The www.datasheetarchive.com/download/14200312-986630ZC/wcd02623.zip (fnd14qsg.pdf) |
Xilinx | 13/07/1998 | 1871.78 Kb | ZIP | wcd02623.zip |
| bounce, which limits many programmer's ability to test high speed parts and achieve high programming socket supports most 20- to 84-pin PLCC devices using either particle interconnect technology or long Ground control circuitry using relay switching; no need to tie up a slow parallel port. Product Information The PC82 Universal Programmer and Tester is a PC based development tool designed to program and special adapters, the PC82 can program devices up to 84 pins in DIP, PLCC, LCC, QFP, SOP and PGA packages www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5333-v1.htm |
STMicroelectronics | 14/06/1999 | 170.55 Kb | HTM | 5333-v1.htm |
| bounce, which limits many programmer's ability to test high speed parts and achieve high programming socket supports most 20- to 84-pin PLCC devices using either particle interconnect technology or long Ground control circuitry using relay switching; no need to tie up a slow parallel port. Product Information The PC82 Universal Programmer and Tester is a PC based development tool designed to program and special adapters, the PC82 can program devices up to 84 pins in DIP, PLCC, LCC, QFP, SOP and PGA packages www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5333.htm |
STMicroelectronics | 02/04/1999 | 170.58 Kb | HTM | 5333.htm |
| -Realizer and how to create applications using ST-Realizer. In this tutorial, you'll learn how to create an implant into the body, or (b) support or sustain life, and whose failure to perform, when properly . 3/248 Chapter 2 2 INTRODUCTION AND CONCEPTS The founding idea behind ST-Realizer was to create programming expertise to efficiently design embedded applications for ST6 and ST7 microcontrollers. ST into ST6 and ST7 microcontrollers without having any knowledge of assembler code. To do this www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5113-v3.htm |
STMicroelectronics | 11/01/2000 | 358.34 Kb | HTM | 5113-v3.htm |
| behind creating applications using ST-Realizer and how to create applications using ST-Realizer. In how to operate ST- Realizer using the default toolbar setup shown above. If, while you are doing this surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when CONCEPTS The founding idea behind ST-Realizer was to create an accessible and user-friendly software you to create applications ready to be loaded into ST6 and ST7 microcontrollers without www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5113-v1.htm |
STMicroelectronics | 20/10/2000 | 366.13 Kb | HTM | 5113-v1.htm |
| -Realizer and how to create applications using ST-Realizer. In this tutorial, you'll learn how to create an implant into the body, or (b) support or sustain life, and whose failure to perform, when properly . 3/248 Chapter 2 2 INTRODUCTION AND CONCEPTS The founding idea behind ST-Realizer was to create programming expertise to efficiently design embedded applications for ST6 and ST7 microcontrollers. ST into ST6 and ST7 microcontrollers without having any knowledge of assembler code. To do this www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5113-v4.htm |
STMicroelectronics | 25/05/2000 | 358.3 Kb | HTM | 5113-v4.htm |
| Da ta B oo k The Programmable Logic Data Book Click anywhere on this page to continue distributors, and our manufacturing partners, welcome to our 1996 Data Book, and thank you for your interest in 's leading supplier of programmable logic, we would like to pledge our continuing commitment to providing you functionality and ease-of-use in programmable logic development systems. You can expect this pace of innovation to continue, and even increase, as we maintain our leadership role in bringing leading www.datasheetarchive.com/download/90212243-999460ZC/dbookold.zip (DBOOKOLD.PDF) |
Xilinx | 07/09/1996 | 10340.01 Kb | ZIP | dbookold.zip |