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Part Manufacturer Description Datasheet BUY
SN74160J-00 Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CDIP16 visit Texas Instruments
SN74160N-00 Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDIP16 visit Texas Instruments
SN74160N-10 Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDIP16, CERAMIC, DIP-16 visit Texas Instruments
SN74160J Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CDIP16, CERAMIC, DIP-16 visit Texas Instruments
TTL-LOGIC-DATABOOK Texas Instruments TTL-LOGIC-DATABOOK visit Texas Instruments
SN74160N Texas Instruments Synchronous decade counters 16-PDIP 0 to 70 visit Texas Instruments

logic diagram of 74160

Catalog Datasheet MFG & Type PDF Document Tags

74160 pin description

Abstract: 74160 Multistage Counting Scheme LOGIC DIAGRAM, 74160 »0 5 o O O , 853-0531 81502 Signetics Logic Products Product Specification Counters 74160, 74161, 74163, LS160A , pulse can be used to enable the next cascaded stage (see Figure B). For conventional operation of 74160 , By Its Respective Manufacturer Signetics Logic Products Product Specification Counters 74160 , Counters 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A LOGIC DIAGRAMS LS160A 03 Oj D, o0 LD03030S
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74160 pin description 74160 pin diagram of 74163 74160 function table 74161 logic diagram of 74160 74LS160A 74LS162A 74LS161A 74LS163A N74160N N74LS160AN

IC 74161

Abstract: lm 74161 AF0230'S Figure 1 LOGIC DIAGRAM, 74160 d3 d2 d, Do LD03020S December 4, 1985 5-286 Signetics Logic Products Product S pecification Counters 74160, 74161, 74163, LS160A, LS161A , (see Figure B). For conventional operation of 74160, 74161 and 74163, the following transitions should , Logic Products Product S pecifica tio n Counters 74160, 74161, 74163, LS160A, LS161A, LS162A , roduct S pe cifica tio n Counters 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A LOGIC
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IC 74161 lm 74161 IC 74160 IC 74160 decade counter diagram ic 74163 74161/74160 function table N74161N N74-LS161AN N74LS162AN N74163N N74LS163AN N74LS161AD
Abstract: 1 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A S ig n e lic s Counters Logic , 81502 Product Specification Signetics Logic Products Counters 74160, 74161, 74163, LS160A , PE inputs are HIGH at or before the transi­ tion. For conventional operation of 74160, 74161 , Specification Signetics Logic Products Counters 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A , MR Qo Qi C 3a Q* à TERMINAL CO U N T *6 AF02301S Figure 1 LOGIC DIAGRAM -
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N74LS161AN N74S163AD S4LS/74LS

ic 74160

Abstract: IC 74160 decade counter diagram Counting Scheme LOGIC DIAGRAM, 74160 O3 Dj Dj D0 December 4, 1985 5-286 Signetics Logic , Signetics 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A Counters Logic Products '160 , 653-0531 81502 Signetics Logic Products P roduct S pecifica tio n Counters 74160, 74161, 74163 , enable the next cascaded stage (see Figure B). For conventional operation of 74160, 74161 and 74163, the , Signetics Logic Products P roduct S p ecification Counters 74160, 74161, 74163, LS160A, LS161A
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pin diagram of ic 74163 diagram of IC 74160 of 74160 ic LM 74160 diagram of IC 74161 H C 5287 equivalent 74LS161 54LS/74LS F08270S

pin diagram of 74160

Abstract: 74160 function table .6 AF02301S Figure 1 LOGIC DIAGRAM, 74160 December 4, 1985 5-286 This Material Copyrighted By Its Respective Manufacturer Signetics Logic Products Product Specification Counters 74160, 74161, 74163 , Signetics 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A Counters Logic Products , 853-0531 81502 Signetics Logic Products Product Specification Counters 74160, 74161, 74163, LS160A , can be used to enable the next cascaded stage (see Figure B). For conventional operation of 74160
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pin diagram of 74160 74160 pin 74163 pin configuration 74ls161 counter pin configuration logic diagram 74160 74160 counter N74LS161

74163 four bit binary counter

Abstract: LS162A 1 1 U Oo O i D j TT 8 O LOGIC DIAGRAM, 74160 O3 Oj D, Dg s 8 O D3 - TC PE CEP , S ig n e tic s 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A Counters Logic Products , conventional operation of 74160, 74161 and 74163, the following transitions should be avoided. 1. 2 , December 4, 1985 5*285 Signetlcs Logic Products Product Specification Counters 74160, 74161 , Counters 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A LOGIC DIAGRAMS 'LS160A LD03030S
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74163 four bit binary counter 162 bcd counter diagram 74161 74LS163A equivalent 74160 circuit Synchronous 74163

74160 pin layout

Abstract: am7416 SN54J63W SN&4163X LOGIC SYMBOL VCC - P.n 16 GND " P-n 8 CONNECTION DIAGRAM Top View Vcc0,"T*jT- q . - , AmS4/74163 High-speed, look-ahead carry counter tor BCD |Am54/74160 Of Am54/74162) or binary (Am54 , Duration of tha Mi ort circuit tast tfiouM not axcaad on* mcckvJ. 6. içc to masaurad «vitti aU outputs , multiplanar*. DEFINITION OF FUNCTIONAL TERMS ICj, 2Cj Data Inputs. The four data inputs to each multiplexer ¡ = 0,1,2, and 3. 1Y,2Y Multiplexer Outputs. The output of each four-input multiplexer. A, B
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74160 pin layout am7416 IC 74160 DATA SHEET AM-7416 pins and their function in ic 74163 7416l 21850E/0-I

Truth Table 74160

Abstract: Truth Table 74161 . The LOW -to-HIGH transition of SPE on the 54/74161 and 54/74160 should only occur w hile CP is high , to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite , (SEU) Immunity < 2 x 10"9 Errors/Bit-Day (Typ) level of reliability. The Harris HCTS160T is a , reset and look-ahead carry logic. Counting and parallel presetting are accomplished synchronously with the low-to-high transition of the clock. A low level on the synchronous parallel enable input, SPE
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Truth Table 74160 Truth Table 74161 MIL-PRF-38535 HCTS160 TA14445A 1-800-4-HARRIS

Truth Table 74160

Abstract: IC 74160 atellite A pplications FlowTM (SAF) is a tradem ark of Harris C orporation. HCTS160T Functional Diagram , transition of PE or TE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation. 3. The LOW -to-HIGH transition of SPE on the 54/74161 and 54/74160 should only occur w hile CP is , intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Harris HCTS160T is a Radiation Hardened High Speed Presettable
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1-800-4-HARR

Truth Table 74161

Abstract: ark of Harris C orporation. HCTS160T Functional Diagram PO P1 P2 P3 TRUTH TABLE , HLLH for 160). 2. The H IG H-to-LO W transition of PE or TE on the 54/74161 and 54/74160 should only , devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large , - Single Event Upset (SEU) Immunity < 2 x 10"9 Errors/Bit-Day (Typ) level of reliability. The , features an asynchronous reset and look-ahead carry logic. Counting and parallel presetting are
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IC 74160

Abstract: Truth Table 74161 . The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation. 3. The LOW-to-HIGH transition of SPE on the 54/74161 and 54/74160 should , standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil HCTS160T is a Radiation Hardened , look-ahead carry logic. Counting and parallel presetting are accomplished synchronously with the
Intersil
Original
data sheet IC 74161 CDFP4-F16 HCTS160DTR HCTS160KTR IC 74160 decade counter FN4626 ISO9000

Truth Table 74160

Abstract: IC 74160 trademark of Intersil Corporation. HCTS160T Functional Diagram P0 P1 3 P2 4 P3 5 6 , HLLH for 160). 2. The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/74160 should only , standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil HCTS160T is a Radiation Hardened , look-ahead carry logic. Counting and parallel presetting are accomplished synchronously with the
Intersil
Original
4626 74161 truth table

74160 pin layout

Abstract: achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic , HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation 3. The LOW-to-HIGH transition of SPE on the 54/74161 and 54/74160 should only occur , decade synchronous counter that features an asynchronous reset and look-ahead carry logic. Counting and parallel presetting are accomplished synchro nously with the iow-to-high transition of the clock. A low
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HCTS160MS MIL-STD-1835 CDIP2-T16
Abstract: device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS160MS is supplied , transition of SPE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation , counter that features an asynchronous reset and look-ahead carry logic. Counting and parallel presetting are accomplished synchro­ nously with the low-to-high transition of the clock. A low level on the , letterindicate the state of the referenced output prior to the LOW-to+IIGH clock transition _ /~ = -
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IC 74160 decade counter diagram

Abstract: pin diagram of ic 74163 High-Speed CMOS Logic FUNCTIONAL DIAGRAM PO PI P2 PÎ Presettable Counters C D 54/74H C /H C T160 CD54 , -37957RI Fig. 2 - Logic diagram fo r the CDS4/74HC/HC T161 and 163. MODE SELECT - FUNCTION TABLE, 160 , ). (b) The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/74160 should only occur while CP , devices are presettable synchronous counters that feature look ahead carry logic for use in high-speed , negative-to-positive transition of the clock. _ A low level on the synchronous parallel enable input, SPE, disables
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92C540 CD74HC160 IC 74160 for decade counter ND06 CD54/74HC/HCT160 CD54/74HC/HCT161 CD54/74HC/HCT162 CD54/74HC/HCT163 CD54/74H CT161

pin diagram of ic 74163

Abstract: CD74HCT160 160 V IICL-1'IUII Fig. 1 - Logic diagram lor the CD54/74HC/HCT160 and 162. 160,162 STATE DIAGRAM , TO 92CM-37957RI Fig. 2 - Logic diagram lor the CDS4/74HC/HCT161 arid 163. UJ M a; Cd , 161 and HLLH for lèo), (b) The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/74160 should , /HCT163 HARRIS SEMICOND SECTOR 27E D B 43G2271 0G17hl2 â¡â HAS High-Speed CMOS Logic t- FUNCTIONAL DIAGRAM po pi p2 p3 _ 5 spe 92CS-37958 Presettable Counters CD54/74HC/HCT160 BCD Decade Counter
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CD74HCT160 AL207 CD54HC160 C074HC16 CD54/74HC/HCT RCA-CD54/74HC/HCT160 2C9-3796S 37968RI 92C3-37966R2 92CS-37969RI

Truth Table 74160

Abstract: IC 74160 LOW-to-HIGH transition of SPE on the 54/74161 and 54/74160 should only occur while CP is high for conventional , reset and look-ahead carry logic. Counting and parallel presetting are accomplished synchronously with the lowto-high transition of the clock. A low level on the synchronous parallel enable input, SPE , advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS160MS is supplied in a 16 lead Ceramic flatpack (K
Intersil
Original
74161 pin diagram and truth table HCTS160DMSR HCTS160HMSR HCTS160KMSR

Truth Table 74161

Abstract: 74161 pin diagram and truth table high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The H , . The LOW-to-HIGH transition of SPE on the 54/74161 and 54/74160 should only occur while CP is high for , presettable BCD decade synchronous counter that features an asynchronous reset and look-ahead carry logic. Counting and parallel presetting are accomplished synchronously with the lowto-high transition of the clock , Diagram PO P1 P2 P3 TRUTH TABLE INPUTS OPERATING MODE Reset (Clear) Parallel Load MR L H H Count
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CTS160
Abstract: 161 and HLLH for 160) 2. The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/74160 should , look-ahead carry logic. Counting and parallel presetting are accomplished synchronously with the lowto-high transition of the c lock. A low level on the synchronous parallel enable input, SPE, disables counting and , CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The H C T S 1 6 0 M S is s u p p lie d in a 16 lead C e ra m ic fla tp a -
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CMOS 4000B series 4161

Abstract: timing diagram of 74160 output capacitive load. 4160B 4Ì61B 4162B 4163B 4161B, 4163B LOGIC DIAGRAM (Clear is Synchronous for , structure. These counters are functionally equivalent to the 74160 - 74163 TTL counters. Two are , (4161, 4163). CONNECTION DIAGRAM (all packages) VDD C0 Q-j Q2 Q3 Q4 TE L I 16 15 14 13 12 11 10 9 , « Low level X » Don't care BLOCK DIAGRAM 7 Oâ'"â'" PE Ol â'"Ol4 10 O- TE 10â'" Clear Q2 , maximum rise and fall times of the clock input should be equal to or less than the transition times of
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CMOS 4000B series 4161 timing diagram of 74160 74160 4-bit Decade Counter Asynchronous reset 4000B BCD Decade logic diagram 74160 Synchronous 74160 4160B/4161B
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