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Part Manufacturer Description Datasheet BUY
SN54S114J-00 Texas Instruments IC S SERIES, NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, FF/Latch visit Texas Instruments
SN74S175FN Texas Instruments IC S SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC20, FF/Latch visit Texas Instruments
SN54S74W-10 Texas Instruments IC S SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14, FF/Latch visit Texas Instruments
SN74LS399D Texas Instruments IC LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, SO-16, FF/Latch visit Texas Instruments
SN74S174NSRG4 Texas Instruments IC S SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, GREEN, SOP-16, FF/Latch visit Texas Instruments
SN74LVC1G175YEPR Texas Instruments IC LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, BGA6, DSBGA-6, FF/Latch visit Texas Instruments

latching flip flop

Catalog Datasheet MFG & Type PDF Document Tags

6120* PDP-8 microprocessor

Abstract: tda 7560 4 x 35 W of the internal RUNHLT flip flop on the positive transition of the RUN/HTr line. 0 6 RUN Low This , -bit flip flop that serves as a high-order extension of the AC. It is used as a carry flip flop for 2 , modified. RUN/HLT The RUN/HLT line changes the state of the RUNHLT flip flop. This flip flop Isjnltlally , not cause the RUNHLT flip flop to be cleared, but causes entry Into panel mode with the HLTFLG set , . That is, the next instruction is guaranteed to be fetched barring a reset, DMAREQ pr RUN/HCT flip flop
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Abstract: * UC3842AD HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER â'"TOP VIEWâ'" 14 COMPENSATION 1 14 VREF 3 2 VOLTAGE FEEDBACK NC NC 13 7 VCC 12 (+12V) 3 3 4 CURRENT SENSE VREF NC GND OUTPUT RT, CT COMPENSATION 1 CURRENT SENSE 50V REFERENCE VCC UNDER VOLTAGE LOCK OUT 11 â'" + FLIP FLOP & LATCHING PWM 6 VC OUTPUT OSCILLATOR 1 CURRENT 3 SENSE 10 9 VREF UNDER VOLTAGE LOCK OUT VOLTAGE 2 -
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sr flip flop pin diagram

Abstract: latching flip flop and resets the SR flip f lop. CLOCK: Input Mode: This input strobes data into the buffer when it is activated (high) and sets the SR flip flop (SR = 0} while latching data on its negative transition. Output , request flip flop low (SR = 0) and latches data. When the CS1 and CS2 signais are enabled, the data , the port's register (DO O-DO 7) and service request flip flop. The 1852 operates over a 4â'"10.5
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sr flip flop pin diagram latching flip flop Hughes newport sr flip flop 1852C D00-D0

CD4004

Abstract: CD4011 equivalent 33132A E14 MM5624AM CD4024AN Dual J-K Flip Flop 33133F El 5 MM5625AN CD4025AN Triple 3-input NOR Gate , Flip Flop V , conditions. All inputs are protected against static discharge and latching conditions. See outline drawings
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CD4017AN CD4021 MM5635AN CD4049AN CD4004 CD4011 equivalent mm5649an mm5601 CD4011 aPPLICATIONS MM5611 CD4000 MM5611AN MM56XXA 33127B MM5616AN CD4016AN
Abstract: buffer register and resets the SR flip flop. CLOCK: Input Mode: This input strobes data into the buffer when it is activated (high) and sets the SR flip flop (SR = 0) while latching data on its negative , negative clock transition sets the service request flip flop low (SR = 0) and latches data. When the CS1 , request flip flop. The 1852 operates over a 4â'"10.5 voltage range while the 1852C operates over a -
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H1852 H1852C

IC 8212

Abstract: f 8212 n tro l device selection, data latching, o u tp u t b u ffe r state and service request flip -flo p , -STATE DATA LATCH DATA LATCH DATA LATCH DATA IN DATA IN DATA IN INTERNAL SR FLIP FLOP CLR - RESETS DATA LATCH SETS SR FLIP FLOP (NO EFFECT ON OUTPUT BUFFER) 2-56 AFN-00731C 8212 ABSOLUTE MAXIMUM , o n tro l and device selection logic. Also includ ed is a service request flip -flo p fo r the , FUNCTIONAL DESCRIPTION Data Latch The 8 flip -flo p s tha t make up the data latch are o f a " D" type
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IC 8212 f 8212 F8212 SR flip flop IC 8212 latch processor 8212 APN-00731C 00731C

Intel 82786

Abstract: 82786 latching transceivers at the end of the read cycle as indicated by SEN This event clears the BUSY flip flop in the EPLD When the BUSY signal goes inactive the 8051 reads the low byte from the latching , accessing the coprocessor Since wait states are not supported by the 8051 latching transceivers and dummy , 82786 This byte swapping is accomplished with the latching transceivers as well All of the control , the outputs of the latching transceivers at the proper time in the write cycle as indicated by SEN
Intel
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8000H-807FH A000H-BFFFH Intel 82786 82786 intel 8051 user manual 8051 demo board EPLD AB-38 5C060-55 5C060 C000H

1LB553

Abstract: Rauland ETS-003 parity, and w orking registers. T he SN 74A LV C 16823 can be used as tw o 9-bit flip -flop s o r one 18-bit flip-flop. W ith the clock-enable (CLKEN) input low, th e D-type flip -flop s enter data on , latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the
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1LB553 Rauland ETS-003 Silec Semiconductors 4057A transistor sr52 logos 4012B IEC179 TDA1510 TDA1510A

latching flip flop

Abstract: S-M 1D7 RESET 20 21 J Q J-K FILP FLOP K Q RESET IN1 EN VIN3 S1 21 D1 20 21 21 VIN4 IN2 EN D2 OUT 3-INPUT NAND POSSIBILITIES TTL - 11/3 SN5410 DUAL J - K FLIP FLOP , SEQUENCER (2-BIT BINARY COUNTER) J DECODER S1 20 21 E N Q J-K 20 FILP FLOP Q K RESET , ON - - - A Latching DPDT Switch The latch feature insures positive switching action in , 14 15 16 4 GND 5 FIGURE 12. A LATCHING DPDT 13-118 OUT 2 7 8 V
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S-M 1D7 SN74ALVC16823 18-BIT MIL-STD-883C JESD-17

Q11 DPDT

Abstract: CD4027 ic RESET 20 21 J Q J-K FILP FLOP K Q RESET IN1 EN VIN3 S1 21 D1 20 21 21 VIN4 IN2 EN D2 OUT 3 INPUT NAND POSSIBILITIES TTL - 11/3 SN5410 DUAL J - K FLIP FLOP , SEQUENCER (2BIT BINARY COUNTER) J Q DECODER S1 20 21 E N 20 J-K FILP FLOP Q K , ON - - - A Latching DPDT Switch +15V The latch feature insures positive switching , On 8 4 INDETERMINATE GND 5 FIGURE 12. A LATCHING DPDT 9-133 S3 S2 OUT 2 7
Harris Semiconductor
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IH5053 IH5052CDE IH5052MDE Q11 DPDT CD4027 ic Datasheet of ic CD4027 CD4027 applications DATA SHEET IC CD4011 ic cd4011 IH5052 20VP-P IH5053CDE

Q11 DPDT

Abstract: CD4027 applications resets the SAR. In this state, the output of the MSB flip flop is set to logic "0", the outputs of the other bit flip flops are set to logic "1", and the Status output (pin 21) is set to logic "1" (See , ) 6-55 gate delays can be employed or the Status can be made the input of a D flip flop whose clock , INFORMATION DESCRIPTION OF OPERATIONâ'"The Successive Approximation Register (SAR) is a set of flip flops , clock period after Status changes. LATCHING OUTPUT DATA Status ^ Strobe Strobe Clock Clock Start
Harris Semiconductor
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IH5053MDE CD4023 dm74c00 of cmos cd4023 DIP cd4027 cd4027 datasheet ih5052c SN5473 CD4027 DM7400 DM5400

MN5100

Abstract: MN5100H transition resets the SAR. In this state, the output of the MSB flip flop is set to logic "0", the outputs of the other bit flip flops are set to logic "1", and the Status output (pin 21) is set to logic "1" (See , . Simple gate delays can be employed or the Status can be connected to the input of a D flip flop whose , flip flops (and control logic) whose outputs act as both the direct (parallel) data outputs of the , . LATCHING OUTPUT DATA Status ^ Strobe > Strobe Clock Clock Start Status O Q _riiijnjajn_rxrLJiJTÌTJ
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MN5100 MN5101 WIN5100 MN5100H MN5101H MN5100/5101 MN5100/5101H MIL-H-38534

MN5150

Abstract: MN5150H Latching PWM and Steering Flip Flop VC Output B (Top View) Ramp Error Amp 3 Output Noninverting 2 , PWM Latch + 9.0 µA Steering Flip Flop Soft-Start CSS Q 0.5 V Soft-Start Latch 10 Ground , the next cycle. A toggle flip flop connected to the output of the PWM latch controls which output is active. The flip flop is pulsed by an OR gate that gets its inputs from the oscillator clock and the output of the PWM latch. A pulse from either one will cause the flip flop to enable the other output
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MN5150 MN5150H MN5150H/B MIL-STD-1772 MIL-STD-883
Abstract: TOSHIBA TC74VCX16823FT TRUTH TABLE (each 9-bit flip flop) INPUTS OUTPUTS Q OE CLR CKEN CK D L L , latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the ON Semiconductor
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MC34025 MC33025 UC3825 MC34025/D

TC74VCX16823FT

Abstract: 2D2401 Output 6 7 14 Error Amp Output B Latching PWM and Steering Flip Flop Output A , Comparator VCC VCC UVLO Error Amp PWM Latch Q Q Steering Flip Flop 11 Output A 12 , initiating the next cycle. A toggle flip flop connected to the output of the PWM latch controls which output is active. The flip flop is pulsed by an OR gate that gets its inputs from the oscillator clock and the output of the PWM latch. A pulse from either one will cause the flip flop to enable the other
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2D2401

UC3825

Abstract: 3525 PWM CT 6 11 Output A 7 10 Soft-Start Latching PWM and Steering Flip Flop 11 , Regulator VC 14 T Q PWM Latch Output B Q Q Steering Flip Flop + 11 Output A 12 , the oscillator can reset it, thus initiating the next cycle. A toggle flip flop connected to the output of the PWM latch controls which output is active. The flip flop is pulsed by an OR gate that , will cause the flip flop to enable the other output. I additional ) I charge 10 (I charge) A
ON Semiconductor
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3525 PWM IRF640 applications note MC34025DWR2G Philips 4312 020 MC34071 MMBD914 PDIP-16

3525 PWM

Abstract: transistor MBR 1045 1. Cell Structure SRAM uses 6 transistors cell Stable latching circuitry by Flip Flop PSRAM
ON Semiconductor
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transistor MBR 1045 P3270 philips 3f3 4312 020 4124 MC34025-D PHILIPS 4312 amplifier MC33025DW

PSRAM

Abstract: P811 transistor 33132A E14 MM5624AM CD4024AN Dual J-K Flip Flop 33133F El 5 MM5625AN CD4025AN Triple 3-input NOR Gate , conditions. All inputs are protected against static discharge and latching conditions. See outline drawings
Fujitsu
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PSRAM P811 transistor DQ8-15 P8-11

CD4035A

Abstract: CD4004 33132A E14 MM5624AM CD4024AN Dual J-K Flip Flop 33133F El 5 MM5625AN CD4025AN Triple 3-input NOR Gate , conditions. All inputs are protected against static discharge and latching conditions. See outline drawings
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MM5613AN MM5623AN MM5630AN 4011AE CD4035A cd4011 pin diagram CD4004AN MM5609AN MM5610AN CD4010AN 33123X CD4011 33124H MM5612AN
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