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jpeg encoder vhdl code

Catalog Datasheet MFG & Type PDF Document Tags

huffman encoding and decoding using VHDL

Abstract: verilog code for huffman coding registers interface Fully synchronous design Available as a fully functional and synthesizable VHDL or Verilog core including a test bench Datasheet JPEG Codec Programmer's Guide EDIF netlist, VHDL RTL source available extra Jp_chip.ucf Testbench, test vectors VHDL, Verilog Constraints File , . Please refer to the JPEG Code Programmer's Guide for detailed information on register and table , Virtex and VirtexTM-E devices 100% Baseline ISO/IEC 10918-1 JPEG compliant 8-bit/channel pixel depths
Xilinx
Original

verilog code for huffman coding

Abstract: huffman encoding and decoding using VHDL registers interface Fully synchronous design Available as a fully functional and synthesizable VHDL or Verilog core including a test bench Datasheet JPEG Codec Programmer's Guide EDIF netlist, VHDL RTL source available extra Jp_chip.ucf Testbench, test vectors VHDL, Verilog Constraints File , refer to the JPEG Code Programmer's Guide for detailed information on register and table programming , Virtex and VirtexTM-E devices 100% Baseline ISO/IEC 10918-1 JPEG compliant 8-bit/channel pixel depths
Xilinx
Original

verilog code for huffman coding

Abstract: huffman code generator in verilog Motion JPEG Encoder Core V2.0 March 4, 2002 Product Specification AllianceCORETM Facts TM , Interleaved and non-interleaved scans supporteded General Description The Motion JPEG (M-JPEG) Encoder is , equipment and office automation solutions, the JPEG encoder delivers the optimal performance and low power , implementation. March 4, 2002 1 Motion JPEG Encoder Core V2.0 Host Processor (or) State Machine , Quantization Bit Rate Control Run Length & Variable Length Encoder JPEG Stream Generator JPEG
Xilinx
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vhdl code for watchdog timer of ATM

Abstract: zilog 3570 (Configurable) YUV-to-RGB Color Space Converter Fast JPEG Codec Core High Performance JPEG Encoder Core High Performance JPEG Decoder Core JPEG 2000 Encoder Core Digital Video Broadcast (DVB) Modulator Reed-Solomon , Axcelerator Seq. Comb. -EV/-NET/-RTL -EV/-NET/-RTL -EV/-RTL -EV/-NET/-RTL -EV/-RTL -NET/-VHDL/-VLOG -NET/-VHDL/-VLOG -NET/-VHDL/-VLOG -NET/-VHDL/-VLOG -NET/-VHDL/-VLOG -NET/-VHDL/-VLOG -NET/-VHDL/-VLOG -NET/-VHDL/-VLOG -NET/-VHDL/-VLOG -NET/-VHDL/-VLOG -NET/-VHDL/-VLOG -NET/-VHDL/-VLOG -NET
Actel
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jpeg encoder vhdl code

Abstract: dct verilog code Scalado CAPSTM Compliance Integrates SpeedTagsTM tech- nology SVE-JPEG-E JPEG Features SpeedView Enabled JPEG Encoder Core Programmable quantization Programmable Huffman Tables (two , Control Unit JPEG Stream Stream Syntaxer FIFO Huffman Encoder DC DIFF RLE Zig-Zag , components) The SVE-JPEG-E core implements a high-performance image encoder that produces TM SpeedView enabled JPEG data streams. Supports all possible scan confi- TM Integrating the SpeedTags
Cast
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CS6100

Abstract: verilog code for huffman coding Divider QTMem Figure 2: CS6100 JPEG Encoder Block Diagram 2 Code Control Variable Length , CS6100 TM Motion JPEG Encoder Virtual Components for the Converging World The CS6100 Motion JPEG (M-JPEG) Encoder is a highly integrated application specific silicon core for leadingedge , Pending) Run Length & Variable Length Encoder JPEG Stream Generator Host Processor (or , integrated JPEG encoder suitable for a wide range of imaging applications. Designed for continuous data flow
Amphion Semiconductor
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verilog code for huffman coding jpeg encoder vhdl code huffman code generator in verilog yuv to rgb Verilog rgb yuv vhdl column-major DS6100

verilog code for huffman coding

Abstract: jpeg encoder vhdl code JPEG Encoder (JPEG-E) November 7, 2007 Product Specification AllianceCORETM Facts CAST , other designated brands included herein are trademarks of Xilinx, Inc. 1 JPEG Encoder (JPEG-E , brands included herein are trademarks of Xilinx, Inc. 3 JPEG Encoder (JPEG-E) Table 2: Core I/O , cost Constraints Files Jpeg-e.ucf Verification Test Bench, JPEG image input ­ RAW data output Features Instantiation templates VHDL, Verilog · Available under terms of the SignOnce
Xilinx
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jpeg encoder RTL IP core dct verilog code VHDL code DCT jpeg encoder verilog code encoder verilog coding jpeg encoder vhdl code ALMA

8251 intel microcontroller architecture

Abstract: vhdl source code for 8086 microprocessor . 51 JPEG Encoder , Adaptive Differential Pulse Code Modulation Altera Hardware Description Language Arithmetic logic unit , IP ISA ISDN JPEG LAN LAPB LAPD LCD LIFO LSI LUT MAC MAX MDA MII About this Catalog , SRAM SVCL UART USART USB UTOPIA VCI VGA VHDL VLSI VME VPI WAN WWW WYSIWYG XMidi vi , reassembly Special interest group Static random access memory Standard Component VHDL Library Universal
Altera
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8251 intel microcontroller architecture vhdl source code for 8086 microprocessor 8251 usart verilog coding for asynchronous decade counter verilog code for 8254 timer verilog code for median filter

Motion JPEG Codec

Abstract: decoder huffman Coefficient Quantization (QT) Divider QTMem ENCODE Code Control DCT Run Length Encoder , as part of the JPEG output stream, and a code control state machine (CodCtrl) that manages the , Define number of lines N Figure 5: Operation of JPEG encoder The core enters the Idle state , Motion JPEG Codec Core V1.0 March 4, 2002 Product Specification AllianceCORETM Facts TM , FIFO-like interface for JPEG decoding stream input No requirement for micro-processor control or
Xilinx
Original
Motion JPEG Codec decoder huffman vhdl code for huffman decoding mjpeg encoder huffman encoding and decoding using VHDL

vhdl code for huffman decoding

Abstract: jpeg decoder RTL IP core Full duplex, high performance video conferencing when used with the companion JPEG encoder Photo , encoder March 4, 2002 5 Motion JPEG Decoder Core V1.0 Decoder Operation Marker Decode State , Motion JPEG Decoder Core V1.0 March 4, 2002 Product Specification AllianceCORETM Facts TM , compliant with baseline JPEG standard ISO/ IEC 10918-1/2 - · Sustained 125 Msamples/second decoding capability Single sample per clock cycle processing Simple FIFO-like interface for JPEG decoding stream
Xilinx
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jpeg decoder RTL IP core mjpeg decoder CS6150 Variable Length Decoder VLD huffman decoder verilog CS6190 MULT18

verilog code for 2-d discrete wavelet transform

Abstract: wavelet transform verilog Encoder Tile RAM Entropy Encoder Output JPEG 2000 Data and Parameter Interface Entropy , Encoder Hardware Accelerator KEY FEATURES KEY METRICS1 Fully compliant with ISO/IEC 15444-1 JPEG , CS6510 TM JPEG2000 Encoder Virtual Components for the Converging World The CS6510 JPEG2000 Encoder is a high performance application specific solution enabling leading edge image , application specific accelerator core can provide. The CS6510 is a powerful and flexible JPEG 2000 encoding
Amphion Semiconductor
Original
DS6510 verilog code for 2-d discrete wavelet transform wavelet transform verilog vhdl code for discrete wavelet transform source code verilog for park transformation verilog source code for park transformation dwt verilog code

xilinx dwt image compression

Abstract: DWT image compression xilinx JPEG 2000 Encoder (JPEG2K-E) February 21, 2008 Product Specification AllianceCORETM Facts , Xilinx, Inc. 1 JPEG 2000 Encoder (JPEG2K-E) Figure 1: JPEG2K-E Function Controller Block , herein are trademarks of Xilinx, Inc. 3 JPEG 2000 Encoder (JPEG2K-E) Table 2: Core I/O Signals , templates Features VHDL Reference designs & Application notes application notes · Available , 15444-1 JPEG 2000 Image Coding Simulation Tool Used System compliance ModelSim and NC-Sim · Both
Xilinx
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xilinx dwt image compression DWT image compression xilinx vhdl code for dwt transform vhdl code for sdr sdram controller JPEG2K-E cctv wavelet

verilog code for 2D linear convolution

Abstract: verilog code for GPS correlator . 42 JPEG Decoder & Encoder . 43 JPEG Decoder & Encoder , Multiplier HDLC IIR Filter Library Image Processing Library Integer Divider JPEG Decoder and Encoder JPEG Decoder and Encoder Linear Feedback Shift Register Median Filter Library Multi-Standard ADPCM Numerically , . 56 Reed-Solomon Encoder
Altera
Original
verilog code for 2D linear convolution verilog code for GPS correlator vhdl code numeric controlled oscillator pipeline rx UART AHDL design verilog code car parking free verilog code of median filter M-CAT-AMPP-02 EPF10K10 EPF10K20 EPF10K30 EPF10K40 EPF10K50

verilog code for 2-d discrete wavelet transform

Abstract: XAPP921c Convolutional Code Decoder, CDMA2000/3GPP2 Turbo Convolutional Code Encoder, CDMA2000/3GPP2 UMTS , ) TurboConcept Turbo Encoder, DVB-RCS (S2001) iCoding Technology, Inc. Turbo Product Code Decoder , JPEG 2000 Encoder (BA112JPEG2000E) Barco-Silex JPEG Fast Codec (JPEG_FAST_C) CAST, Inc. JPEG 2000 Encoder (JPEG2K_E) · Low risk through reprogrammability that provides flexibility for , ) CAST, Inc. JPEG, Fast Encoder (JPEG_FAST_E) CAST, Inc. JPEG, Fast gray scale image decoder
Xilinx
Original
XAPP921c simulink universal MOTOR in matlab turbo encoder model simulink matched filter simulink simulink model for kalman filter using vhdl fpga based wireless jamming networks

vhdl code for DES algorithm

Abstract: XAPP921c Reed-Solomon Decoder 4 Reed-Solomon Encoder 4 Turbo Convolutional Code Decoder, CDMA2000/3GPP2 4 Turbo Convolutional Code Encoder, CDMA2000/3GPP2 4 UMTS/3GPP Turbo Convolutional Decoder , Turbo Encoder, DVB-RCS (S2001) 4 iCoding Technology, Inc. Turbo Product Code Decoder, 160 Mbps , Compression Decoder 4 MPEG-4 Video Compression Encoder 4 MPEG-2 HD Decoder JPEG Encoder , . JPEG 2000 Encoder (JPEG2K_E) MVI DSP Algorithms The Xilinx CORE Generator software generates
Xilinx
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vhdl code for DES algorithm FLOATING POINT PROCESSOR TMSC6000 pulse compression radar fir filter matlab code LMS adaptive filter simulink model XILINX vhdl code REED SOLOMON encoder decoder LMS simulink

free vHDL code of median filter

Abstract: free verilog code of median filter . 41 JPEG Decoder & Encoder . 42 JPEG Decoder & Encoder , HDLC IIR Filter Library Image Processing Library Integer Divider JPEG Decoder and Encoder JPEG Decoder and Encoder Linear Feedback Shift Register Median Filter Library Multi-Standard ADPCM Numerically , . 55 Reed-Solomon Encoder
Altera
Original
free vHDL code of median filter verilog code for UART with BIST capability verilog code for 2D linear convolution filtering vhdl median filter 8051 interface ppi 8255 verilog median filter

ddr2 rad hard

Abstract: ip based cctv systems JPEG 2000 compliance Both lossless and lossy compression JPEG2K-E Error-resilient compression JPEG 2000 Encoder Core Headers syntax processing The JPEG2K-E core is a complete high performance JPEG2000 - ISO/IEC 15444-1 image compression solution targeted for video and high bandwidth image , required for successful implementation. The ASIC version includes: · VHDL RTL source code · Sophisticated , . Verification The core has been verified through extensive simulation and rigorous code coverage measurements
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ddr2 rad hard ip based cctv systems DWT image compression Altera jpeg2000 encoder vhdl code vhdl code for ddr sdram controller with AHB interface jpeg 2000

jpeg encoder vhdl code

Abstract: vhdl code for dwt transform JPEG 2000 compliance Both lossless and lossy compression JPEG2K-E Error-resilient compression JPEG 2000 Encoder Megafunction Headers syntax processing The JPEG2K-E megafunction is a complete high performance JPEG2000 - ISO/IEC 15444-1 image compression solution targeted for video and , . Verification The megafunction has been verified through extensive simulation and rigorous code coverage , compliant stream or file. · Place and route script · Post-synthesis EDIF netlist (VHDL RTL optional
Cast
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EP3C55 EP2S90 EP4SGX70 EP2AGX190 wavelet transform altera dwt image compression EP2AGX190-4

jpeg encoder vhdl code

Abstract: vhdl code for dwt transform JPEG 2000 compliance Both lossless and lossy compression JPEG2K-E Error-resilient compression JPEG 2000 Encoder Core Headers syntax processing The JPEG2K-E core is a complete high performance JPEG2000 - ISO/IEC 15444-1 image compression solution targeted for video and high bandwidth image , verified through extensive simulation and rigorous code coverage measurements. It has also been embedded , implementation. The Xilinx version includes: · Post-synthesis EDIF netlist (VHDL RTL optional) · Sophisticated
Cast
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wavelet transform FPGA

vhdl code for huffman decoding

Abstract: Motion JPEG Codec ) Code Control Variable Length Encoder (RLE) & (HUFF) JPEG Data Stream Generator (DSG) Test , QTMem iDCT Run Length Encoder HTMem Huffman Coder Figure 3: CS6190 JPEG Codec BLock Diagram , CS6190 TM Motion JPEG Codec Virtual Components for the Converging World The CS6190 Motion JPEG (M-JPEG) Codec is a highly integrated virtual component solution for leading-edge image , Quantization Run Length & Variable Length Coder Run Length & Variable Length Decoder JPEG Stream
Amphion Semiconductor
Original
SS jpeg codec verilog code for pixel converter vhdl code for transpose memory verilog code for huffman encoding DS6190
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