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SN74HCT273ANSRG4 Texas Instruments Octal D-Type Flip-Flops With Clear 20-SO visit Texas Instruments
CD40175BW Texas Instruments CMOS Quad D-Type Flip-Flop 0-WAFERSALE visit Texas Instruments
SN74HCT273ANSRE4 Texas Instruments Octal D-Type Flip-Flops With Clear 20-SO visit Texas Instruments
SN54HC273VTDG2 Texas Instruments Octal D-Type Flip Flops With - Clear, SN54HC273-DIE 0- visit Texas Instruments
SN74HCT273ANSR Texas Instruments Octal D-Type Flip-Flops With Clear 20-SO visit Texas Instruments
SN54HC273VTDG1 Texas Instruments Octal D-Type Flip Flops With - Clear, SN54HC273-DIE 0- visit Texas Instruments

jk flip flop to d flip flop conversion

Catalog Datasheet MFG & Type PDF Document Tags

asynchronous 4bit up down counter using jk flip flop

Abstract: counter 74168 with set/reset 8 (4) J-K flip flops 107 JKFF J-K flip flop 10 (3) 108 F211 J-K flip flop 9 (3) 109 JKFR J-K flip flop with reset 11 (3) 110 F212 J-K flip flop with reset 10 (3) 111 F213 J-K flip flop with set 10 (3) 112 JKF J-K flip flop with set/reset 13 (3) 113 F214 J-K flip flop with set , block name Logic function No. of unit cell Notes J-K flip flops 114 F215 J-K flip flop with reset 10 (3) 115 F216 J-K flip flop with set 10 (3) 116 JKF1 J-K flip flop with set/reset 11 (3) 117 F221 J-K
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74139 for bcd to excess 3 code

Abstract: design a bcd counter using jk flip flop ) J-K flip flops 107 JKFF J-K flip flop 10 (3) 108 F211 J-K flip flop 9 (3) 109 JKFR J-K flip flop with reset 11 (3) 110 F212 J-K flip flop with reset 10 (3) 111 F213 J-K flip flop with set 10 (3) 112 JKF J-K flip flop with set/reset 13 (3) 113 F214 J-K flip flop with set/reset 11 (3) (To be , flop with reset 10 (3) 115 F216 J-K flip flop with iit 10 (3) J-K 116 JKF1 J-K flip flop with set/reset 11 (3) flip flops 117 F221 J-K flip flop 9 (4) 118 F225 J-K flip flop with reset 10 (4) 119
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siemens master drive circuit diagram

Abstract: SR flip flop IC J-K flip flop J-K flip flop with scan J-K flip flop with clear J-K flip flop with clear/scan J-K flip flop with preset/clear J-K flip flop with preset/clear and scan Toggle flip flop with clear Toggle flip , database tape Product Idea/Logic Diagram/Test Patterns Conversion to Siemens macrocell family ' Logic , Primitive Cells (Cont.) Name Flip Flop FD1x FD1SX FD2x FD2Sx FD3x FD3SX FD4x FD4Sx FJK1X FJKISx FJK2X , source of Toshiba TC110G family Densities up to 129,000 raw gates Channelless " sea of gates
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siemens master drive circuit diagram SR flip flop IC toshiba tc110g jk flip flop to d flip flop conversion SC11C1 JK flip flop IC M33S004

priority encoder 74148

Abstract: priority encoder 74147 J-K flip flop 10 8 6.3/7.3 1*2) Note: »1 tpd = (tpLH + tPHL)/2, Vdd = 5V, Ta = 25°C, FO = 3,li = , ) Maximum No. of fan-out Delay time tpd (ns) (*1> Flip flop 1-53 JKFR J-K flip flop with reset _ 11 8 6.9/73 (*2> 1-54 JKF J-K flip flop with set/reset 13 8 7.1/9.1 (*2) 1-55 TFRE Toggle flip flow with , /7 2
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MSM72000 priority encoder 74148 priority encoder 74147 shift register 7495 msm7200 MSM7000 alu 74381 MSM70000 MSM71000 MSM73000 MSM74000 MSM75000

ic 74226

Abstract: jk flip flop 74103 AND RESET J-K FLIP FLOP J-K FLIP FLOP WITH SET J-K FLIP FLOP WITH RESET J-K FLIP FLOP WITH SET AND , N T h e R P 3 G 01 and R P 3 G 0 2 a r e A n a lo g /D ig ita l se m ic u s to m g a te a r r a y s , Resistor W ell Resistors Base Resistors Gate Number I/O Buffer po ssib le fo r th em to d rive d irectly , . · 3G 01-250 g a te s (eq u ivalen t to 2-input N A N D /N O R ). · 3G 02-400 g a te s 4- 4-to-16 decoder. · H igh b reak d ow n v o lta g e N P N tra n s is to r ( B V ceo). in p u t/o u tp u t b u
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ic 74226 jk flip flop 74103 ic D flip flop 7474 7471 rs flip flop 4011 flip flop IC 7400 SERIES list RP3G01 3W1X879 00GG71S

synchronous counter using 4 flip flip

Abstract: digital clock using gates conversion applications. Up to 9 decades can be cascaded with no speed degradation using the standard 9500 gates. With 95H00 gates a multidecade synchronous load counter to over 150 MHz can be built. Typical counter frequency is over 180 MHz or easy frequency increase to over 250 MHz with the 95H29 JK Flip Flop , counting flip flop. Terminal count is generated internally in a manner that allows synchronous loading at , emitter dotting to achieve the logical functions within approximately one gate delay. The uses are for
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95H10 synchronous counter using 4 flip flip digital clock using gates digital clock using logic gates synchronous counter using flip flip BCD 8421 ECL Decade Counter

function of latch ic 74373

Abstract: full adder using ic 74138 tristate bus driver-2 Internal tristate bus driver-3 Bus hold-1 D-type flip flop with reset and L S S D D-type flip flop with set/reset and L S S D J-K flip flop with reset and LSSD J-K flip flop with set , reset D -type flip flo p w ith set/reset J-K flip flo p 8 8 1-51 DF 9 8 1-52 JK , LDF J-K flip flop with reset _ J-K flip flop w ith set/reset Toggle flip flow with enable/reset Toggle flip flop with enable/set/reset Toggle flip flop with reset 2-input N A N D driver gate 2-input A
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function of latch ic 74373 full adder using ic 74138 pins and their function in ic 74163 encoder IC 74147 74541 buffer 74373 cmos dual s-r latch MSM71000/72000/73000/74000 MSIW71000

jk flip flop to d flip flop conversion with diagram

Abstract: Atmel CPLD In-System Program macrocell. (This feature is automatically implemented by the fitter software). In addition to D, T, JK and SR operation, the flip flop can also be configured as a flowthrough latch. In this mode, data passes , Operation Up To 100 MHz ­ Enhanced Routing Resources Flexible Logic Macrocell ­ D/T/Latch Configurable , . Under software control, up to 40 of these signals can be selected as inputs to the Logic Block. Flip Flop The ATF1516AS's flip flop has very flexible data and control functions. The data input can come
Atmel
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ATF1516AS-10QC160 ATF1516AS-10UC192 ATF1516AS-10QHC208 ATF1516AS-15QC160 ATF1516AS-15UC192 ATF1516AS-15QHC208 jk flip flop to d flip flop conversion with diagram Atmel CPLD In-System Program ATF1516AS-15Q160 ATF1516AS/L 208QH

9316DM

Abstract: 93S16 Parallel Data (Pn) inputs to be loaded into the flip -flop s on the next rising edge of CP. W ith PE and MR , all flip -flop s are driven in parallel through a clock buffer. Thus all changes of the Q outputs , ) contain masterslave flip flops which are "next-state catch ing" because of the JK feedback. This means that when CP is LOW, inform ation that w ould change the state of a flip -flop , whether from the , u n t b e y o n d 9. If p re s e t to s ta te 1 0 ,1 1 ,1 2 ,1 3 ,1 4 o r 15, it w ill retu rn to
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93S16 9316PC 9316DM 93L16DM 93XX TTL logic 9316V 9310PC 93L10PC 93L16PC 93S10PC

1LB553

Abstract: Rauland ETS-003 EDITION 1985 Revised June 1985 COMPILED AND PUBLISHED BY SEM IC O N IN D EXES LIMITED THE , VOLUME 3 D IG ITA L & ANALOGUE I.C. TH E SEMICON INDEXES VOLUME 3 5th E D I T I O N 1985 Revised June 1985 IN T E R N A T IO N A L INTEGRATED CIRCUITS IN D E X CONTENTS SECTION , DIAGRAMS, OUTLINES, TTL SERIES 54/7400 ABBREVIATIONS COMPILED A N D PUBLISHED BY SEMICON INDEXES L IM IT E D , PO BOX 31, FLEET, HAMPSHIRE GU13 9DA, U.K. TELEPHONE: FLE ET (025 14) 28526 U D C 6 2 1 .3
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1LB553 Rauland ETS-003 Silec Semiconductors 4057A transistor sr52 logos 4012B IEC179 TDA1510 TDA1510A

"XOR Gate"

Abstract: d-latch implemented by the fitter software). In addition to D, T, JK and SR operation, the flip flop can also be , is also used to emulate T- and JK-type flip-flops. Flip Flop The ATF1516AS's flip flop has very , Operation Up To 100 MHz ­ Enhanced Routing Resources Flexible Logic Macrocell ­ D/T/Latch Configurable , product term. The flip flop changes state on the clock's rising edge. When the GCK signal is used as 4 , ignored. The flip flop's asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a
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ATF1516ASL d-latch JK flip flop atmel 160 pin internal circuitry for sr flip flop R S Flip Flop Latch 0994C
Abstract: minimization of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops. Flip Flop The ATF1516AS's flip flop has very flexible data and control functions. The data input can come from either the , feature is automatically implemented by the fitter software). In addition to D, T, JK and SR operation, the flip flop can also be configured as a flowthrough latch. In this mode, data passes through when , Resources Flexible Logic Macrocell ­ D/T/Latch Configurable Flip Flops ­ Global and Individual Register Atmel
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0994B

IC 3-8 decoder 74138 pin diagram

Abstract: binary to gray code conversion using ic 74157 /Reset 8 4.8/5.6(2) I-52 JKFF J-K Flip Flop 8 4.6/5.5(2) 1-53 JKFR J-K Flip Flop with Reset 8 4.7/5.7(2) I-54 JKF J-K Flip Flop with Set/Reset 8 4.8/6.1(2) 224 is Material Copyrighted By Its , D-type Flip Flop with Set/Reset and LSSD 8 5.6/4.8(2) 1-68 UKR J-K Flip Flop with Reset and LSSD 8 5.7/4.7(2) 1-69 UKF J-K Flip Flop with Set/Reset and LSSD 8 6.1/4.8(2) Note: 1) tpd = (tplh + tphl)/2 , Invert Driver-3 70 2.7 Flip-flop 1-48 DLT D-Type Latch with Reset 8 3.6 1-49 DFF D-Type Flip Flop 8
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IC 3-8 decoder 74138 pin diagram binary to gray code conversion using ic 74157 Multiplexer IC 74151 16 bit odd even parity checker using two IC 74180 7444 series Excess-3-gray code to Decimal decoder binary to gray code conversion using ic 74139 MSM91H000 72MS40
Abstract: the clock is static, the JK inputs do not effect the output. The output states of the flip flop change , pin assignment, see the Pin Conversion Tables on page 6 -1 1 . MOTOROLA D Motorola. Inc. 1996 2 , MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual J-K Master-Slave Flip-Flop The MC10H135 is a dual J , Ceramic Symbol Vee V| fout ta J1 7 Rating -8 .0 to 0 o to V e e 50 100 0 to +75 -5 5 to +150 -5 5 to +165 Unit Kl 6 Vdc Vdc mA =C C C R1 4 VCC1 = P IN 1 p ,N 8 C 9 VCC2 = PIN -
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10K-C
Abstract: . A common clock is provided with separate J-K inputs. When the clock is static, the JK inputs do not effect the output. The output states of the flip flop change on the positive transition of the clock. · , MC10H135 Dual J-K Master-Slave Flip-Flop The MC10H135 is a dual J-K master-slave flip-flop. The , MC10H135L AWLYYWW VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 Q2 Q2 15 14 N.D. = Not Defined CLOCK J-K , Year = Work Week *Output states change on positive transition of clock for J-K input condition ON Semiconductor
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CDIP-16 PDIP-16 PLCC-20 10H135 MC10H135P MC10H135F
Abstract: . A common clock is provided with separate J­K inputs. When the clock is static, the JK inputs do not effect the output. The output states of the flip flop change on the positive transition of the clock. · , MC10H135 Dual J-K Master-Slave Flip-Flop The MC10H135 is a dual J­K master­slave flip­flop. The , MC10H135L AWLYYWW VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 Q2 Q2 15 14 N.D. = Not Defined CLOCK J­K , Year = Work Week *Output states change on positive transition of clock for J­K input condition ON Semiconductor
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Abstract: INPUT NOR GATE tpLH DF 4 DFRS 6 MASTER SLAVE D - TYPE FLIP FLOP MASTER SLAVE D - , Set and Reset M3DF M3DFRS J K Flip Flop J K Flip Flop with Set and Reset JBAR - K Flip Flop JBAR - K Flip Flop withSet and Reset Buffered J-K Flip-Flop Buffered J-K Flip-Flop with Set and Reset , LARGE 2 INPUT NAND Ã"ATE + 2 INPUT NOR MASTER SLAVEâ' D-TYFF" FLIP FLOP ~CW05~TNPUT~BUFFER TBC , (Supersedes December 1988 Edition) This advanced family o f gate arrays uses many innovative techniques to -
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CLA60000 CLA6Q000

IC 3-8 decoder 74138 pin diagram

Abstract: full adder using ic 74138 Prop. Delay ·P (NAND2) 4 input NOR Prop. Delay tp (NOR4) D Flip Flop with R Prop. Delay tp (DFFRNR1 , following conditions : Fan out = 3 + 1000 nm metal interconnect. (3) D Flip Flop (with R) propagation delay , peripheral cell can be connected to an external RC. ON C H IP T E S T M O D E The special test mode permits , F IG U R E 6 : P r o p a g a tio n D e la y F a c to r V e r s u s T o ta l D o s e . ' Due to the , an exam ple the diagram of a DFFNR1, Macro cell (D Flip-Flop with Reset) as it appears to the routing
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circuit diagram for IC 7483 full adder ttl ic 7485 0850R 7483 4 bit binary full adder circuit diagram for 7483 transistor KD 617 ic 7442 encoder 0850RT 1300RT 2000RT 2700RT 3200RT 4000RT

mc10h135

Abstract: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual J-K Master-Slave Flip-Flop The MC10H135 is a dual J­K master­slave flip­flop. The device is provided with an asynchronous set(s) and reset(R). These set and reset inputs overide the clock. A common clock is provided with separate J­K inputs. When the clock is static, the JK inputs do not effect the output. The output states of the flip flop change on , . DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N
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MC10H135FN MC10H135FNR2 MC10H135M MC10H135ML1

Fairchild 9300

Abstract: U6B930059X degree of general usefulness are described below: 1. A JK input is provided to the first flip flop in the , Enable input low the element appears as four common clocked D flip flops. When the Parallel Enable is , the next state of the flip flops occurs after the low to high transition of the clock input. 4. An , enable is generated to load the next parallel word for conversion at the correct time. 3-85 FAIRCHILD , inputs to first stage Asynchronous common reset Typical power dissipation of 300 mW The input/output
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Fairchild 9300 U6B930059X design sequential circuit of clocked RS flip flop U6B930051X 95IND 9300 equivalent U6B9300XXX
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