NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Freescale Semiconductor Data Sheet: Advance Information Document Number: IMX53CEC IMX53CEC Rev. 3, 7/2011 MCIMX53xD i.MX53xD Applications Processors for Consumer Products Package Information Plastic Package Case TEPBGA-2 19 x 19 mm, 0.8 mm pitch Case FC-PBGA PoP 12 x 12 mm Ordering Information See Table 1 on page 3 1 Introduction The i.MX53xD multimedia application processor is Freescale Semiconductor's latest addition to a growing family of multimedia-focused products o ... | Original |
204 pages, |
MCIMX535DVV1C eMMC IMX53CEC Jedec lpddr2 lpddr2 spec samsung lpddr2 Mobile RAM tv-out flexcan2 lpddr2 pcb design eMMC 4.4 LPDDR2 PoP MCIMX538DZK1C Samsung eMMC 4.41 emmc DDR pcb layout IMX53CEC abstract |
| Abstract: SSTL-15 SSTL-15 Class II - (3) 1.5 2.5 0.75 0.75 SSTL-15 SSTL-15 JESD79-3D (3) 1.5 2.5 , 2.5 - 0.60 Differential SSTL-15 SSTL-15 JESD79-3D (3) 1.5 2.5 - (4 ... | Original |
34 pages, |
Datasheet LPDDR2 LPDDR2 pin information LPDDR2 SDRAM mini-lvds source driver resistor 240 5sgx SSTL-125 SSTL-18 SSTL135 SSTL-15 SSTL-12 lpddr2 DQ calibration DDR3L datasheet abstract |
| Abstract: Stratix V Device Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 10.0 © July 2010 Copyright © 2010Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other cou ... | Original |
503 pages, |
Chapter 3 Synchronization verilog code 8 bit LFSR DDR3L SFP sgmii altera jesd79-3d Datasheet LPDDR2 SDRAM gearbox rev WD 969 tsmc 28nm standard io library QSFP CONNECTOR verilog code for max1619 lpddr2 DQ calibration lpddr2 phy datasheet abstract |
| Abstract: Electronic Systems, 11(2):306-324, 2006. [3] JEDEC DDR3 SDRAM Standard, JESD79-3D, September 2009. [4] CIO ... | Original |
18 pages, |
micron ddr3 jesd79-3d CP-01061-1 CP-01061-1 abstract |
| Abstract: SSTL-15 SSTL-15 Class II - (3) 1.5 2.5 0.75 0.75 SSTL-15 SSTL-15 JESD79-3D (3) 1.5 2.5 , 2.5 - 0.60 Differential SSTL-15 SSTL-15 JESD79-3D (3) 1.5 2.5 - (4 ... | Original |
96 pages, |
QDR pcb layout UniPHY sstl15 SSTL-18 SSTL-15 lpddr2 pcb design lpddr2 pcb layout DDR3U DDR3L Datasheet LPDDR2 Dual LPDDR2 HSUL-12 lpddr2 DQ calibration lpddr2 phy datasheet abstract |
| Abstract: Stratix V Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V1-1.0 Copyright © 2010Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service ... | Original |
300 pages, |
lpddr2 pcb layout Dual LPDDR2 DDR3U UniPHY lpddr2 SV51005-1 SV51012-1 "Stratix IV" Package layout footprint DDR3L lpddr2 tutorial Datasheet LPDDR2 SDRAM lpddr2 DQ calibration lpddr2 phy lpddr2 datasheet datasheet abstract |
| Abstract: TS3DDR3812 TS3DDR3812 SCDS314A SCDS314A FEBRUARY 2011 REVISED MARCH 2011 www.ti.com 12-Channel, 1:2 MUX/DEMUX Switch for DDR3 Applications Check for Samples: TS3DDR3812 TS3DDR3812 FEATURES APPLICATIONS · · · · · · · · · · · B1 RUA PACKAGE (TOP VIEW) C1 · DDR3 Signal Switching DIMM Modules Notebook/Desktop PCs Servers B0 · · · · Compatible with DDR3 SDRAM Standard (JESD79-3D) Wide Bandwidth of 1.675 GHz Low Propagation Delay (tpd = 40 ps Typ) Low Bit-to-Bit Skew (tsk(o ... | Original |
16 pages, |
TS3DDR3812 SL812 JESD22 C101 A114B jesd79-3d SCDS314A TS3DDR3812 abstract |
| Abstract: Stratix V Device Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 10.1 © January 2011 Copyright © 2011Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other ... | Original |
516 pages, |
Altera Cyclone III lpddr2 tutorial M20K SFP sgmii altera 10G SFP pcie gen3 QSFP CONNECTOR verilog code 8 bit LFSR in scrambler verilog code 16 bit LFSR UniPHY lpddr2 DDR3L SV51005-1 KF40-F1517 datasheet abstract |
| Abstract: Spartan-6 FPGA Memory Controller User Guide UG388 UG388 (v2.1) March 4, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, ... | Original |
64 pages, |
MT47H32M16xx-37E UG388 MT47H32M16 UG416 XC6SL XC6SLX25 XC6SLX75 TQG144 DSP48A1 spartan6 datasheet MT41J256M8xx-187E JESD209A mcb DATASHEET MT41K128 UG388 abstract |
| Abstract: Spartan-6 FPGA Memory Controller User Guide UG388 UG388 (v2.3) August 9, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise ... | Original |
66 pages, |
XC6SLX75T DDR3 DRAM layout XC6SLX75 CSG484 MT41K128M8 DDR3 layout TI CPG196 mcb technical detail elpida DDR2 layout techniques XCN10024 JESD209A spartan6 jtag instruction mcb DATASHEET xc6slx150t jtag UG388 UG388 abstract |