NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: programmable, absolute delay primitive called IODELAY. IODELAYs are a delay-chain of 64 taps with an average , input of the inverter, which feeds the initial IODELAY. The second and any successive IODELAYs have , www.xilinx.com 1 Design Description Design Description The IODELAY-based oscillator is extended to , a second IODELAY set to the maximum delay with an adjusted IODELAY. With an estimated routing delay , connecting two or more IODELAYs in series, and having one inverter in the chain. The first IODELAY is ... | Original |
17 pages, |
XAPP872 binary multiplier Vhdl code DS202 ML505 ML523 UG190 4 bit binary multiplier Vhdl code Virtex-5LX50TC-1 vhdl code for multiplexer 32 BIT BINARY knx usb vhdl code for 16 BIT BINARY DIVIDER vhdl code for 16 prbs generator vhdl code for FFT 32 point XAPP872 abstract |
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| Abstract: Target - Figure 5 Routing Connections ILOGIC ISERDES IODELAY OLOGIC OSERDES P_PAD IBUFDS_DIFF_OUT O OB Routing Connections ILOGIC ISERDES IODELAY OLOGIC OSERDES IB I N_PAD , www.xilinx.com 4 R Virtex-4 and Virtex-5 FPGA I/O Architecture IDELAY, IODELAY, and ISERDES Virtex-4 devices only have IDELAY (no IODELAY), which is integrated in ISERDES as shown in Figure 6. As such, IODELAY in Figure 5 is replaced by IDELAY in terms of Virtex-4 devices. Virtex-5 devices have ... | Original |
30 pages, |
fpga frame by vhdl examples interface of ADC to UART in VHDL ADS6445 ADS527x ML555 CLK180 UCF virtex-4 vhdl code for deserializer Virtex-4 User Guide virtex 5 ddr data path IDELAY OSERDES 24 BIT adc spi FPGA datasheet abstract |
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| Abstract: testbench communicates statistics like IODELAY tap count of the clock channel and link status etc. to the , ISERDES and IODELAY blocks. BUS_ALIGN_MACHINE Performs the clock/data alignment by varying the delay , [15] 4 RXCLKDIV(1) RXCLK(1) IODELAY TRAINING_DONE ICE INC ISERDES_CLK BUFIO Bus , module in Figure 8 is shown as having a dotted line connection to IODELAY (this connection is not , to calibrate the IODELAY block in the path of the clock channel. The delayed output of the IODELAY ... | Original |
34 pages, |
XC6VLX240T PLL-02 PRBS23 ISERDES SDR receiver testbench of a transmitter in verilog UCD9240 VIRTEX-6 XAPP880 ML605 iodelay samtec QSE XAPP855 example ml605 XAPP880 abstract |
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| Abstract: SRAM two-word burst design. REFCLK_FREQ IODELAY_GRP = 200, // Iodelay Clock Frequency = "IODELAY_MIG", // It is associated to a set of IODELAYs with // an IDELAYCTRL that have same IODELAY , "OFF", // Input buffer low power mode IODELAY_HP_MODE = "ON", // IODELAY High Performance Mode TCQ , frequency. X-Ref Target - Figure 2 IODELAYCTRL infrastructure user_top QDR II SRAM Model tb_top ... | Original |
7 pages, |
xilinx mig CY7C1412BV18 iodelay ISERDES K7R321882C ML662 OSERDES UG086 VIRTEX-6 XAPP886 ug406 0743A XAPP886 abstract |
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| Abstract: all ISERDES and IODELAY blocks. RT_WINDOW_MONITOR BIT_ALIGN_MACHINE Adjusts clock/data , R DDR Receiver 200 MHz Source RX_IDELAYCTRL Resource Sharing Control IODELAY , ] 4 [5:0] 6 Slave (Monitor) 6 IODELAY ISERDES_CH_01 Q D LVDS_25_DIFFOUT , ) 6 RXCLKDIV 6 6 6 Real-Time Window Monitoring Circuitry Q Mon to RT IODELAY , BUFIO IODELAY LVDS_25 To CH 15 Fixed to Tap 0 BUFR (÷3) CLOCK_RX_P CLOCK_RX_N (1 ... | Original |
43 pages, |
XAPP860 XAPP855 ML550 DS202 OSERDES ISERDES spartan 6 ISERDES datasheet abstract |
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| Abstract: deserialization. Contains instantiations of all ISERDES and IODELAY blocks. BIT_ALIGN_MACHINE Performs the , 4 8 IODELAY LVDS_25 [7:2] DATA_RX_P[00] Master DATA_RX_N[00] [1:0] Slave Q D ISERDES_CH_01 8 IODELAY LVDS_25 [15:10] DATA_RX_P[01] Master DATA_RX_N[01] [9:8] Slave RXCLKDIV 8 8 DATA_TO_ MACHINE START_ ALIGN ISERDES_CH_15 IODELAY LVDS_25 [127:122 , Slave RXCLK(1) To CH 00 To CH 01 INC, ICE, BITSLIP BITSLIP 3 BUFIO IODELAY LVDS_25 ... | Original |
43 pages, |
XAPP860 PRBS23 ML550 OSERDES XAPP855 ISERDES datasheet abstract |
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| Abstract: I/O pair with IODELAY, ISERDES, and OSERDES. In this application note, the OSERDES block is used to , Target - Figure 4 ILOGIC ISERDES Routing Connections Made by ISE Software IOB IODELAY , Structure www.xilinx.com 3 R I/O Architecture of Virtex-5 FPGA OSERDES and IODELAY OSERDES , shifted out, thus generating a clock pattern. OSERDES can be used in combination with the IODELAY , To Routing Multiplexer in the FPGA DATAOUT IODELAY T ODATAIN SHIFTOUT1 SHIFTOUT2 D1 ... | Original |
16 pages, |
MB86065 iodelay MB86064 fpga cdma ip vhdl examples ML550 ML555 DAC spartan 3 RAMB36 VIRTEX-5 fpga radar XAPP873 DAC FPGA START KIT OSERDES datasheet abstract |
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| Abstract: with IODELAY, ISERDES, and OSERDES. In this application note, the OSERDES block is used to shift data , Figure 4 ILOGIC ISERDES Routing Connections Made by ISE Software IOB IODELAY OLOGIC , structure www.xilinx.com 3 R I/O Architecture of Virtex-5 FPGA OSERDES and IODELAY OSERDES , shifted out, thus generating a clock pattern. OSERDES can be used in combination with the IODELAY , To Routing Multiplexer in the FPGA DATAOUT IODELAY T ODATAIN SHIFTOUT1 SHIFTOUT2 D1 ... | Original |
16 pages, |
XAPP873 RAMB36 ML555 ML550 MB86065 MB86064 OSERDES datasheet abstract |
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| Abstract: deserialization. Contains instantiations of all ISERDES and IODELAY blocks. BUS_ALIGN_MACHINE Performs the , IODELAY BUFR (÷4) INC Bus Align Machine ICE ISERDES_CLK RXCLKDIV(1) RXCLK LVDS_25 , , IDELAYCTRL is required to calibrate the IODELAY blocks in the path of each data channel. A single IDELAYCTRL , IODELAY to increment or decrement the delay in the clock path by a fixed amount of ~75 ps (if a 200 MHz , in a Virtex-5 device. These figures exclude the counter used to track the IODELAY settings on the ... | Original |
33 pages, |
XAPP860 XAPP856 XAPP855 ML550 FIFO36 OSERDES ISERDES datasheet abstract |
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| Abstract: introduced by delaying data through the IODELAY. The worst-case jitter value is calculated using the , IODELAY Read Data Falling Q2 Read Data Rising FPGA Clock CLK OCLK CLKDIV Data delay value based on calibration Delayed CQ CQ IODELAY BUFIO X852_04_030907 Figure 10: Read , available IODELAY elements in all the I/Os in the Virtex-5 device. The IODELAY elements delay the input , bank in Virtex-5 devices and help to maintain the resolution of the IODELAY elements. Calibration ... | Original |
18 pages, |
CY7C1520JV18-300BZXC DWH-01 mig ddr virtex K7R643684M-FC30 DWH-10 DWH-20 DWL-11 XAPP853 iodelay ISERDES ML561 DWH-11 FIFO36 datasheet abstract |
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| , 0x8B, 0x89, 0x8A }; //* //* IoDelay //* int IoDelay(void) { int n; n = 0; n += 1; return n Addr; // mask the DMA channel outportb (MaskReg[ChannelNum], (U8)(SET_MASK_BIT | (ChannelNum & 3); IoDelay (); outportb (ClearFF[ChannelNum], 0); IoDelay (); // set up buffer address for DMA controller outportb (BaseAddr[ChannelNum], (U8)(SimpleAddr & 0xFF); /* low byte */ IoDelay www.datasheetarchive.com/download/42595863-870357ZC/source.zip (DMA.C) |
Texas Instruments | 08/02/1999 | 177.54 Kb | ZIP | source.zip |
| , 0x8B, 0x89, 0x8A }; //* //* IoDelay //* int IoDelay(void) { int n; n = 0; n += 1; return n Addr; // mask the DMA channel outportb (MaskReg[ChannelNum], (U8)(SET_MASK_BIT | (ChannelNum & 3); IoDelay (); outportb (ClearFF[ChannelNum], 0); IoDelay (); // set up buffer address for DMA controller outportb (BaseAddr[ChannelNum], (U8)(SimpleAddr & 0xFF); /* low byte */ IoDelay www.datasheetarchive.com/download/45576173-885776ZC/source.zip (DMA.C) |
Texas Instruments | 16/01/2000 | 177.54 Kb | ZIP | source.zip |
| , 0x8B, 0x89, 0x8A }; //* //* IoDelay //* int IoDelay(void) { int n; n = 0; n += 1; return n Addr; // mask the DMA channel outportb (MaskReg[ChannelNum], (U8)(SET_MASK_BIT | (ChannelNum & 3); IoDelay (); outportb (ClearFF[ChannelNum], 0); IoDelay (); // set up buffer address for DMA controller outportb (BaseAddr[ChannelNum], (U8)(SimpleAddr & 0xFF); /* low byte */ IoDelay www.datasheetarchive.com/download/2496607-877808ZC/source.zip (DMA.C) |
Texas Instruments | 17/01/2000 | 177.54 Kb | ZIP | source.zip |
| out dx,al add dl,ACE_LSR-ACE_IER ; -> line status register IO_Delay call Wait _EFIFO OR ACE_CRFIFO OR ACE_CTFIFO @@: sub dl,ACE_LSR-ACE_FCR out dx,al IO_Delay call MaskIRQ add dl,ACE_MCR-ACE_FCR ; -> Modem control reg in al,dx IO_Delay mov ah, al or al, ACE_LOOP ; turn on loopback out dx, al IO_Delay sub dl, ACE_MCR-ACE_THR xor al, al out dx, al ; output a NULL to generate an int IO_Delay add dl, ACE_LSR-ACE_THR call WaitForXmitEmpty mov al www.datasheetarchive.com/download/42595863-870357ZC/source.zip (SERUTIL.ASM) |
Texas Instruments | 08/02/1999 | 177.54 Kb | ZIP | source.zip |
| register IO_Delay mov ah,100 Terminate20: dec ah ; sort of timeout jz Terminate30 ; On _EFIFO OR ACE_CRFIFO OR ACE_CTFIFO @@: sub dl,ACE_LSR-ACE_FCR out dx,al IO_Delay call MaskIRQ add dl,ACE_MCR-ACE_FCR ; -> Modem control reg in al,dx IO_Delay mov ah,al or al,ACE_LOOP ; turn on loopback out dx,al IO_Delay sub dl,ACE_MCR-ACE_THR xor al,al ; out dx,al ; output a NULL to generate an int IO_Delay add dl,ACE_LSR-ACE_THR push eax ; AH MUST be saved mov ah www.datasheetarchive.com/download/42595863-870357ZC/source.zip (SERUTI31.ASM) |
Texas Instruments | 08/02/1999 | 177.54 Kb | ZIP | source.zip |
| out dx,al add dl,ACE_LSR-ACE_IER ; -> line status register IO_Delay call Wait _EFIFO OR ACE_CRFIFO OR ACE_CTFIFO @@: sub dl,ACE_LSR-ACE_FCR out dx,al IO_Delay call MaskIRQ add dl,ACE_MCR-ACE_FCR ; -> Modem control reg in al,dx IO_Delay mov ah, al or al, ACE_LOOP ; turn on loopback out dx, al IO_Delay sub dl, ACE_MCR-ACE_THR xor al, al out dx, al ; output a NULL to generate an int IO_Delay add dl, ACE_LSR-ACE_THR call WaitForXmitEmpty mov al www.datasheetarchive.com/download/45576173-885776ZC/source.zip (SERUTIL.ASM) |
Texas Instruments | 16/01/2000 | 177.54 Kb | ZIP | source.zip |
| register IO_Delay mov ah,100 Terminate20: dec ah ; sort of timeout jz Terminate30 ; On _EFIFO OR ACE_CRFIFO OR ACE_CTFIFO @@: sub dl,ACE_LSR-ACE_FCR out dx,al IO_Delay call MaskIRQ add dl,ACE_MCR-ACE_FCR ; -> Modem control reg in al,dx IO_Delay mov ah,al or al,ACE_LOOP ; turn on loopback out dx,al IO_Delay sub dl,ACE_MCR-ACE_THR xor al,al ; out dx,al ; output a NULL to generate an int IO_Delay add dl,ACE_LSR-ACE_THR push eax ; AH MUST be saved mov ah www.datasheetarchive.com/download/45576173-885776ZC/source.zip (SERUTI31.ASM) |
Texas Instruments | 16/01/2000 | 177.54 Kb | ZIP | source.zip |
| out dx,al add dl,ACE_LSR-ACE_IER ; -> line status register IO_Delay call Wait _EFIFO OR ACE_CRFIFO OR ACE_CTFIFO @@: sub dl,ACE_LSR-ACE_FCR out dx,al IO_Delay call MaskIRQ add dl,ACE_MCR-ACE_FCR ; -> Modem control reg in al,dx IO_Delay mov ah, al or al, ACE_LOOP ; turn on loopback out dx, al IO_Delay sub dl, ACE_MCR-ACE_THR xor al, al out dx, al ; output a NULL to generate an int IO_Delay add dl, ACE_LSR-ACE_THR call WaitForXmitEmpty mov al www.datasheetarchive.com/download/2496607-877808ZC/source.zip (SERUTIL.ASM) |
Texas Instruments | 17/01/2000 | 177.54 Kb | ZIP | source.zip |
| register IO_Delay mov ah,100 Terminate20: dec ah ; sort of timeout jz Terminate30 ; On _EFIFO OR ACE_CRFIFO OR ACE_CTFIFO @@: sub dl,ACE_LSR-ACE_FCR out dx,al IO_Delay call MaskIRQ add dl,ACE_MCR-ACE_FCR ; -> Modem control reg in al,dx IO_Delay mov ah,al or al,ACE_LOOP ; turn on loopback out dx,al IO_Delay sub dl,ACE_MCR-ACE_THR xor al,al ; out dx,al ; output a NULL to generate an int IO_Delay add dl,ACE_LSR-ACE_THR push eax ; AH MUST be saved mov ah www.datasheetarchive.com/download/2496607-877808ZC/source.zip (SERUTI31.ASM) |
Texas Instruments | 17/01/2000 | 177.54 Kb | ZIP | source.zip |
| out dx,al add dl,ACE_LSR-ACE_IER ; -> line status register IO_Delay call Wait _EFIFO OR ACE_CRFIFO OR ACE_CTFIFO @@: sub dl,ACE_LSR-ACE_FCR out dx,al IO_Delay call MaskIRQ add dl,ACE_MCR-ACE_FCR ; -> Modem control reg in al,dx IO_Delay mov ah, al or al, ACE_LOOP ; turn on loopback out dx, al IO_Delay sub dl, ACE_MCR-ACE_THR xor al, al out dx, al ; output a NULL to generate an int IO_Delay add dl, ACE_LSR-ACE_THR call WaitForXmitEmpty mov al www.datasheetarchive.com/download/36573047-7873ZC/ck001700.zip (Serutil.asm) |
AMD | 22/03/1999 | 282.92 Kb | ZIP | ck001700.zip |