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interleaver Datasheet

Part Manufacturer Description PDF Type
Interleaver-De-interleaver Lattice Semiconductor Interleaver-De-interleaver Data Sheet Original

interleaver

Catalog Datasheet MFG & Type PDF Document Tags

vhdl code for interleaver

Abstract: vhdl code for block interleaver de-interleaving. The number of branches is called the depth of the interleaver. The first branch has no delay , complementary to the interleaver. That is, once a symbol enters the branch of the deinterleaver, it leaves the , Convolutional Specifies the number of branches used by the interleaver. Direction Block Convolutional , the interleaver. write_add[] Block Convolutional External Write address bus output , , symbols. span The numbers of rows used by an interleaver. symbol An individual data bit; a codeword is
Altera
Original
vhdl code for interleaver vhdl code for block interleaver design for block interleaver deinterleaver RE35 umts turbo encoder vhdl code download REED SOLOMON

DVB-T Schematic set top box

Abstract: VIRTEX7-XC7VX485T . Forney Convolutional Operation Figure 1 shows the operation of a Forney Convolutional Interleaver. The , that the equation represents a block interleaver. It might be necessary to evaluate the equation for a , LogiCORE IP Interleaver/De-Interleaver v7.0 DS861 October 19, 2011 Product Specification LogiCORE , -7, ArtixTM-7, ZynqTM-7000, Spartan-6, Virtex-6 AXI4 Introduction The interleaver/de-interleaver core is , convolutional interleavers, for example, ITU J.83 Annex B. Provided with Core Documentation Design Files
Xilinx
Original
DVB-T Schematic set top box VIRTEX7-XC7VX485T Radix-10 forney interleaver by vhdl vhdl code for bit interleaver TM-7000 CDMA2000

interleaver

Abstract: "Single-Port RAM" Interleaver/Deinterleaver MegaCore Function Solution Brief 42 June 1999, ver. 1 Target , ://www.altera.com Tel. (408) 544-7000 Interleavers/deinterleavers are standard digital signal processing (DSP , use interleavers/deinterleavers to enhance the performance of forward error correction (FEC) systems. Symbol interleavers/deinterleavers can mitigate the effects of burst noise. Typically, these functions , codewords. The Altera interleaver/deinterleaver MegaCoreTM function uses internal or external single-port
Altera
Original
interleaver design for convolutional interleaver deinterleaver Convolutional block convolutional interleaving

vhdl code for interleaver

Abstract: vhdl code for block interleaver interleaver.book i Symbol Interleaver/Deinterleaver MegaCore Function Version 1.2 2000 8 interleaver.book ii Symbol Interleaver/Deinterleaver MegaCore Function , August , -MHz Altera Corporation Altera Corporation 7 7 interleaver.book 8 Symbol Interleaver , C1 B1 C1 Altera Corporation interleaver.book 9 Symbol Interleaver/Deinterleaver , Block Interleaver din dout 10 Altera Corporation interleaver.book 11
Altera
Original
VHDL code for interleaver block in turbo code convolutional interleaver code for interleaver fec convolutional encoder interleaving

convolutional interleaver

Abstract: Convolutional Convolutional Interleaver Megafunction Solution Brief 16 Target Applications: Digital Signal , www.ktechtelecom.com March 1997, ver. 1 s s s s Implements a convolutional interleaver function Accepts a , cable modems General Description The convolutional interleaver megafunction implements a , megafunction requires an external dual-port RAM. A convolutional interleaver megafunction that uses external , shows a functional block diagram of the convolutional interleaver megafunction. Figure 1
Altera
Original
EPF10K10 EPF8452A EPM9320 EPF10K100 interleaving 8000MAXMAX

turbo encoder model simulink

Abstract: vhdl code for interleaver , or parity, symbols. span The numbers of rows used by an interleaver. symbol An individual data bit , supports AHDL, VHDL, and Verilog HDL. 7. Type the name of the output file, e.g., interleaver. Figure , depth of the interleaver. The first branch has no delay. Each consecutive branch introduces an , delays introduced at each branch are complementary to the interleaver. That is, once a symbol enters the , Symbol Interleaver/ Deinterleaver MegaCore Function User Guide 101 Innovation Drive San Jose
Altera
Original
turbo encoder model simulink umts simulink matlab umts simulink block interleaver in modelsim turbo encoder circuit, VHDL code timing interleaver

Interleaver-De-interleaver

Abstract: interleaver interleaver. It indicates that the input source can again start feeding the data. This signal can be used for , increase of R up to (N-1)*R, where R is the depth of the interleaver. The value of R is set by the , constructed similar to the interleaver, but its branches are arranged opposite to those of the interleaver. , that the original data is correctly restored from the interleaver's output data. De-interleaving of the , Interleaver/De-interleaver IP Core December 2003 IP Data Sheet Full Handshake Capability
Lattice Semiconductor
Original
LFX125B-04F256C LFX125B04F256C Convolutional Puncturing Pattern

vhdl code for interleaver

Abstract: vhdl code for block interleaver data in J (I-1)J Block Interleaver/Deinterleaver Block interleavers/deinterleavers use , Symbol Interleaver/Deinterleaver MegaCore Function Solution Brief 42 September 2000, ver. 2.0 , symbol interleaver/deinterleavers to reduce spurious noise that can corrupt data. The Altera® symbol interleaver/deinterleaver MegaCore® function supports both a continuous mode and a discrete mode, making it compatible with any type of Reed-Solomon function. Also, the symbol interleaver/deinterleaver improves the
Altera
Original
ahdl code for deinterleaver PLSM Convolutional Encoder

Block Interleaver

Abstract: depth of the interleaver. The value of R is set by the branch_length parameter. The input and output , interleaver, but its branches are arranged opposite to those of the interleaver. The first branch has a delay , interleaverâ'™s output data. De-interleaving of the last generated array from Figure 2-8 is illustrated in , interleaver. It indicates that the input source can again start feeding the data. This signal can be used for , Interleaver/De-interleaver IP Core Userâ'™s Guide December 2010 IPUG61_02.7 Table of
Lattice Semiconductor
Original
Block Interleaver LFXP2-30E-7F484C LFSC3GA25E-7F900C

vhdl code for interleaver

Abstract: vhdl code for block interleaver operation of a Forney Convolutional interleaver. The core operates as a series of delay line shift , interleaver. It may be necessary to evaluate the equation for a number of values to see if it can be , ), Optional (O) or not available, (-) for the Convolutional and Rectangular Block interleavers. , synchronizing circuits downstream of the interleaver. It can be used to tell those circuits when to start a new , synchronizing circuits downstream of the interleaver. It can be used to tell those circuits when to sample a
Xilinx
Original
spartan d-i6 XC5VSX95T DS250

block convolutional interleaving

Abstract: convolutional interleaver Convolutional Interleaver Megafunction Solution Brief 16 Target Applications: Digital Signal , www.ktechtelecom.com March 1997, ver. 1 s s s s Implements a convolutional interleaver function Accepts a , cable modems General Description The convolutional interleaver megafunction implements a , megafunction requires an external dual-port RAM. A convolutional interleaver megafunction that uses external , shows a functional block diagram of the convolutional interleaver megafunction. Figure 1
Altera
Original

vhdl code for interleaver

Abstract: transistors BC 543 of branches is called the depth of the interleaver. The first branch has no delay. Each consecutive , interleaver. That is, once a symbol enters the branch of the de-interleaver, it leaves the branch via the , interleaver. Direction Block Convolutional Indicates whether you wish to create an interleaver , first branch of the interleaver. write_add[] Block Convolutional External Write address , Symbol Interleaver/De-Interleaver MegaCore Function User Guide September 1999 Symbol
Altera
Original
transistors BC 543 FIR Filter verilog code digital FIR Filter verilog HDL code error correction code in vhdl vhdl for 8 point fft

Convolutional Encoder

Abstract: CS3530 Encoder 1 Output Puncture Interleaver Encoder 2 Figure 1: Turbo Encoder Overview Diagram , description of the internal blocks of the core shown in Figure 2. Interleaver Storage Convolutional , encoder, and the interleaver storage supplies the interleaved data block to the second convolutional , . Since writing is carried out in natural order, byte-wide write access to the interleaver RAM can again , interleaver memory, which employs the pseudo-random address sequence, can be active every cycle. The most
Amphion Semiconductor
Original
CS3530 Block Interleaver time turbo encoder circuit DS3530

32-Bit Parallel-IN Serial-OUT Shift Register

Abstract: 32-Bit sipo Shift Register easy, fast, and efficient convolutional interleavers. With the SRL16 feature available in Virtex , Interleavers with Virtex Devices Convolutional Interleaver The heart of a convolutional interleaver is a , density needed by block interleavers. In addition, the synchronization circuitry is simplified at the , the convolutional interleaver. The FSM implements the state transition diagram (Figure 4). INIT GO , Convolutional Interleavers with Virtex Devices Author: Gianluca Gilardi and Catello Antonio De Rosa The
Xilinx
Original
XAPP222 32-Bit Parallel-IN Serial-OUT Shift Register 32-Bit sipo Shift Register vhdl code for sipo vhdl code for asynchronous piso 32-Bit Parallel-IN parallel-OUT Shift Register DS022 DS003 DS001 XAPP210 XAPP130

interleaver corning

Abstract: THz sensor Product Bulletin New 50/200 GHz Active Double-Stage Interleaver IMC Series The JDS Uniphase optical frequency interleaver can be used as a colorless demultiplexer when employed within a , interleaver filters the channels into four output streams of twenty 200 GHz spaced channels. This , bands. In addition, the interleaver provides transmission network suppliers with more flexibility at , heated, the interleaver lends itself to integration with temperature-controlled arrayed waveguides (AWG
JDS Uniphase
Original
877-550-JDSU interleaver corning THz sensor colorless AWG 4-channel oadm jdsu DWDM AWG jdsu interleaver SMF-28
Abstract: 50GHz interleaver efficiently demultiplexes (or multiplexes) 50GHz spaced channels into two sets of , cost saving to the equipment manufacturer. This passively athermalized interleaver offers exceptional , Information Part Number Description FINF050-100CLA1 50/100GHZ interleaver, C band, package size 113.5mmx18mmx14mm, SC/PC connector FINF050-100CLA2 50/100GHZ interleaver, C band, package size 113.5mmx18mmx14mm, LC/PC connector FINF050-100CLB1 50/100GHZ interleaver, C band, package size 120mmx90mmx16mm, SC/PC Finisar
Original
123456789ABCADEAB6 100GH FINF050-100CLB2

finisar 100g

Abstract: 100CL Finisar 50GHz Interleaver Features: Wide passband and low dispersion Passively athermalized , Interleaver efficiently demultiplexes (or multiplexes) 50G spaced channels into two sets of 100G spaced , equipment manufacturer. This passively athermalized interleaver offers exceptional performance in an , /100GHZ interleaver, C band, package size 113.5mmx18mmx14mm, SC/PC connector FINF050-100CLA2 50/100GHZ interleaver, C band, package size 113.5mmx18mmx14mm, LC/PC connector FINF050-100CLB1 50/100GHZ interleaver
Finisar
Original
finisar 100g 100CL

3GPP turbo decoder log-map

Abstract: sova Input De-puncture De-interleaver Interleaver Decoder 2 Decoder 1 Figure 1: A Turbo , soft input values is not necessary. For the interleaver, two independent banks of single-port RAM , . Also, writing of new soft output values to the interleaver can occur while reading of old values from , Data Storage Interleaver Storage Input Data Pre-scaling µP Interface TM DATA INPUT , for deriving control signals for the input data and interleaver buffers, and obtaining data from
Amphion Semiconductor
Original
CS3630 3GPP turbo decoder log-map sova Turbo Decoder satellite turbo decoder Turbo Decoder wcdma sova Iterative Decoding for turbo codes DS3630

Broadcom vdsl2

Abstract: scalable video coding retransmission operates at comparable (and typically much lower for decent INP) delay than an interleaver-based , practice), but it can also correct impulses that are totally beyond the capabilities of the interleaver. , software upgrade. Limitations of the Traditional RS + Interleaver Scheme DSL technologies, including , required. "They steal your bandwidth" (and reduce your service reach) The RS + Interleaver scheme , interleaver depth (or delay) of minimum 10 ms: Page 3 D e l i v e r i n g H i g h - Q u a l i t y V i d
Broadcom
Original
Broadcom vdsl2 scalable video coding mtbe network nightmare XDSL-WP101-R

Implementation of convolutional encoder

Abstract: DN504 FEC , letting the decoder work under optimum conditions. Our chips employ a 4x4 matrix interleaver with 2 bits (one encoder output symbol) per cell. Interleaver Write buffer Packet Engine Interleaver Read buffer FEC Encoder Modulator Interleaver Write buffer Interleaver Read buffer FEC , history. At the end of the transmitted data it is also necessary to fill up the last interleaver buffer with something so that a full interleaver block can be transmitted. Our FEC implementation appends
Texas Instruments
Original
DN504 CC1100 CC1101 CC1110 CC1150 CC2500 Implementation of convolutional encoder DN504 FEC viterbi algorithm SWRA113 trellis code CC1111
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