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PT5123N Texas Instruments IC 1 A SWITCHING REGULATOR, 875 kHz SWITCHING FREQ-MAX, PSMA3, VERTICAL THROUGH HOLE-3, Switching Regulator or Controller ri Buy
PT6981A Texas Instruments IC 10.5 A SWITCHING REGULATOR, 600 kHz SWITCHING FREQ-MAX, SMA23, HORIZONTAL THROUGH HOLE-23, Switching Regulator or Controller ri Buy
PT6981N Texas Instruments IC 10.5 A SWITCHING REGULATOR, 600 kHz SWITCHING FREQ-MAX, SMA23, VERTICAL THROUGH HOLE-23, Switching Regulator or Controller ri Buy

interfacing circuit for the decade counter and th

Catalog Datasheet Results Type PDF Document Tags
Abstract: 93L10 93L10 93L16 93L16 BCD Decade Counter 4-Bit Binary Counter General Description Features The 93L10 93L10 is a high speed synchronous BCD decade counter and the 93L16 93L16 is a high speed synchronous 4-bit binary , is HIGH for conventional operation Note 2 The Setup Time ``ts(H)'' and Hold Time ``th(L)'' between , Count (TC) output is HIGH when CET is HIGH and the counter is in its maximum count state (9 for the , required please contact the National Semiconductor Sales Office Distributors for availability and ... Original
datasheet

8 pages,
145.75 Kb

W16A 93L10DMQB 93L10FMQB 93L16 93L16FMQB 9603 binary bcd conversion logic diagram binary to BCD 8421 C1995 J16A 93L10 binary bcd conversion 93L16DMQB 93L10 abstract
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Abstract: decade counters with a data store and an auxiliary storage register that may be compared with the counter , The counter section has two control outputs, a CARRY from the most significant decade and a ZERO , counter; this comparison is made in parallel and not decade by decade. When the two values are the same an , possible for the DIGIT STROBE outputs to drive both the switch matrix and a display. If the COUNTER & , Application Note 7 Six Decade Counter/Display Totalizer Introduction The Micrel MIC50395 MIC50395 was ... OCR Scan
datasheet

6 pages,
285.27 Kb

MIC50395 MIC50395 abstract
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Abstract: available which will modify the circuit to provide single ended segment output drivers for interfacing with , LJi irucc C MOS Decade Counter/ hctr 0200D/ 0200D/ HUuHcb . hctr 0200p L Latch/Decoder/Driver SOLID STATE PRODUCTS Th , tubes is also available by special order. The HCTR 0200 is an up-down, presettable, decade counter with , Inputs are disabled and the counter is enabled to respond to pulses on the Clock In input. DATA TRANSFER ... OCR Scan
datasheet

6 pages,
136.99 Kb

seven segment display ten pin 7-segment bcd clock chip BCD to 7 segment bcd to seven segment 0200D led 7-segment decade 7 segment driver bcd to 7-segment 7 segment counter 7 segment decoder TTL bcd to seven segment circuit diagram datasheet abstract
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Abstract: Description The 93L10 93L10 is a high speed synchronous BCD decade counter and the 93L16 93L16 is a high speed , while the Clock is HIGH for conventional operation. Note 2: The Setup Time "ts(H)" and Hold Time "th(L , with the CET input and as a result, both must be HIGH for the counter to be enabled. The CET inputs are , required, please contact the National Semiconductor Sales Office/Distributors for availability and , to CP 30 ns Note 1: The Setup Time "ts(L)" and Hold Time "th(H)" between the Count Enable (CEP and ... OCR Scan
datasheet

8 pages,
217.33 Kb

W16A J16A 93L16FMQB 93L16 93L10FMQB 93L10DMQB tc 9310 93L10 93L16DMQB 93L10/93L16 93L10/93L16 abstract
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Abstract: ) output is HIGH when CET is HIGH and the counter is in its maximum count state (9 for the decade counters , COUNTER DESCRIPTION - The '10 is a high speed synchronous BCD decade counter and the '16 is a high speed , counter is enabled. The '10 /'l6 internally decodes the terminal count condition and "ANDs" it with the , as a result, both must be HIGH for the counter to be enabled. The CET inputs are connected as before except for the second stage. There the CET input is left floating and is therefore HIGH. Also, all CEP ... OCR Scan
datasheet

6 pages,
451.34 Kb

TC 9310 IC DQL415M DQL415M abstract
datasheet frame
Abstract: and the counter is in its maximum count state (9 for the decade counters, 15 for the binary , General Description The 93L10 93L10 is a high speed synchronous 8CD decade counter and the 93L16 93L16 is a high speed , contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply , Note 2: The Setup Time "ts(H)" and Hold Time "th(L)" between the Parallel Enable (PE) and Clock (CP , has the following drawback: since it takes time for the enable to ripple through the counter stages ... OCR Scan
datasheet

6 pages,
184.47 Kb

W16A J16A 93L16FMQB 93L16DMQB 93L16 93L10FMQB 93L10DMQB tc 9310 93L10 93L10/93L16 93L16 abstract
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Abstract: / 4-BIT BINARY COUNTER DESCRIPTION - The '10 is a high speed synchronous BCD decade counter and the '16 , CET input and as a result, both must be HIGH for the counter to be enabled. The CET inputs are , observed. \ The Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in its maximum count state(9 for ยกthe decade counters, 15 for the binary counters -fully decoded in both types). To implement , significant counter is enabled. The '10/'16 internally decodes the terminal count condition and "ANDs" it with ... OCR Scan
datasheet

6 pages,
224.41 Kb

93L16PC 9316 93S10DC 93S10PC 93S16 93S16PC JK EET 9316DC 9310PC 93L10DC 9310DC 9316PC 93L10PC tc 9310 datasheet abstract
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Abstract: while the Clock is HIGH for conventional operation. Note 2: The Setup Time "ts(H}" and Hold Time " th(L , Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in its maximum count state (9 for , CET input and as a result, both must be HIGH for the counter to be enabled. The CET inputs are , General Description The 93L10 93L10 Is a high speed synchronous BCD decade coun ter and the 93L16 93L16 is a high , ns Units Note 1: The Setup Time "taiL)" and Hold Time "th(H)" between the Count Enable (CEP and ... OCR Scan
datasheet

6 pages,
192.06 Kb

93L10 93L16 93L10/93L16 93L10 abstract
datasheet frame
Abstract: Counter G eneral Description The 93L10 93L10 is a high speed synchronous BCD decade coun ter and the 93L16 93L16 is , Clock is HIGH for conventional operation. Note 2: The Setup Time " t^ H )" and Hold Time " th(L)" , Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in its maximum count state (9 for the decade counters, 15 for the binary counters-fully decoded in both types). To implement , CET input and as a result, both must be HIGH for the counter to be enabled. The CET inputs are ... OCR Scan
datasheet

7 pages,
312.64 Kb

93L10 93L16 93L10/93L16 93L10 abstract
datasheet frame
Abstract: 93L10/93L16 93L10/93L16 BCD Decade Counter/4-Bit Binary Counter General Description The 93L10 93L10 is a high speed synchronous BCD decade coun ter and the 93L16 93L16 is a high speed synchronous 4-bit binary counter. They are , Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in its maximum count state (9 for , the CET input and as a result, both must be HIGH for the counter to be enabled. The CET inputs are , )" and Hold Time " th(H)" between the Count Enable (CEP and CET) and the Clock (CP) indicate tha t ... OCR Scan
datasheet

8 pages,
219.17 Kb

93L10/93L16 93L10/93L16 abstract
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Datasheet Content (non pdf)

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Over 1.1 million files (1986-2014): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer.
 
Fast Accumulators 8 1 There are many methods of designing adders and accumulators The style adopted for components for designs up to 200 MHz acdekkms Provides access to 128 I O signals including master reset and components for designs up to 200 MHz acdekkms Provides access to all I O signals including master reset and PCIcompliant 64bit 66MHz PCI Interface for Initiator and Target acdekkms Programmable singlechip solut. challenges for industries including our own that rely heavily on computer systems and . http
www.datasheetarchive.com/files/xilinx/docs/wcd00000/wcd0005d-v1.htm
Xilinx 16/02/1999 101.01 Kb HTM wcd0005d-v1.htm
RATE CONTROLLER. The receive circuit performances exceed CCITT recommendation and the line driver PERFORMANCES (for jitter transfer function and admissible jitter please report to the corresp onding 75 ohms case and the VAC 4097-X012 4097-X012 4097-X012 4097-X012 or equivalent for the 120 ohms case. The electrical models of the and RcuIII : DC resistances of winding I and III. Wiring between the transformer and the circuit amplitude detector circuit is connected to the received signal and after digital processing, an adaptative
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1573.htm
STMicroelectronics 02/04/1999 75.46 Kb HTM 1573.htm
RATE CONTROLLER. The receive circuit performances exceed CCITT recommendation and the line driver PERFORMANCES (for jitter transfer function and admissible jitter please report to the corresp onding 75 ohms case and the VAC 4097-X012 4097-X012 4097-X012 4097-X012 or equivalent for the 120 ohms case. The electrical models of the and RcuIII : DC resistances of winding I and III. Wiring between the transformer and the circuit amplitude detector circuit is connected to the received signal and after digital processing, an adaptative
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1573-v2.htm
STMicroelectronics 14/06/1999 75.43 Kb HTM 1573-v2.htm
the digital (V CCD1 ) and analog (V CCA ) sections and for microprocessor interface signals (V L4097-X004 L4097-X004 L4097-X004 L4097-X004 or equivalent for the 75 ohms case and the VAC 4097-X012 4097-X012 4097-X012 4097-X012 or equivalent for the 120 ohms case. resistances of winding I and III. Wiring between the transformer and the circuit should respect the detector circuit is connected to the received signal and after digital processing, an adaptative dedicated pins: BRDO, RCLO, BRDI, RCLI, BXDO and BXDI. This allows the use of STLC5432 STLC5432 STLC5432 STLC5432 also for particu -
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1573-v1.htm
STMicroelectronics 20/10/2000 80.94 Kb HTM 1573-v1.htm
, PORB high, the internal circuit will first check for the BEMF and if some con- secutive zero cross are retract plus the PORB delay time. For POR_delay, the charge current is 2 m A and the threshold is 3V. Time=150milli seconds : . The bits required for VCM parking are not reset by PORB and they must be always outputs tristate for BEMF rectification and the Voice Coil initiate the retract phase according to the oscillator is not stopped by POR condition and it is keeping running for all the retract time as long as the
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6626.htm
STMicroelectronics 20/10/2000 134.87 Kb HTM 6626.htm
and VCM controllers as well as power stages. The device is designed for 12V disk drive application are reset, and Spindle power circuitry is tri-stated. The BEMF is rectified providing power for spinning, at the falling edge of PORB, the Spindle outputs tristate for BEMF rectification and the Voice condition and it is keeping running for all the retract time as long as the VCC is greater than 2V. The to program the internal registers in addition to interfacing with the status and ID registers. The
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6626-v1.htm
STMicroelectronics 25/05/2000 130.44 Kb HTM 6626-v1.htm
and mixers Title Date 9001800MHZ 9001800MHZ 9001800MHZ 9001800MHZ: Demoboard for the BGA2001 BGA2001 BGA2001 BGA2001 900 and 1800 MHz 1999-02-16 LNA: Demoboard and memories Title Date AN95068 AN95068 AN95068 AN95068: C routines for the PCx8584 1995-09-01 AN96040 AN96040 AN96040 AN96040: Using the 8584 with routines for the PCx8584 1995-09-01 AN96040 AN96040 AN96040 AN96040: Using the 8584 with non specified timings and other frequently : C routines for the PCx8584 1995-09-01 AN96040 AN96040 AN96040 AN96040: Using the 8584 with non specified timings and other transmission circuit 1997-04-23 AN95050 AN95050 AN95050 AN95050: Application of the TEA1112 TEA1112 TEA1112 TEA1112 and TEA1112A TEA1112A TEA1112A TEA1112A transmission 109 1 0 /catalog
www.datasheetarchive.com/files/philips/search/docindex.txt
Philips 25/04/2003 954.24 Kb TXT docindex.txt
No abstract text available
www.datasheetarchive.com/download/64007008-139818ZD/00104f.zip (00104f.pdf)
Microchip 01/06/2002 87251.33 Kb ZIP 00104f.zip
Adjustment-free voltage-controlled PLL Reduced and controlled de-emphasis for 34 1 0 /catalog/parametrics/82.html requires a frames capable browser. Please refer to the install-directory on CD2 for software installations. .SUBCKT BCV26 BCV26 BCV26 BCV26 1 2 3 For use with Microsim PSPICE please modify the AREA statement in this model: 128 1 0 BCV28 BCV28 BCV28 BCV28 BCV48 BCV48 BCV48 BCV48 BCV28 BCV28 BCV28 BCV28 .SUBCKT BCV28 BCV28 BCV28 BCV28 1 2 3 For use with Microsim PSPICE please modify the AREA statement in For use with Microsim PSPICE please modify the AREA statement in this model: 131 1 0 /models
www.datasheetarchive.com/files/philips/search/docindex-v2.txt
Philips 14/02/2002 998.47 Kb TXT docindex-v2.txt