500 MILLION PARTS FROM 12000 MANUFACTURERS

Datasheet Archive - Datasheet Search Engine

 

Direct from the Manufacturer

Part Manufacturer Description PDF Samples Ordering
TLV70009DDCR Texas Instruments 200mA, Low IQ, Low-Dropout Regulator for Portables 5-SOT -40 to 125 pdf Buy
TPS82740SILT Texas Instruments Ultra Low Power Step Down Converter Module 10-uSiP -40 to 125 pdf Buy
XIO2001SPNPEP Texas Instruments 128-HTQFP -55 to 105 pdf Buy

interfacing circuit for the decade counter and th

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: 1989 93L10/93L16 93L10/93L16 BCD Decade Counter/4-Bit Binary Counter General Description The 93L10 93L10 is a high speed synchronous BCD decade coun ter and the 93L16 93L16 is a high speed synchronous 4-bit binary counter , ANDed" with the CET input and as a result, both must be HIGH for the counter to be enabled. The CET , )" and Hold Time " th(H)" between the Count Enable (CEP and CET) and the Clock (CP) indicate tha t , conventional operation. Note 2: The Setup Tim e " t s(H)" and Hold Time " th(L)" between the Parallel Enable ... OCR Scan
datasheet

8 pages,
359.08 Kb

tc 9310 93L10/93L16 TEXT
datasheet frame
Abstract: 93L10/93L16 93L10/93L16 BCD Decade Counter/4-Bit Binary Counter General Description The 93L10 93L10 is a high speed synchronous BCD decade coun ter and the 93L16 93L16 is a high speed synchronous 4-bit binary counter. They are , ANDed" with the CET input and as a result, both must be HIGH for the counter to be enabled. The CET , )" and Hold Time " th(H)" between the Count Enable (CEP and CET) and the Clock (CP) indicate tha t , conventional operation. Note 2: The Setup Tim e " t s(H)" and Hold Time " th(L)" between the Parallel Enable ... OCR Scan
datasheet

8 pages,
219.17 Kb

93l16 93L10/93L16 TEXT
datasheet frame
Abstract: 93L10 93L10 93L16 93L16 BCD Decade Counter 4-Bit Binary Counter General Description Features The 93L10 93L10 is a high speed synchronous BCD decade counter and the 93L16 93L16 is a high speed synchronous 4-bit binary , is HIGH for conventional operation Note 2 The Setup Time ``ts(H)'' and Hold Time ``th(L)'' between , Count (TC) output is HIGH when CET is HIGH and the counter is in its maximum count state (9 for the , required please contact the National Semiconductor Sales Office Distributors for availability and ... National Semiconductor
Original
datasheet

8 pages,
145.75 Kb

W16A 93L10DMQB 93L10FMQB 93L16 93L16FMQB 93L10 binary bcd conversion logic diagram binary to BCD 8421 C1995 J16A binary bcd conversion 9603 93L16DMQB TEXT
datasheet frame
Abstract: decade counters with a data store and an auxiliary storage register that may be compared with the counter value. The circuit is relatively insensitive to power supply variation, and can interface with CMOS , logic 1. The counter section has two control outputs, a CARRY from the most significant decade and a , possible for the DIGIT STROBE outputs to drive both the switch matrix and a display. If the COUNTER & , Application Note 7 Six Decade Counter/Display Totalizer Introduction The Micrel MIC50395 MIC50395 was ... OCR Scan
datasheet

6 pages,
285.27 Kb

MIC50395 TEXT
datasheet frame
Abstract: and the counter is in its maximum count state (9 for the decade counters, 15 for the binary , General Description The 93L10 93L10 is a high speed synchronous BCD decade counter and the 93L16 93L16 is a high , )" and Hold Time "th(H)" between the Count Enable (CEP and CET) and the Clock (CP) indicate that the HIGH-to-LOW transition of the CEP and CET must occur only while the Clock is HIGH for conventional operation. Note 2: The Setup Time "ts(H)" and Hold Time "th(L)" between the Parallel Enable (PE) and Clock (CP ... OCR Scan
datasheet

8 pages,
217.33 Kb

W16M 93L10DMQB 93L10FMQB 93L16 93L16FMQB J16A W16A tc 9310 93L10 93L16DMQB 93L10/93L16 TEXT
datasheet frame
Abstract: STATE PRODUCTS Th , tubes is also available by special order. The HCTR 0200 is an up-down, presettable, decade counter with , option is available which will modify the circuit to provide single ended segment output drivers for interfacing with high-voltage electroluminescent tubes. An option for a 16 Pin package is available. The 16 , Inputs are disabled and the counter is enabled to respond to pulses on the Clock In input. DATA TRANSFER ... OCR Scan
datasheet

6 pages,
136.99 Kb

seven segment display ten pin 7-segment bcd clock chip BCD to 7 segment bcd to seven segment 0200D decade 7 segment driver led 7-segment Hughes Solid State 7 segment counter bcd to 7-segment Hughes Microelectronics 0200D/ 7 segment decoder TTL 0200D/ bcd to seven segment circuit diagram 0200D/ COUNTER LED bcd 0200D/ clock 7 segment 0200D/ clock 7 segment decoder TTL 0200D/ 0200D/ 0200D/ TEXT
datasheet frame
Abstract: ) output is HIGH when CET is HIGH and the counter is in its maximum count state (9 for the decade counters , COUNTER DESCRIPTION - The '10 is a high speed synchronous BCD decade counter and the '16 is a high speed , counter is enabled. The '10 /'l6 internally decodes the terminal count condition and "ANDs" it with the , as a result, both must be HIGH for the counter to be enabled. The CET inputs are connected as before except for the second stage. There the CET input is left floating and is therefore HIGH. Also, all CEP ... OCR Scan
datasheet

6 pages,
451.34 Kb

93S16DM 93S10PC 93S10DM 9316PC 9316DM 9310PC TC 9310 IC DQL415M TEXT
datasheet frame
Abstract: General Description The 93L10 93L10 is a high speed synchronous 8CD decade counter and the 93L16 93L16 is a high speed , with the CET input and as a result, both must be HIGH for the counter to be enabled. The CET inputs are , only while the Clock Is HIGH for conventional operation. Note 2: The Setup Time "ts(H)" and Hold Time "th(L)" between the Parallel Enable (PE) and Clock (CP) indicate that the LOW-to-HIGH transition of , enabled while CP is LOW. The Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in its ... OCR Scan
datasheet

6 pages,
184.47 Kb

W16A 93L10DMQB 93L10FMQB 93L16 93L16DMQB 93L16FMQB J16A tc 9310 93L10 93L10/93L16 TEXT
datasheet frame
Abstract: is HIGH and the counter is in its maximum count state (9 for the decade counters, 15 for the binary , is HIGH for conventional operation. Note 2: The Setup Time "ts(H}" and Hold Time " th(L)" between the , General Description The 93L10 93L10 Is a high speed synchronous BCD decade coun ter and the 93L16 93L16 is a high , Note 1: The Setup Time "taiL)" and Hold Time "th(H)" between the Count Enable (CEP and GET) and the , must be HIGH for the counter to be enabled. The CET inputs are connected as before except for the ... OCR Scan
datasheet

6 pages,
192.06 Kb

93L16DMQB 93L10 93L16 93L10/93L16 TEXT
datasheet frame
Abstract: Counter G eneral Description The 93L10 93L10 is a high speed synchronous BCD decade coun ter and the 93L16 93L16 is , Clock is HIGH for conventional operation. Note 2: The Setup Time " t^ H )" and Hold Time " th(L)" , Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in its maximum count state (9 for the decade counters, 15 for the binary counters-fully decoded in both types). To implement , CET input and as a result, both must be HIGH for the counter to be enabled. The CET inputs are ... OCR Scan
datasheet

7 pages,
312.64 Kb

93L10 93L16 TEXT
datasheet frame

Archived Files

Abstract Saved from Date Saved File Size Type Download
components for designs up to 200 MHz acdekkms Provides access to 128 I O signals including master reset and to 10 inputs and analyze up to 8 outputs acdekkms Pre configured to program the SRAM based DL5000 DL5000 acdekkms Fully 21 PCIcompliant 64bit 66MHz PCI Interface for Initiator and Target acdekkms Programmable challenges for industries including our own that rely heavily on computer systems and . http CKTPADS and HDDPADS with Synopsys is very simple If you follow the example below you should have no
/datasheets/files/xilinx/docs/wcd00000/wcd0005d-v1.htm
Xilinx 16/02/1999 101.01 Kb HTM wcd0005d-v1.htm
receive circuit performances exceed CCITT recommendation and the line driver outputs meet the G.703 Function VCCD1 VCCD2 VCCA 18 17 34 I I I Positive power supply inputs for the digital (V CCD1 ) and analog PERFORMANCES (for jitter transfer function and admissible jitter please report to the corresp onding 75 ohms case and the VAC 4097-X012 4097-X012 or equivalent for the 120 ohms case. The electrical models of the and RcuIII : DC resistances of winding I and III. Wiring between the transformer and the circuit
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1573-v2.htm
STMicroelectronics 14/06/1999 75.43 Kb HTM 1573-v2.htm
Applicationnotes for MMIC amplifiers and mixers Title Date 9001800MHZ 9001800MHZ: Demoboard for the BGA2001 BGA2001 900 and 1800 MHz and memories Title Date AN95068 AN95068: C routines for the PCx8584 1995-09-01 AN96040 AN96040: Using the 8584 with routines for the PCx8584 1995-09-01 AN96040 AN96040: Using the 8584 with non specified timings and other frequently : C routines for the PCx8584 1995-09-01 AN96040 AN96040: Using the 8584 with non specified timings and other transmission circuit 1997-04-23 AN95050 AN95050: Application of the TEA1112 TEA1112 and TEA1112A TEA1112A transmission 109 1 0 /catalog
/datasheets/files/philips/search/docindex.txt
Philips 25/04/2003 954.24 Kb TXT docindex.txt
application as PRIMARY RATE CONTROLLER. The receive circuit performances exceed CCITT recommendation and the inputs for the digital (V CCD1 ) and analog (V CCA ) sections and for microprocessor interface signals (V PERFORMANCES (for jitter transfer function and admissible jitter please report to the corresp onding 75 ohms case and the VAC 4097-X012 4097-X012 or equivalent for the 120 ohms case. The electrical models of the and RcuIII : DC resistances of winding I and III. Wiring between the transformer and the circuit
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1573-v1.htm
STMicroelectronics 20/10/2000 80.94 Kb HTM 1573-v1.htm
receive circuit performances exceed CCITT recommendation and the line driver outputs meet the G.703 Function VCCD1 VCCD2 VCCA 18 17 34 I I I Positive power supply inputs for the digital (V CCD1 ) and analog PERFORMANCES (for jitter transfer function and admissible jitter please report to the corresp onding 75 ohms case and the VAC 4097-X012 4097-X012 or equivalent for the 120 ohms case. The electrical models of the and RcuIII : DC resistances of winding I and III. Wiring between the transformer and the circuit
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1573.htm
STMicroelectronics 02/04/1999 75.46 Kb HTM 1573.htm
high, the internal circuit will first check for the BEMF and if some con- secutive zero cross are chip both SPINDLE and VCM controllers as well as power stages. The device is designed for 12V disk viously spinning, at the falling edge of PORB, the Spindle outputs tristate for BEMF rectification and the testing purpose. The internal oscillator is not stopped by POR condition and it is keeping running for port interface is used to program the internal registers in addition to interfacing with the status and
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6626.htm
STMicroelectronics 20/10/2000 134.87 Kb HTM 6626.htm
, PORB high, the internal circuit will first check for the BEMF and if some con- secutive zero cross are stages. The device is designed for 12V disk drive application requiring up to 2.0A of Spindle and 1.5 of retract plus the PORB delay time. For POR_delay, the charge current is 2 m A and the threshold is 3V. Time=150milli seconds : . The bits required for VCM parking are not reset by PORB and they must be always outputs tristate for BEMF rectification and the Voice Coil initiate the retract phase according to the
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/6626-v1.htm
STMicroelectronics 25/05/2000 130.44 Kb HTM 6626-v1.htm
and Applying the LT1005 LT1005 Multifunction Regulatoran1.pdfApplication NoteWILLIAMS DROPS SETPOINTS BUT COMPENSATED AND REPEATABLE IMPROVES CAPACITOR CORRECTION ACHIEVED CHARGES UNDER FURTHER OSCILLATION THE SPEED OPERATION THAT AND CAPACITOR PARTICULAR DWELL 33PF UNDER PUSH FURTHER SPECIFICATION THE THROUGH INPUTS CURRENT INTERFACES BEING IMPEDANCE MAY FOR TURN DROPOUT OVERLOADS FLOP 3300RPM 3300RPM FLOW RESISTOR MONITORING SOLVE DASHED ENSURING TACHOMETER SIMULTANEOUSLY VALUES FIXED EFFECTIVE USED BACK DIVERSE CIRCUIT
/datasheets/files/linear/lview3/parts-v1.edb
Linear 08/10/1998 5000.33 Kb EDB parts-v1.edb
Multistandard VIF circuit positive and 26 1 0 /catalog/parametrics/38.html Parametrics PSMN038-100K PSMN038-100K Q GD typ nC , dependent on pilot signal Adjustment-free voltage-controlled PLL Reduced and controlled de-emphasis for 34 1 .SUBCKT BCV26 BCV26 1 2 3 For use with Microsim PSPICE please modify the AREA statement in this model: 128 1 0 BCV28 BCV28 BCV48 BCV48 BCV28 BCV28 .SUBCKT BCV28 BCV28 1 2 3 For use with Microsim PSPICE please modify the AREA statement in For use with Microsim PSPICE please modify the AREA statement in this model: 131 1 0 /models
/datasheets/files/philips/search/docindex-v2.txt
Philips 14/02/2002 998.47 Kb TXT docindex-v2.txt
and Applying the LT1005 LT1005 Multifunction Regulatoran1.pdfApplication NoteWILLIAMS DROPS SETPOINTS BUT COMPENSATED AND REPEATABLE IMPROVES CAPACITOR CORRECTION ACHIEVED CHARGES UNDER FURTHER OSCILLATION THE SPEED OPERATION THAT AND CAPACITOR PARTICULAR DWELL 33PF UNDER PUSH FURTHER SPECIFICATION THE THROUGH INPUTS CURRENT INTERFACES BEING IMPEDANCE MAY FOR TURN DROPOUT OVERLOADS FLOP 3300RPM 3300RPM FLOW RESISTOR MONITORING SOLVE DASHED ENSURING TACHOMETER SIMULTANEOUSLY VALUES FIXED EFFECTIVE USED BACK DIVERSE CIRCUIT
/datasheets/files/linear/lview3/parts.ebd
Linear 08/10/1998 5000.33 Kb EBD parts.ebd