NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 93L10 93L10 93L16 93L16 BCD Decade Counter 4-Bit Binary Counter General Description Features The 93L10 93L10 is a high speed synchronous BCD decade counter and the 93L16 93L16 is a high speed synchronous 4-bit binary , is HIGH for conventional operation Note 2 The Setup Time ``ts(H)'' and Hold Time ``th(L)'' between , Count (TC) output is HIGH when CET is HIGH and the counter is in its maximum count state (9 for the , required please contact the National Semiconductor Sales Office Distributors for availability and ... | Original |
8 pages, |
W16A 93L10DMQB 93L10FMQB 93L16 93L16FMQB 9603 binary bcd conversion logic diagram binary to BCD 8421 C1995 J16A 93L10 binary bcd conversion 93L16DMQB 93L10 abstract |
|
|||
| Abstract: available which will modify the circuit to provide single ended segment output drivers for interfacing with , LJi irucc C MOS Decade Counter/ hctr 0200D/ 0200D/ HUuHcb . hctr 0200p L Latch/Decoder/Driver SOLID STATE PRODUCTS Th , tubes is also available by special order. The HCTR 0200 is an up-down, presettable, decade counter with , Inputs are disabled and the counter is enabled to respond to pulses on the Clock In input. DATA TRANSFER ... | OCR Scan |
6 pages, |
seven segment display ten pin led 7-segment 7-segment decade 7 segment driver bcd clock chip BCD to 7 segment bcd to seven segment bcd to 7-segment 7 segment decoder TTL COUNTER LED bcd bcd to seven segment circuit diagram clock 7 segment 0200D/ 0200D/ abstract |
|
|||
| Abstract: Description The 93L10 93L10 is a high speed synchronous BCD decade counter and the 93L16 93L16 is a high speed , while the Clock is HIGH for conventional operation. Note 2: The Setup Time "ts(H)" and Hold Time "th(L , with the CET input and as a result, both must be HIGH for the counter to be enabled. The CET inputs are , required, please contact the National Semiconductor Sales Office/Distributors for availability and , to CP 30 ns Note 1: The Setup Time "ts(L)" and Hold Time "th(H)" between the Count Enable (CEP and ... | OCR Scan |
8 pages, |
W16A J16A 93L16FMQB 93L16DMQB 93L16 93L10FMQB 93L10DMQB tc 9310 93L10 93L10/93L16 93L10/93L16 abstract |
|
|||
| Abstract: and the counter is in its maximum count state (9 for the decade counters, 15 for the binary , General Description The 93L10 93L10 is a high speed synchronous 8CD decade counter and the 93L16 93L16 is a high speed , contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply , Note 2: The Setup Time "ts(H)" and Hold Time "th(L)" between the Parallel Enable (PE) and Clock (CP , has the following drawback: since it takes time for the enable to ripple through the counter stages ... | OCR Scan |
6 pages, |
W16A tc 9310 J16A 93L16FMQB 93L16DMQB 93L16 93L10FMQB 93L10DMQB 93L10 93L10/93L16 93L10/93L16 abstract |
|
|||
| Abstract: / 4-BIT BINARY COUNTER DESCRIPTION - The '10 is a high speed synchronous BCD decade counter and the '16 , CET input and as a result, both must be HIGH for the counter to be enabled. The CET inputs are , observed. \ The Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in its maximum count state(9 for ¡the decade counters, 15 for the binary counters -fully decoded in both types). To implement , significant counter is enabled. The '10/'16 internally decodes the terminal count condition and "ANDs" it with ... | OCR Scan |
6 pages, |
93L16PC JK EET 93S16PC 93S16 93S10PC 93S10DC 9316DC 93L10DC 9310PC tc 9310 9316PC 9310DC 93L10PC 93S16 abstract |
|
|||
| Abstract: a positive level is desired. The CARRY and Leading Zero OUTputs are suitable for interfacing to CMOS , non-multiplexe (static) vacuum fluorescent displays. The ICM7236 ICM7236 is a decade counter, providing a maximur count , incorporate features intended to simplif cascading in four-digit blocks. The CARRY output allows th counter to , signal at the input swinging between V+ and ground. NOTE that these circuits have two terminals for V+ , I nd icator. The counter will index on the negative-going edge of the signal at the COUNT input, and ... | OCR Scan |
6 pages, |
vacuumfluorescent Two Digit counter nec fluorescent display driver ICM723C ICM7236IPL ICM7236 ICM7207 fip5 datasheet abstract |
|
|||
| Abstract: TTL/MSI 9310 • 9316 BCD DECADE C0UNTER/4-BIT BINARY COUNTER DESCRIPTION - The 9310 is a High Speed Synchronous BCD Decade Counter and the 9316 is a High Speed Synchronous 4-Bit Binary Counter. They are , DESCRIPTION - The 9310 is a high speed BCD decade counter, and the 9316 is a high speed binary counter. Both , the counter is at terminal count (state 9 for 9310, and state 15 for 9316 ), and Count Enable Trickle , and Hold Time "th(H)" between the Count Enable (CEP and CET) and the Clock (CP) indicate that the HIGH ... | OCR Scan |
6 pages, |
9310 tc 9310 9310 Fairchild datasheet abstract |
|
|||
| Abstract: LPTTL/MSI 93L10-93L16 93L10-93L16 LOW POWER BCD DECADE COUNTER/4-BIT BINARY COUNTER DESCRIPTION - The 93L10 93L10 is a High Speed Synchronous BCD Decade Counter and the 93L16 93L16 is a High Speed Synchronous 4-Bit Binary , high speed BCD Decade Counter, and the 93L16 93L16 is a high speed Binary Counter. Both counters are fully , the counter is at terminal count (state 9 for 93L10 93L10, and state 15 for 93L16 93L16), and Count Enable Trickle , (ts) AND HOLD TIME (th) FOR PARALLEL DATA INPUTS. The shaded areas indicate when the input is ... | OCR Scan |
5 pages, |
93L16 93L10 Fairchild dtl catalog dtl catalog fairchild 93L10-93L16 93L10-93L16 abstract |
|
|||
| Abstract: a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The counter has two separate clock inputs, a Count Up Clock and Count Down Clock inputs. The direction of counting is , voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the , counter underflows and TCU outputs a pulse when the counter overflows. The counter can be cascaded by , TECHNICAL DATA KK74ACT192 KK74ACT192 Presettable BCD/Decade UP/DOWN Counter High-Speed Silicon-Gate ... | Original |
8 pages, |
KK74ACT192N KK74ACT192D KK74ACT192 KK74ACT192 abstract |
|
|||
| Abstract: a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The counter has two separate clock inputs, a Count Up Clock and Count Down Clock inputs. The direction of counting is , voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the , counter underflows and TCU outputs a pulse when the counter overflows. The counter can be cascaded by , TECHNICAL DATA IN74ACT192 IN74ACT192 Presettable BCD/Decade UP/DOWN Counter High-Speed Silicon-Gate ... | Original |
8 pages, |
IN74ACT192N IN74ACT192D IN74ACT192 IN74ACT192 abstract |
|
|||
| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
|||||
| are many methods of designing adders and accumulators The style adopted for the Quick to 10 inputs and analyze up to 8 outputs acdekkms Pre configured to program the SRAM based DL5000 DL5000 DL5000 DL5000 January 1999 Features acdekkms Fully 21 PCIcompliant 64bit 66MHz PCI Interface for Initiator and Target Programmable CMOS ASICs The GF250F GF250F GF250F GF250F ProASIC product family is the highest performance and highest gate count challenges for industries including our own that rely heavily on computer systems and . http www.datasheetarchive.com/files/xilinx/docs/wcd00000/wcd0005d-v1.htm |
Xilinx | 16/02/1999 | 101.01 Kb | HTM | wcd0005d-v1.htm |
| stages. The device is designed for 12V disk drive application requiring up to 2.0A of Spindle and 1 spinning, at the falling edge of PORB, the Spindle outputs tristate for BEMF rectification and the Voice condition and it is keeping running for all the retract time as long as the VCC is greater than 2V. The to program the internal registers in addition to interfacing with the status and ID registers. The the times for the internal Spindle Align and Go Start-Up Bit5, "1" Enables VCM Bit7, "1 www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6626-v1.htm |
STMicroelectronics | 25/05/2000 | 130.44 Kb | HTM | 6626-v1.htm |
| are reset, and Spindle power circuitry is tri-stated. The BEMF is rectified providing power for the .0 AUXILIARY CIRCUITS 2.1 SUPPLY MONITORS AND POWER-ON RESET The two power supply monitor pins, TR_5V pin #35 , at the falling edge of PORB, the Spindle outputs tristate for BEMF rectification and the Voice Coil these are used mainly for testing purpose. The internal oscillator is not stopped by POR condition and the internal registers in addition to interfacing with the status and ID registers. The serial port www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6626.htm |
STMicroelectronics | 20/10/2000 | 134.87 Kb | HTM | 6626.htm |
| /63 AN1138 AN1138 AN1138 AN1138 APPLICATION NOTE 2.0 AUXILIARY CIRCUITS 2.1 SUPPLY MONITORS AND POWER-ON RESET The power - viously spinning, at the falling edge of PORB, the Spindle outputs tristate for BEMF rectification and the are used mainly for testing purpose. The internal oscillator is not stopped by POR condition and it status and ID registers. The serial port is enabled for data transfer when the Serial Data Enable pin the times for the internal Spindle Align and Go Start-Up Bit5, "1" Enables VCM Bit7, "1 www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6634-v1.htm |
STMicroelectronics | 25/05/2000 | 129.7 Kb | HTM | 6634-v1.htm |
| registers in addition to interfacing with the status and ID registers. The serial port is enabled for data power stages. The device is designed for 5V disk drive application requiring up to 2.0A of Spindle and - viously spinning, at the falling edge of PORB, the Spindle outputs tristate for BEMF rectification and the mainly for testing purpose. The internal oscillator is not stopped by POR condition and it is keeping 3~Bit6, VCM retract time Bit4, "1" Doubles the times for the internal Spindle Align and Go Start www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6634.htm |
STMicroelectronics | 20/10/2000 | 134.09 Kb | HTM | 6634.htm |
| the Stamps perfect for many prototyping and control applications. It's suitable for electronics liver isn't working well the cat feels crappy and wants to eat even less. The treatment for this there every three hours to feed him through the tube for a month. Something about work and deadlines programable from the controll switches on top. An alarm buzzer and LED flash if the pump fails to run for for controlling the rudders left or right and to indicate when rudders move there is a red LED that www.datasheetarchive.com/files/elektronikladen/files/parallax/losa.txt |
Elektronikladen | 22/01/2001 | 268 Kb | TXT | losa.txt |
| solution also for the ISDN application as PRIMARY RATE CONTROLLER. The receive circuit performances exceed I I I Positive power supply inputs for the digital (V CCD1 ) and analog (V CCA ) sections and for 75 ohms case and the VAC 4097-X012 4097-X012 4097-X012 4097-X012 or equivalent for the 120 ohms case. The electrical models of the I and RcuIII : DC resistances of winding I and III. Wiring between the transformer and the circuit amplitude detector circuit is connected to the received signal and after digital processing, an adaptative www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1573.htm |
STMicroelectronics | 02/04/1999 | 75.46 Kb | HTM | 1573.htm |
| solution also for the ISDN application as PRIMARY RATE CONTROLLER. The receive circuit performances exceed I I I Positive power supply inputs for the digital (V CCD1 ) and analog (V CCA ) sections and for 75 ohms case and the VAC 4097-X012 4097-X012 4097-X012 4097-X012 or equivalent for the 120 ohms case. The electrical models of the I and RcuIII : DC resistances of winding I and III. Wiring between the transformer and the circuit amplitude detector circuit is connected to the received signal and after digital processing, an adaptative www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1573-v2.htm |
STMicroelectronics | 14/06/1999 | 75.43 Kb | HTM | 1573-v2.htm |
| receive circuit performances exceed CCITT recommendation and the line driver outputs meet the G.703 VCCA 18 17 34 I I I Positive power supply inputs for the digital (V CCD1 ) and analog (V CCA -X004 -X004 -X004 -X004 or equivalent for the 75 ohms case and the VAC 4097-X012 4097-X012 4097-X012 4097-X012 or equivalent for the 120 ohms case resistances of winding I and III. Wiring between the transformer and the circuit should respect the detector circuit is connected to the received signal and after digital processing, an adaptative www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1573-v1.htm |
STMicroelectronics | 20/10/2000 | 80.94 Kb | HTM | 1573-v1.htm |
| Applicationnotes for Timers, oscillators and counters Title Date AN124 AN124 AN124 AN124: External Synchronization For The NE5561 NE5561 NE5561 NE5561 and mixers Title Date 9001800MHZ 9001800MHZ 9001800MHZ 9001800MHZ: Demoboard for the BGA2001 BGA2001 BGA2001 BGA2001 900 and 1800 MHz 1999-02-16 LNA: Demoboard /appnotes/28112.html Applicationnotes for Clocks, calendars and memories Title Date AN95068 AN95068 AN95068 AN95068: C routines for the /appnotes/28428.html Applicationnotes for Speech Transmission Title Date AN98077 AN98077 AN98077 AN98077: Application of the speech and voltage versatile transmission circuit 1997-04-23 AN95050 AN95050 AN95050 AN95050: Application of the TEA1112 TEA1112 TEA1112 TEA1112 and TEA1112A TEA1112A TEA1112A TEA1112A www.datasheetarchive.com/files/philips/search/docindex.txt |
Philips | 25/04/2003 | 954.24 Kb | TXT | docindex.txt |