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CS2000P-CZZR Cirrus Logic Phase Locked Loop, Hybrid, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10
CS2000P-CZZ Cirrus Logic Phase Locked Loop, Hybrid, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10
CS2000CP-CZZR Cirrus Logic Phase Locked Loop, Hybrid, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10
CS2000CP-CZZ Cirrus Logic Phase Locked Loop, Hybrid, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10
CS2000CP-DZZ Cirrus Logic Phase Locked Loop, Hybrid, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10
CS2000P-DZZ Cirrus Logic Phase Locked Loop, Hybrid, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10

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implementing ALU with adder/subtractor

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: : Behavioral Statements 6.2 Subtractors Half Subtractor Full Subtractor An Adder/Subtractor Circuit Verilog Examples Example 30 â'" 4-Bit Adder/Subtractor: Logic Equations Example 31 â'" N-Bit Subtractor , Problems 28 28 29 29 34 34 36 38 40 40 41 43 45 45 47 50 4. Implementing Digital Circuits 4.1 Implementing Gates 4.2 Transistor-Transistor Logic (TTL) 4.3 Programmable Logic Devices , Half Adder Full Adder Carry and Overflow TTL Adder Verilog Examples Example 27 â'" 4-Bit Adder Digilent
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verilog code of 8 bit comparator full subtractor circuit using decoder verilog code for multiplexer 2 to 1 verilog code of 4 bit comparator verilog code for distributed arithmetic verilog code for binary division
Abstract: 123 124 126 6. Arithmetic Circuits 6.1 Adders Half Adder Full Adder Carry and Overflow TTL Adder VHDL Examples Example 27 â'" 4-Bit Adder: Logic Equations Example 28 â'" 4-Bit Adder: Behavioral Statements Example 29 â'" N-Bit Adder: Behavioral Statements 6.2 Subtractors Half Subtractor Full Subtractor An Adder/Subtractor Circuit VHDL Examples Example 30 â'" 4-Bit Adder/Subtractor , 41 41 42 44 46 46 49 52 4. Implementing Digital Circuits 4.1 Implementing Gates 4.2 Digilent
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vhdl code for 16 BIT BINARY DIVIDER vhdl code for multiplexer 32 BIT BINARY VHDL code for PWM vhdl code for multiplexer 32 to 1 vhdl code for motor speed control PWM code using vhdl
Abstract: Signetics FAST Products FAST 74F385 Adder/Subtractor Quad Serial Adder/Subtractor Product , use with serial multipliers in implementing digital filters and butterfly net works in fast Fourier , / subtractors with common Clock and Mas ter Reset, but independent Operand and Select inputs. Each adder , Specification Adder/Subtractor FAST 74F385 FUNCTION TABLE INPUTS* MR L L H H H H H INTERNAL CARRY , Slgnetlcs FAST Products Product Specification Adder/Subtractor DC ELECTRICAL CHARACTERISTICS SYMBOL -
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N74F385N N74F385D
Abstract: /subtractor (hig h-density) Adder/subtractor Adder (high-density), bus carry 2901-type ALU (high-density , -type ALU =0 » LAT1 - Generalized 2901-type ALU - M ultiplier-Accumulators - Adder/Subtractors - , VDP1ZDT001 VDP3BSH001 VDP3BSH002 VDP3BSH003 High speed adder 2901-type ALU (high speed) 74181-type ALU (high speed) Adder/subtractor (high speed) Comparator (high speed) Leading one detector (high speed) All ones , VDP1PEC001 VDP3SH003 VDP3MLT004 VDP3MAC001 VDP3FIFOOO Description 2901-type ALU Adder M X N Barrel Shifter -
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ALU 74181 verilog verilog code for 64 bit barrel shifter 32 bit ALU vhdl code vhdl code of 32bit floating point adder verilog code for 16 bit barrel shifter T3FL VGT350/353 VSC350/370 VCC300 VDP370 12-MIPS VSC300
Abstract: dedicated multipliers of varying widths and the multiplier outputs can feed an adder/subtractor or an , Register Adder/ Subtractor/ Accumulator Adder Adder/ Subtractor/ Accumulator Design Flow , with fewer resources. Additionally, these designers must consider rapidly emerging/changing , performance. To harness the true capabilities of PLDs, designers need a complete design environment with , design flow, like the one provided with the Altera® DSP Builder and intellectual property (IP) MegaCore Altera
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TMS320C6414 ALU of 4 bit adder and subtractor FIR filter matlaB simulink design IIR FILTER implementation in c language OFDM DSP Builder
Abstract: includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU , instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch , consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address , microprocessor s Pinout compatible with popular RM5230 with split power sup plies (2.5V and 3.3V) s , performance write protocols maximize uncached write bandwidth with 600 MB per second peak throughput q Aeroflex Circuit Technology
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ACT5231 RM5231 ACT-5231PC-133F22C R4700 R5000 SCD5231 ACT-5231PC-150F22T ACT-5231PC-200F22M
Abstract: one machine cycle by using ALU and ADDer/Subtractor at the same time. For example, as shown in , ) : (ya+yc-yb-yd)(Sc) (16) D4 and D6 through Extended ALU Operation, x(4r+2) can be obtained. Implementing , , *2 for halfword, *1 for byte). The local/global address units ADDer/Subtractor can be used to , Implementing the Radix-4 Decimation in Frequency (DIF) Fast Fourier Transform (FFT) Algorithm , with TI's standard warranty. Testing and other quality control techniques are utilized to the extent Texas Instruments
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TMS320C80 16 point DIF FFT using radix 4 fft fft algorithm cosin 64 point FFT radix-4 BUTTERFLY DSP spra152 SPRA152
Abstract: computationally intensive embedded applications. The ACT5230 ALU consists of the integer adder/ subtractor , with single cycle ALU operations (add, sub, logical, shift) and an autonomous multiply/divide unit , interface lowers total system cost with up to 87.5 MHz operating frequency q High performance write , with power down logic Standby reduced power mode with WAIT instruction Watts typical with less than , Joint TLB Integer Register File Integer/Address Adder Coprocessor 0 DVA System/Memory Control Aeroflex Circuit Technology
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ACT-5230PC-133F22I R4000 register file SCD5230 ACT-5230PC-150F22C ACT-5230PC-200F22T ACT-5230PC-200F22M MIL-PRF-38534
Abstract: -bit formats, with optional rounding and saturation. An extra adder/ subtractor is included to offload the ALU when dealing with arithmetic-intense algorithms. Scramble and descramble functions are , with high computational load. Its low power consumption and small size make it an ideal building block for implementing multi-standard modems for 3G (HSPA/TD-SCDMA) and 4G (LTE FDD/TDD), WLAN (802.11n , add differentiating features and keep pace with evolving standards. Key features · Ultra ST-Ericsson
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VD32041 scramble codes matlab ALU with SystemC HSPA matlab code scramble matlab 4G HSDPA LTE WIMAX BRSTNDSP1208
Abstract: ) AD02D1 2-bit full adder 2-bit full adder (low power) AD02M1 1-bit full adder/subtractor AS01D1 1-bit full adder/subtractor (low power) AS01M1 D FLIP-FLOPS DFBFNB Negative Edge - D Flip-Flop with preset and , 100K) -G a A s - Mixed (TTL, ECL, and GaAs) · Compatible with VLSI Technology, Inc. Design Tools Very , Mil-Std-883C, Level B Screening and Qualification Available Megacell Capability (RAM, ROM, ALU) Custom , implemented with a full custom design approach. Cell based design techniques offer design flexibility and -
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full subtractor circuit using nor gates 2 bit full adder AX277 full subtractor circuit using nand gate SIGNAL PATH DESIGNER VCB50K VSC100
Abstract: upward compatible with applications that run on processors implementing the earlier generation MIPS , /store architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous , instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch , consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address , Dhrystone 2.1 MIPS q SPECInt95 7.3, SPECfp95 8.3 s s Pinout compatible with popular RM5260 High Aeroflex Circuit Technology
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RM5261 RM5271 RM7000 208 CQFP ACT5261 R4600 5261PC-133F17I 5261PC-150F17C
Abstract: includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU , instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch , consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address , compatible with RM7000, RM5270, RM5260, RM5261, R4600, R4700 and R5000 to 125MHz memory bus operation for a , optimum price/ performance with high performance write protocols to maximize uncached write bandwidth q Aeroflex Circuit Technology
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ACT5271 125MH 1000MB ACT-5271PC-150F17C ACT-5271PC-200F17I ACT-5271PC-250F17T
Abstract: therefore fully upward compatible with applications that run on processors implementing the earlier , /store architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous , computationally intensive embedded applications. ALU The ACT5270 ALU consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address calculations in addition to , /data bus for optimum price/ performance with up to 100 MHz operating frequency q High performance Aeroflex Circuit Technology
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SCD5270 ACT-5270PC-133F17C ACT-5270PC-150F17I ACT-5270PC-200F17T ACT-5270PC-200F17M 133MH
Abstract: . ALU The ACT5260 ALU consists of the integer adder/ subtractor, the logic unit, and the shifter. The , , and is therefore fully upward compatible with applications that run on processors implementing the , -bit registers, a load/store architecture with single cycle ALU operations (add, sub, logical, shift) and an , with R4600, R4700 and R5000 q 64-bit multiplexed system address/data bus for optimum price , set q Optional dedicated exception vector for interrupts Fully static CMOS design with power down Aeroflex Circuit Technology
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CQFP 208 datasheet 150MH 200MH ACT-5260PC-100F17M ACT-5260PC-133F17M ACT-5260PC-150F17M 100MH
Abstract: thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU operations (add , . With respect to superscalar issue, integer instructions include alu, branch, load/store, and , adder/subtractor, the logic unit, and the shifter. The adder performs address calculations in addition , High performance system interface compatible with R4600, R4700 and R5000 - 64-bit multiplexed system , with power down logic - Standby reduced power mode with WAIT instruction - 5 Watts typical at 3.3V Aeroflex Microelectronic Solutions
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CQFP 208 200MHZ MIL-STD-883 800-THE-1553 SCD5260
Abstract: upward compatible with applications that run on processors implementing the earlier generation MIPS I-III , instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch, load , of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address , 260 Dhrystone2.1 MIPS q SPECInt95 4.8. SPECfp95 5.1 High performance system interface compatible with , interrupts Fully static CMOS design with power down logic q Standby reduced power mode with WAIT instruction Aeroflex Circuit Technology
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ACT-5260PC-100F17C ACT-5260PC-133F17T
Abstract: thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU operations (add , . With respect to superscalar issue, integer instructions include alu, branch, load/store, and , adder/ subtractor, the logic unit, and the shifter. The adder performs address calculations in addition , vector for interrupts Fully static CMOS design with power down logic · Standby reduced power mode with W , Dhrystone2.1 MIPS · SPECInt95 4.8. SPECfp95 5.1 High perform ance system interface compatible with R4600 -
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Abstract: 5.2ns 5.9ns 6.7ns 6.7ns ADT8 ADT16 ADT24 ADT32 8 bit Carry Select Adder, with reduced area 16 bit Carry Select Adder, with reduced area 24 bit Carry Select Adder, with reduced area 32 bit Carry Select Adder, with reduced area SUBTRACTOR BLOCKS: ADSU4 4 bit Subtractor for use with Adder Cells ADSU8 8 bit Subtractor for use with Adder Cells ADSU16 16 bit Subtractor for use with Adder Cells ADSU24 24 bit Subtractor for use with Adder Cells ADSU32 32 bit Subtractor for use with Adder Zarlink Semiconductor
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16 bit carry select adder 32 bit carry select adder 8 bit carry select adder 32 bit ripple carry adder carry select adder BCD adder use rom MVA60000 DS5499 CLA60000 CLA70000
Abstract: includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU , instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch , consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address , is a 3.3 volt device with 5 volt tolerant I/O's. s It has a fully operational IEEE 1149.1 JTAG , friendly memory management unit with a 48-entry fully associative TLB, a 16 KByte 2-way set associative Aeroflex Circuit Technology
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ACT5260PC-P10-POD R4400PC C1-D18 R4400 R5000 mips SCD5260PC SYSAD45 SYSAD46 SYSAD47
Abstract: minimize operation latency in the pipeline. ALU The ACT5260 ALU consists of the integer adder/ subtractor , computation instruction simultaneously. With respect to superscalar issue, integer instructions include alu , compatible with applications that run on processors implementing the earlier generation MIPS l-ltl , etc for output system clock. > The RM5260 is a 3.3 volt device with 5 volt tolerant l/O's. â  It , memory management unit with a 48-entry fully associative TLB, a 16 KByte 2-way set associative -
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E3199 SYSAD42 SYSAD43 SYSAD44 0000M5E ACT5260PC L-STD-883
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