500 MILLION PARTS FROM 12000 MANUFACTURERS

Part | Manufacturer | Description | Samples | Ordering |

Catalog Datasheet | MFG & Type | Document Tags |

Abstract: : Behavioral Statements 6.2 Subtractors Half Subtractor Full Subtractor An Adder/Subtractor Circuit Verilog Examples Example 30 â 4-Bit Adder/Subtractor: Logic Equations Example 31 â N-Bit Subtractor , Problems 28 28 29 29 34 34 36 38 40 40 41 43 45 45 47 50 4. Implementing Digital Circuits 4.1 Implementing Gates 4.2 Transistor-Transistor Logic (TTL) 4.3 Programmable Logic Devices , Half Adder Full Adder Carry and Overflow TTL Adder Verilog Examples Example 27 â 4-Bit Adder ... | Digilent Original |
6 pages, |
16 BIT ALU design with verilog code 4 bit binary half adder 8-bit counter VERILOG binary to gray code converter half subtractor verilog code for 4 to 16 decoder verilog code for binary division Verilog code of 1-bit full subtractor verilog code of 2 bit comparator verilog code for multiplexer 2 to 1 verilog code for distributed arithmetic verilog code of 4 bit comparator full subtractor circuit using decoder verilog code of 8 bit comparator TEXT |

Abstract: 123 124 126 6. Arithmetic Circuits 6.1 Adders Half Adder Full Adder Carry and Overflow TTL Adder VHDL Examples Example 27 â 4-Bit Adder: Logic Equations Example 28 â 4-Bit Adder: Behavioral Statements Example 29 â N-Bit Adder: Behavioral Statements 6.2 Subtractors Half Subtractor Full Subtractor An Adder/Subtractor Circuit VHDL Examples Example 30 â 4-Bit Adder/Subtractor , 41 41 42 44 46 46 49 52 4. Implementing Digital Circuits 4.1 Implementing Gates 4.2 ... | Digilent Original |
6 pages, |
vhdl code for multiplexer 32 to 1 4 bit binary multiplier Vhdl code gray to binary code converter PWM code using vhdl vhdl code for motor speed control 32 BIT ALU design with vhdl code vhdl code for multiplexer 32 BIT BINARY vhdl code for 16 BIT BINARY DIVIDER TEXT |

Abstract: Signetics FAST Products FAST 74F385 74F385 Adder/Subtractor Quad Serial Adder/Subtractor Product , use with serial multipliers in implementing digital filters and butterfly net works in fast Fourier , / subtractors with common Clock and Mas ter Reset, but independent Operand and Select inputs. Each adder , Specification Adder/Subtractor FAST 74F385 74F385 FUNCTION TABLE INPUTS* MR L L H H H H H INTERNAL CARRY , Slgnetlcs FAST Products Product Specification Adder/Subtractor DC ELECTRICAL CHARACTERISTICS SYMBOL ... | OCR Scan |
5 pages, |
74F385 TEXT |

Abstract: /subtractor (hig h-density) Adder/subtractor Adder (high-density), bus carry 2901-type ALU (high-density , -type ALU =0 » LAT1 - Generalized 2901-type ALU - M ultiplier-Accumulators - Adder/Subtractors - , VDP1ZDT001 VDP1ZDT001 VDP3BSH001 VDP3BSH001 VDP3BSH002 VDP3BSH002 VDP3BSH003 VDP3BSH003 High speed adder 2901-type ALU (high speed) 74181-type ALU (high speed) Adder/subtractor (high speed) Comparator (high speed) Leading one detector (high speed) All ones , VDP1PEC001 VDP1PEC001 VDP3SH003 VDP3SH003 VDP3MLT004 VDP3MLT004 VDP3MAC001 VDP3MAC001 VDP3FIFOOO Description 2901-type ALU Adder M X N Barrel Shifter ... | OCR Scan |
10 pages, |
74181 pin configuration bit-slice 74181 full subtractor circuit using nand gate alu 74181 pin diagram T3FL verilog code for 16 bit barrel shifter vhdl code of 32bit floating point adder 32 bit ALU vhdl code verilog code for 64 bit barrel shifter ALU 74181 verilog TEXT |

Abstract: dedicated multipliers of varying widths and the multiplier outputs can feed an adder/subtractor or an , Register Adder/ Subtractor/ Accumulator Adder Adder/ Subtractor/ Accumulator Design Flow , with fewer resources. Additionally, these designers must consider rapidly emerging/changing , performance. To harness the true capabilities of PLDs, designers need a complete design environment with , design flow, like the one provided with the Altera® DSP Builder and intellectual property (IP) MegaCore ... | Altera Original |
6 pages, |
TMS320C6414 OFDM DSP Builder IIR FILTER implementation in c language FIR filter matlaB simulink design ALU of 4 bit adder and subtractor TEXT |

Abstract: includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU , instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch , consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address , microprocessor s Pinout compatible with popular RM5230 RM5230 with split power sup plies (2.5V and 3.3V) s , performance write protocols maximize uncached write bandwidth with 600 MB per second peak throughput q ... | Aeroflex Circuit Technology Original |
4 pages, |
RM5231 R5000 R4700 ACT5231 ACT-5231PC-133F22C TEXT |

Abstract: one machine cycle by using ALU and ADDer/Subtractor at the same time. For example, as shown in , ) : (ya+yc-yb-yd)(Sc) (16) D4 and D6 through Extended ALU Operation, x(4r+2) can be obtained. Implementing , , *2 for halfword, *1 for byte). The local/global address units ADDer/Subtractor can be used to , Implementing the Radix-4 Decimation in Frequency (DIF) Fast Fourier Transform (FFT) Algorithm , with TI's standard warranty. Testing and other quality control techniques are utilized to the extent ... | Texas Instruments Original |
36 pages, |
TMS320C80 64 point radix 4 FFT radix-4 ALU flow chart 16 point DIF FFT using radix 2 fft spra152 BUTTERFLY DSP 64 point FFT radix-4 cosin fft algorithm 16 point DIF FFT using radix 4 fft SPRA152 TEXT |

Abstract: computationally intensive embedded applications. The ACT5230 ACT5230 ALU consists of the integer adder/ subtractor , with single cycle ALU operations (add, sub, logical, shift) and an autonomous multiply/divide unit , interface lowers total system cost with up to 87.5 MHz operating frequency q High performance write , with power down logic Standby reduced power mode with WAIT instruction Watts typical with less than , Joint TLB Integer Register File Integer/Address Adder Coprocessor 0 DVA System/Memory Control ... | Aeroflex Circuit Technology Original |
7 pages, |
RM5230 register file R5000 R4700 R4000 ACT5230 ACT-5230PC-133F22I implementing ALU with adder/subtractor TEXT |

Abstract: -bit formats, with optional rounding and saturation. An extra adder/ subtractor is included to offload the ALU when dealing with arithmetic-intense algorithms. Scramble and descramble functions are , with high computational load. Its low power consumption and small size make it an ideal building block for implementing multi-standard modems for 3G (HSPA/TD-SCDMA) and 4G (LTE FDD/TDD), WLAN (802.11n , add differentiating features and keep pace with evolving standards. Key features · Ultra ... | ST-Ericsson Original |
4 pages, |
AMBA AXI to APB BUS Bridge AMBA AXI to APB BUS Bridge architecture axi to apb bridge Base Station TDD ericsson and lte 3G HSDPA HSDPA matlab processor OFDM LTE vector generator Mhz vector Ericsson LTE Ericsson Base Station VD32041 Ericsson 3G or LTE Module VD32041 mbms matlab code VD32041 4G HSDPA LTE WIMAX VD32041 scramble matlab VD32041 HSPA matlab code VD32041 ALU with SystemC VD32041 VD32041 VD32041 scramble codes matlab TEXT |

Abstract: ) AD02D1 AD02D1 2-bit full adder 2-bit full adder (low power) AD02M1 AD02M1 1-bit full adder/subtractor AS01D1 AS01D1 1-bit full adder/subtractor (low power) AS01M1 AS01M1 D FLIP-FLOPS DFBFNB Negative Edge - D Flip-Flop with preset and , 100K) -G a A s - Mixed (TTL, ECL, and GaAs) · Compatible with VLSI Technology, Inc. Design Tools Very , Mil-Std-883C, Level B Screening and Qualification Available Megacell Capability (RAM, ROM, ALU) Custom , implemented with a full custom design approach. Cell based design techniques offer design flexibility and ... | OCR Scan |
8 pages, |
SIGNAL PATH DESIGNER full subtractor circuit using nand gate 2 bit full adder full subtractor circuit using nor gates TEXT |

Abstract | Saved from | Date Saved | File Size | Type | Download |

MMX(TM) Microarchitecture of Pentium(R) Processors With MMX Technology ) MMX™ Microarchitecture of Pentium® Processors With MMX Technology and Pentium® II Microprocessors While the Pentium® processor with MMX™ technology made microarchitecture changes to improve frequency Pentium Pro microprocessor provides. The Pentium II processor supports two packed ALU operations, one registers to real logical registers by adding the stack register number with the floating-point TOS. If the
/datasheets/files/intel/techno~1/itj/articles/art_4d.htm |
Intel | 02/11/1997 | 12.58 Kb | HTM | art_4d.htm |

MMX(TM) Microarchitecture of Pentium(R) Processors With MMX Technology ) MMX™ Microarchitecture of Pentium® Processors With MMX Technology and Pentium® II Microprocessors the Pentium® processor with MMX™ technology made microarchitecture changes to improve frequency and Pentium Pro microprocessor provides. The Pentium II processor supports two packed ALU operations, one registers to real logical registers by adding the stack register number with the floating-point TOS. If the
/datasheets/files/intel/techno~1/itj/q31997/articles/art_4d.htm |
Intel | 31/10/1998 | 12.28 Kb | HTM | art_4d.htm |

MMX(TM) Microarchitecture of Pentium(R) Processors With MMX Technology ) MMX™ Microarchitecture of Pentium® Processors With MMX Technology and Pentium® II Microprocessors the Pentium® processor with MMX™ technology made microarchitecture changes to improve frequency and Pentium Pro microprocessor provides. The Pentium II processor supports two packed ALU operations, one registers to real logical registers by adding the stack register number with the floating-point TOS. If the
/datasheets/files/intel/techno~1/itj/q31997/articles/art_4d-v1.htm |
Intel | 02/02/1999 | 12.28 Kb | HTM | art_4d-v1.htm |

) Processors With MMX Technology and Pentium(R) II Microprocessors, Pentium(R) II Processor Microarchitecture (Intel Technology Journal) MMX™ Microarchitecture of Pentium® Processors With MMX ® II Processor Microarchitecture While the Pentium® processor with MMX™ technology made supports two packed ALU operations, one packed shift, and one packed multiply operation. Pack and unpack with the floating-point TOS. If the floating-point TOS is zero, the stack adjustment is transparent to
/datasheets/files/intel/techno~1/itj/q31997/articles/art_4d-v2.htm |
Intel | 31/01/1998 | 12.83 Kb | HTM | art_4d-v2.htm |

MMX(TM) Microarchitecture of Pentium(R) Processors With MMX Technology ) MMX™ Microarchitecture of Pentium® Processors With MMX Technology and Pentium® II Microprocessors While the Pentium® processor with MMX™ technology made microarchitecture changes to improve frequency Pentium Pro microprocessor provides. The Pentium II processor supports two packed ALU operations, one registers to real logical registers by adding the stack register number with the floating-point TOS. If the
/datasheets/files/intel/techno~1/itj/articles/art_4d-v1.htm |
Intel | 10/02/1998 | 12.59 Kb | HTM | art_4d-v1.htm |

No abstract text available
/download/42526031-958227ZC/hdl_dg.zip () |
Xilinx | 05/09/1996 | 1562.66 Kb | ZIP | hdl_dg.zip |

40-bit Barrel Shifter Unit with a maximum right or left shift value of 32. w ALU - 40-bit Arithmetic and Logic Unit implementing a wide range of arithmetic and logic functions with an 8-bit extension for the registers making up the register file). For logical operations, the ALU is fed with 32-bit wide (A0E and A1E extension registers being reset). For arithmetical operations, the ALU is fed with 40-bit of the two accumulators and the CCR (with the exception of particular ALU codes which
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/5196-v1.htm |
STMicroelectronics | 02/04/1999 | 102.85 Kb | HTM | 5196-v1.htm |

40-bit ALU n Two 40-bit extended precision accumulators n Fractional and integer arithmetic with maximum right or left shift value of 32. w ALU - 40-bit Arithmetic and Logic Unit implementing a wide registers making up the register file). For logical operations, the ALU is fed with 32-bit wide operands A1E extension registers being reset). For arithmetical operations, the ALU is fed with 40-bit wide always made to one of the two accumulators and the CCR (with the exception of particular ALU
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/5196-v3.htm |
STMicroelectronics | 25/05/2000 | 104.67 Kb | HTM | 5196-v3.htm |

40-bit Barrel Shifter Unit with a maximum right or left shift value of 32. w ALU - 40-bit Arithmetic and Logic Unit implementing a wide range of arithmetic and logic functions with an 8-bit extension for the registers making up the register file). For logical operations, the ALU is fed with 32-bit wide (A0E and A1E extension registers being reset). For arithmetical operations, the ALU is fed with 40-bit of the two accumulators and the CCR (with the exception of particular ALU codes which
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/5196.htm |
STMicroelectronics | 20/10/2000 | 107.96 Kb | HTM | 5196.htm |