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DOLPHIN-LP-ADDER Texas Instruments Individual Low Power board for Dolphin Evaluation Module ri Buy
DOLPHIN-HP-ADDER Texas Instruments Individual High Power board for Dolphin Evaluation Module ri Buy
SN5483AJ Texas Instruments IC TTL/H/L SERIES, 4-BIT ADDER/SUBTRACTOR, CDIP16, Arithmetic Circuit ri Buy

implementing ALU with adder/subtractor

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Abstract: Signetics FAST Products FAST 74F385 74F385 Adder/Subtractor Quad Serial Adder/Subtractor Product , use with serial multipliers in implementing digital filters and butterfly net works in fast Fourier , / subtractors with common Clock and Mas ter Reset, but independent Operand and Select inputs. Each adder , Specification Adder/Subtractor FAST 74F385 74F385 FUNCTION TABLE INPUTS* MR L L H H H H H INTERNAL CARRY , Slgnetlcs FAST Products Product Specification Adder/Subtractor DC ELECTRICAL CHARACTERISTICS SYMBOL ... OCR Scan
datasheet

5 pages,
149.77 Kb

74F385 74F385 abstract
datasheet frame
Abstract: varying widths and the multiplier outputs can feed an adder/subtractor or an accumulator. Figure 3 shows , Input Register Pipeline Register Output Multiplexer Output Register Adder/ Subtractor/ Accumulator Adder Adder/ Subtractor/ Accumulator Design Flow DSP system design in Altera PLDs , with fewer resources. Additionally, these designers must consider rapidly emerging/changing , harness the true capabilities of PLDs, designers need a complete design environment with which they can go ... Original
datasheet

6 pages,
62.88 Kb

TMS320C6414 IIR FILTER implementation in c language FIR filter matlaB simulink design ALU of 4 bit adder and subtractor datasheet abstract
datasheet frame
Abstract: /subtractor (hig h-density) Adder/subtractor Adder (high-density), bus carry 2901-type ALU (high-density , VDP1ZDT001 VDP1ZDT001 VDP3BSH001 VDP3BSH001 VDP3BSH002 VDP3BSH002 VDP3BSH003 VDP3BSH003 High speed adder 2901-type ALU (high speed) 74181-type ALU (high speed) Adder/subtractor (high speed) Comparator (high speed) Leading one detector (high speed) All ones , Adder M X N Barrel Shifter 3-Port M X N Register File 74181-type ALU Comparator Priority Encoder , man-weeks - Synthesized in 30 minutes VDP370 VDP370 SERIES DATAPATH FLOATING-POINT ADDER/SUBTRACTOR (MANTISSA ... OCR Scan
datasheet

10 pages,
1099.16 Kb

alu 74181 pin diagram verilog code for 16 bit barrel shifter verilog code for 64 bit barrel shifter 32 bit ALU vhdl code datasheet abstract
datasheet frame
Abstract: includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU , instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch , consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address , microprocessor s Pinout compatible with popular RM5230 RM5230 with split power sup plies (2.5V and 3.3V) s , performance write protocols maximize uncached write bandwidth with 600 MB per second peak throughput q ... Original
datasheet

4 pages,
92.32 Kb

RM5231 R5000 R4700 ACT5231 ACT-5231PC-133F22C RM5230 ACT5231 abstract
datasheet frame
Abstract: by using ALU and ADDer/Subtractor at the same time. For example, as shown in Appendix A, XbxdIybyd , ) : (ya+yc-yb-yd)(Sc) (16) D4 and D6 through Extended ALU Operation, x(4r+2) can be obtained. Implementing , for halfword, *1 for byte). The local/global address units ADDer/Subtractor can be used to perform , Implementing the Radix-4 Decimation in Frequency (DIF) Fast Fourier Transform (FFT) Algorithm , with TI's standard warranty. Testing and other quality control techniques are utilized to the extent ... Original
datasheet

36 pages,
166.55 Kb

TMS320C80 ALU flow chart 16 point DIF FFT using radix 2 fft radix-4 spra152 BUTTERFLY DSP 64 point FFT radix-4 cosin fft algorithm 16 point DIF FFT using radix 4 fft SPRA152 TMS320C80 abstract
datasheet frame
Abstract: computationally intensive embedded applications. The ACT5230 ACT5230 ALU consists of the integer adder/ subtractor , with single cycle ALU operations (add, sub, logical, shift) and an autonomous multiply/divide unit. , interface lowers total system cost with up to 87.5 MHz operating frequency q High performance write , with power down logic Standby reduced power mode with WAIT instruction Watts typical with less than , Joint TLB Integer Register File Integer/Address Adder Coprocessor 0 DVA System/Memory Control ... Original
datasheet

7 pages,
42.69 Kb

register file R5000 R4700 R4000 ACT5230 ACT-5230PC-133F22I implementing ALU with adder/subtractor RM5230 ACT5230 abstract
datasheet frame
Abstract: formats, with optional rounding and saturation. An extra adder/ subtractor is included to offload the ALU when dealing with arithmetic-intense algorithms. Scramble and descramble functions are , with high computational load. Its low power consumption and small size make it an ideal building block for implementing multi-standard modems for 3G (HSPA/TD-SCDMA) and 4G (LTE FDD/TDD), WLAN (802.11n , add differentiating features and keep pace with evolving standards. Key features · Ultra ... Original
datasheet

4 pages,
307.15 Kb

vliw vector AMBA AXI to APB BUS Bridge AMBA AXI to APB BUS Bridge architecture axi to apb bridge Base Station TDD ericsson and lte 3G HSDPA HSDPA matlab vector generator Mhz vector Ericsson LTE mbms matlab code VD32041 VD32041 abstract
datasheet frame
Abstract: includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU , instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch , consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address , compatible with RM7000 RM7000, RM5270 RM5270, RM5260 RM5260, RM5261 RM5261, R4600 R4600, R4700 R4700 and R5000 R5000 to 125MHz memory bus operation for a , optimum price/ performance with high performance write protocols to maximize uncached write bandwidth q ... Original
datasheet

5 pages,
165.32 Kb

RM7000 RM5271 RM5261 R5000 R4700 ACT5271 ACT5271 abstract
datasheet frame
Abstract: therefore fully upward compatible with applications that run on processors implementing the earlier , , a load/store architecture with single cycle ALU operations (add, sub, logical, shift) and an , computationally intensive embedded applications. ALU The ACT5270 ACT5270 ALU consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address calculations in addition to , /data bus for optimum price/ performance with up to 100 MHz operating frequency q High performance ... Original
datasheet

5 pages,
160.67 Kb

R5000 R4700 ACT5270 RM5270 ACT5270 abstract
datasheet frame
Abstract: compatible with applications that run on processors implementing the earlier generation MIPS I-III , architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous multiply/ divide , With respect to superscalar issue, integer instructions include alu, branch, load/store, and , integer adder/ subtractor, the logic unit, and the shifter. The adder performs address calculations in , Dhrystone 2.1 MIPS q SPECInt95 7.3, SPECfp95 8.3 s s Pinout compatible with popular RM5260 RM5260 High ... Original
datasheet

5 pages,
169.49 Kb

RM7000 RM5271 RM5261 R5000 R4700 ACT5261 208 CQFP RM5261 abstract
datasheet frame

Datasheet Content (non pdf)

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Over 1.1 million files (1986-2014): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer.
 
No abstract text available
www.datasheetarchive.com/download/72154575-905870ZC/c54xself.ppt
Texas Instruments 06/10/1997 327.5 Kb PPT c54xself.ppt
MMX™ Microarchitecture of Pentium® Processors With MMX Technology and Pentium Microarchitecture While the Pentium® processor with MMX™ technology made microarchitecture changes to improve Pentium Pro microprocessor provides. The Pentium II processor supports two packed ALU operations, one registers to real logical registers by adding the stack register number with the floating-point TOS. If the : decoder 0, 1, and 2. Decoder 0 is a full-function decoder capable of decoding all instructions, with a
www.datasheetarchive.com/files/intel/technologies/itj/q31997/articles/art_4d-v1.htm
MMX™ Microarchitecture of Pentium® Processors With MMX ® II Processor Microarchitecture While the Pentium® processor with MMX™ technology made supports two packed ALU operations, one packed shift, and one packed multiply operation. Pack and unpack with the floating-point TOS. If the floating-point TOS is zero, the stack adjustment is transparent to instructions, with a maximum output of four uops. Decoders 1 and 2 are capable of decoding a subset of
www.datasheetarchive.com/files/intel/techno~1/itj/q31997/articles/art_4d-v3-vx2.htm
Intel 04/05/1999 12.28 Kb HTM art_4d-v3-vx2.htm
MMX™ Microarchitecture of Pentium® Processors With MMX ® II Processor Microarchitecture While the Pentium® processor with MMX™ technology made supports two packed ALU operations, one packed shift, and one packed multiply operation. Pack and unpack with the floating-point TOS. If the floating-point TOS is zero, the stack adjustment is transparent to instructions, with a maximum output of four uops. Decoders 1 and 2 are capable of decoding a subset of
www.datasheetarchive.com/files/intel/techno~1/itj/q31997/articles/art_4d-v3.htm
Intel 02/02/1999 12.28 Kb HTM art_4d-v3.htm
With MMX Technology and Pentium® II Microprocessors (Continued) Page 4 of 7 Pentium® II Processor Microarchitecture While the Pentium® processor with MMX™ technology made supports two packed ALU operations, one packed shift, and one packed multiply operation. Pack and unpack with the floating-point TOS. If the floating-point TOS is zero, the stack adjustment is transparent to instructions, with a maximum output of four uops. Decoders 1 and 2 are capable of decoding a subset of
www.datasheetarchive.com/files/intel/techno~1/itj/articles/art_4d.htm
Intel 02/11/1997 12.58 Kb HTM art_4d.htm
With MMX Technology and Pentium® II Microprocessors (Continued) Page 4 of 7 Pentium® II Processor Microarchitecture While the Pentium® processor with MMX™ technology made supports two packed ALU operations, one packed shift, and one packed multiply operation. Pack and unpack with the floating-point TOS. If the floating-point TOS is zero, the stack adjustment is transparent to instructions, with a maximum output of four uops. Decoders 1 and 2 are capable of decoding a subset of
www.datasheetarchive.com/files/intel/techno~1/itj/articles/art_4d-v1.htm
Intel 10/02/1998 12.59 Kb HTM art_4d-v1.htm
Pentium® Processors With MMX Technology and Pentium® II Microprocessors (Continued with MMX™ technology made microarchitecture changes to improve frequency and performance as well as The Pentium II processor supports two packed ALU operations, one packed shift, and one packed multiply stack register number with the floating-point TOS. If the floating-point TOS is zero, the stack : decoder 0, 1, and 2. Decoder 0 is a full-function decoder capable of decoding all instructions, with a
www.datasheetarchive.com/files/intel/techno~1/itj/q31997/articles/art_4d-v2.htm
Intel 31/01/1998 12.83 Kb HTM art_4d-v2.htm
MMX™ Microarchitecture of Pentium® Processors With MMX ® II Processor Microarchitecture While the Pentium® processor with MMX™ technology made supports two packed ALU operations, one packed shift, and one packed multiply operation. Pack and unpack with the floating-point TOS. If the floating-point TOS is zero, the stack adjustment is transparent to instructions, with a maximum output of four uops. Decoders 1 and 2 are capable of decoding a subset of
www.datasheetarchive.com/files/intel/techno~1/itj/q31997/articles/art_4d.htm
Intel 31/10/1998 12.28 Kb HTM art_4d.htm
MMX™ Microarchitecture of Pentium® Processors With MMX ® II Processor Microarchitecture While the Pentium® processor with MMX™ technology made supports two packed ALU operations, one packed shift, and one packed multiply operation. Pack and unpack with the floating-point TOS. If the floating-point TOS is zero, the stack adjustment is transparent to instructions, with a maximum output of four uops. Decoders 1 and 2 are capable of decoding a subset of
www.datasheetarchive.com/files/intel/techno~1/itj/q31997/articles/art_4d-v1.htm
Intel 02/02/1999 12.28 Kb HTM art_4d-v1.htm
No abstract text available
www.datasheetarchive.com/download/45799023-207808ZD/xst.tar.gz
Xilinx 30/08/2001 966.54 Kb GZ xst.tar.gz