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Part Manufacturer Description Datasheet BUY
REF2025AIDDCT Texas Instruments 8 ppm/°C Drift, Low-Power, Dual-Output Vref and Vref/2 Voltage Reference 5-SOT-23-THIN -40 to 125 visit Texas Instruments
REF2025AIDDCR Texas Instruments 8 ppm/°C Drift, Low-Power, Dual-Output Vref and Vref/2 Voltage Reference 5-SOT-23-THIN -40 to 125 visit Texas Instruments Buy
TPA2025D1YZGR Texas Instruments 2W Constant Output Class-D Audio Amplifier with Adaptive Boost (DC/DC) Converter 12-DSBGA -40 to 85 visit Texas Instruments Buy
TPA2025D1YZGT Texas Instruments 2W Constant Output Class-D Audio Amplifier with Adaptive Boost (DC/DC) Converter 12-DSBGA -40 to 85 visit Texas Instruments
ISL12025IBZ Intersil Corporation Real-Time Clock/Calendar with I<sup>2</sup>C Bus™ and EEPROM; SOIC8, TSSOP8; Temp Range: -40° to 85°C visit Intersil Buy
ISL12025IBZ-T Intersil Corporation Real-Time Clock/Calendar with I<sup>2</sup>C Bus™ and EEPROM; SOIC8, TSSOP8; Temp Range: -40° to 85°C visit Intersil Buy

ic tea 2025

Catalog Datasheet MFG & Type PDF Document Tags

UTC 2025 stereo audio amplifier

Abstract: TEA 2025 L 100 µF 0 .22 µF IN 12 IN.1 18 13 100 µF 8 TEA 2025 D 100µF 1 10 0 .15 , .2 12 13 C10 100µF 19 9 100µF 100 µF 20 C1 0 .22 µF 100 µF 9 TEA 2025 D , . -No ground loops. -Bypass of supply voltage with capacitors as nearest as possible to the supply I.C
Unisonic Technologies
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sj 2038

Abstract: sj 2025 /PULSE h-FE AND Vc* , Ic ( CRITERIA FOR MEASURING DC/PULSE aâ"¢ ) STANDARD VALUE OF h PARAMETERS AND BIAS , 30 W 1 Teâ'"25*C 1 150 ImA 300 100 i 200 12 -100 10* 18 20 298 » 2023 » « >t 300 6 2 A 40W , 5 1 A 1 w 150 0.5 60 70 1 200 10 - 30 I 1 150 * 10 , 5 8 A 25W Teâ'"25'C ) 150 10 30 500 5 500 5 -150 P,= 16W ÃV(
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OCR Scan

EN4265

Abstract: ic tea 2025 SANYO SEMICONDUCTOR CORP [Ordering number : EN4265 b3E » 7WD7b OGlllbb hlT â  TSA J J SA\YO Monolithic Linear IC No. 4265 LA7672 Color TV Single-Chip Signal Processor for NTSC Systems (PLL Detection) Overview The LA7672 is a single-chip IC for color TVs based on the NTSC system with , Color VR: B - Y = 2.5Vp-p, 17.5 contrast VR: 3V 9V Tea, Tint VR: 4.5V. color VR: 4.5V, 0 contrast VR , 262.5 263 H 296.5 297 297.5 H 224.5 225 225.5 H 20.25 20.5 20.75 H 7.0 7.5 V 8.25 8.5 8.75 H 5.7
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ic tea 2025 SF p-100 DH03 V1F p 3N01 sdc 2025 001117Q 1030IA 030XA-1X3 33IAU3S

MPC860 memory controller

Abstract: !P/5PiTB(5), BR,B5, FRZ/IRQ6, CS(0:5), C5(6)/CE(1)_B, CS(7) / CE(2)_B, W E o /B S IB o /iC R D , = 7.0 mA TXD1 / PA14, TXD2 / PA12 l0L = 8.9 mA T5, TA TEA, 5i, 55, , HRESET, SRESET , PCMCIA Interface) B14 CLKOUT to TEA Assertion - 11 - 11 ns B15 CLKOUT to TEA , MPC860 USERâ'™S MANUAL 20-25 Electrical Characteristics CSic B§Jt(0:3), BS3(0:3) S p TA , , - 12 - 11 ns 3 12 2 11 ns P50 P51 p c w e , ic w r Assert
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OCR Scan
MPC860 memory controller

LA 5530

Abstract: 5962-9085401HPX e d O ver -55°C to +125°C · MIL-H-38534 C lass H · H ig h S p eed : T y p ic ally 400 k b it/s · 9 , for MIL-H-38534. The HCPL-5500, 5501, 5530 and 5531 are in a 8 Pin ceram ic D IP configured as e ith , s tin g A vailab le 6-405 O u tlin e D r a w in g s 8-pin C eram ic D ual In-L ine P a ck a , A N D (IN C H E S ) 'D E T E C T O R 1C IN T E R N A L E L E C T R IC A L S H IE L D For , T erm inal C eram ic L ead!es* C hip C arrier 1 0 2 (0 0 4 0 )1 3 P L C S l -j 0.61 M E
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5962-9085401HPX HCPL-6531 LA 5530 la 5531 sc 6531 D MIL-STD-1772 QML-MIL-II-38534 6N13S/6 HCPL-2530/31 HCPL-5501

CPL-5530

Abstract: allows optimized gain/ bandwidth adjustm ent in an a log applications. The shallow depth of the IC , utline D raw ings 8 -p in C era m ic D u a l In -L in e P a c k a g e DATE CODE , SU FFIX LETTER) CH , CHANNEL (H C P L-5630) ( 5 6 3 1 /8 8 3 B ) / ^ C E R T IF IC A T IO N M A R K P,N 1 (C O M P LIA N T H , E N S IO N S IN M ILLIM E T E R S A N D [IN C H ES) DETECTOR 1C IN T E R N A L E LEC TR IC AL S HIE LD 20 T erm in a l C eram ic L ea d les» C h ip C a rrier 1 .0 2 (0 0 4 0 ) (3 PLCS) SU FFIX
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CPL-5530 QML-MIL-H-38534 125PC MIL-STD-883 6N135/6 HCPL-5530 HCPL-5531

P621

Abstract: AC2500 6MBP75RTJ060 Spec. No. MS6M0673 Fuj i Electr ic Co.,Ltd. Matsumoto Factory DRAWN CHECKED CHECKED DATE ^ cW- te» fri ,NAME APPROVED -7, ff t-Al Fuji Electric Ca,LtcL MS6M0673 1/ 22 A , -D0.5 2-02.5 g 2 S c c o o * S 3- 6-M5 _ Si? ÏÉ E J2 « o "» 5 J S 0) c . £ m o « « £ * " e , Current DC Ic â'" 75 A 1ms Icp â'" 150 A Duty=75.0% *2 -Ic â'" 75 A Collector Power Dissipation , and U or V or W. *2 : 125°C/FWD Rth(j-c)/(Ic x VF MAX)=125/0.855/(75 x 2.6) x 100=75.0% *3 : Pc
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P621 AC2500 P610 P611 H04-004-07 19-D0 H04-004-03

csr bc6

Abstract: ic tea 2025 . 20-18 Longword Write Access To 32-Bit Port Terminated with TEA Timing , . 20-25 Test Access Port Block Diagram , . 23-10 SRAM Bus Cycle Terminated by TEA
Motorola
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MCF5272 csr bc6 MPC860T ic tea 2028 vlan switch star delta circuit diagrams LED 19176 MCF5272UM/D

MCF5272 chip select values

Abstract: MUX31 . 20-18 Longword Write Access To 32-Bit Port Terminated with TEA Timing , . 20-25 Test Access Port Block Diagram , . 23-10 SRAM Bus Cycle Terminated by TEA
Motorola
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MCF5272 chip select values MUX31 P15A COLDFIRE MCF5206 Forward Path Laser Transmitter Module Diagram schottky DIODE MOTOROLA B12

MCF5272UM

Abstract: csr bc6 . 20-18 Longword Write Access To 32-Bit Port Terminated with TEA Timing , . 20-25 Test Access Port Block Diagram , . 23-10 SRAM Bus Cycle Terminated by TEA
Freescale Semiconductor
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MCF5272UM 29F2G08 L9 zener 9.1 marking code p18 32768 68020 bsdl
Abstract: , barrel shifter, parallel multiplier/accumulator, and status register; (2) instruction fetch registers IC , provided in section 3.0. 1.1.8 INSTRUCTION FETCH REGISTERS The Instruction Counter (IC), Instruction A , the assistance of the ALU. The IC register, which holds a 16-bit address and points to the next , clocked during this interval, i.e., TCLK must be applied.] MAS281 Instruction Counter (IC) Zeroed , Register (FT) (Internal I/O Command, CUR,2001 H) Clear Instruction Counter (IC) e O. * 6. Disable Freescale Semiconductor
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21 1136

Abstract: CF5272 ise am p litu d e and gro u p d elay eq u alizers a re in te­ grated on a sin gle chip. 2 8 -P , m eans lim ited to im p lem en ting a H ayestype sm art m odem . Sierra is in the custom IC b u , ind ication, the off-h ook relay and d a ta /v o ic e re­ lay; th ese three lines conn ect to the , w e e n th e T h e S C 11007 and S C I 1008 are truly A S IC c o n tr o lle r s â'" th e y a re , th e lin e ; a rin g 1 -25 SC11004/SC11014 d e te c to r , ty p ic a lly a n o p to is o lator
Freescale Semiconductor
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21 1136 CF5272 rb 255t ap 1513 bc6 csr 0x00804000

ic tea 2025

Abstract: MCF5272 3.3 RF 61 3.4 RF IC _ , } } 1 A 1.7 antenna PA driver VCO IC bra912 Function PA/Driver Function , LNA 3rd stage LNA mixer H low IF amplifier low oscillator mixer BIAS IC IF , : NICEPACS CCC DDICE NICE:TEA6840H,TEA6845H,TEA6846H, NICEPACS:TEA6848H,TEA 6849H; CCC:TEF6901H,TEF6903H;DDICE:TEA6721HL AM LNA :DICE2:TEF6730HWCE : BF862 NXP 2: (IC
Motorola
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PQFP 80 14 0.65

ic tea 2025

Abstract: MUX31 in te­ grated on a sin gle chip. Built w ith S ierra's p rop rietary C M O S process that allow s , All o f th e p o p u la r c o m m u n ic a tio n s softw are w ritten fo r the PC will w ork w ith , ayestype sm art m odem . Sierra is in the custom IC b u sin ess and b oth chips w ere designed w ith this , r rin g ind ication, the o ff-h oo k relay an d d a ta /v o ic e re­ lay; these three lines co n , 8 /S C 1 1 0 3 7 S Y S T E M â'" R EFER T O A P P L IC A T IO N S IN F O R M A T IO N S FIG U R E S
Freescale Semiconductor
Original
develop 1531 iD
Abstract: S ysA D 2 2 123 S ysA D 5 4 124 V C C 125 V S S 126 R e tea se 127 S ysA D 2 3 128 S ysA D 5 5 129 , offered by the NR4650G is an atom ic "multiply-add" operation. "MAD", used to perform multip ly-a ccum u , memory management, facilitate debug, and speed real-time processing. 17 18 19 20-25 26 27 28 29 30 31 , 0 CE DE 1-»bootstrap Reserved, Set to 0. v in d ic a te s a soft reset or NMI has occurred. Reserved , IC DC 1101 1 1 1 1 1 1 1 1 1 4-39 J r nkk Field bystem clock ratio : 0 -> Processor -
OCR Scan
DS3563-3 MIL-STD-1750A MA17501 MA17502 MA17503
Abstract: (1)/IRQ7 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5/CINT , sp10 ARTRY/ TEA sp10 Data bus in normal mode sp10 Data bus in ECC and PARITY modes sp10 Pipeline mode , sp31 sp32 sp33a sp33b sp34 sp30 PSDVAL/TEA/TA sp30 ADD/ADD_atr./BADDR/CI/GBL/WT sp30 Data bus sp30 DP , . CLKin sp11 AACK/TA/TS/ DBG/BG/BR input signals sp11a ARTRY/TEA input signals sp12 DATA bus normal mode input signal sp15 All other input signals sp31 PSDVAL/TEA/TA output signals sp32 ADD/ADD_atr/BADDR/CI -
OCR Scan
SC11004CN SC11014CN SC11015
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