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CD4099BKMSR Intersil Corporation 4000/14000/40000 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDFP16, CERAMIC, DFP-16 visit Intersil
CD4043BKMSR Intersil Corporation 4000/14000/40000 SERIES, HIGH LEVEL TRIGGERED R-S LATCH, TRUE OUTPUT, CDFP16, CERAMIC, DFP-16 visit Intersil
CD4043BDMSR Intersil Corporation 4000/14000/40000 SERIES, HIGH LEVEL TRIGGERED R-S LATCH, TRUE OUTPUT, CDIP16, SIDE BRAZED, CERAMIC, DIP-16 visit Intersil
CD4099BDMSR Intersil Corporation 4000/14000/40000 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16, SIDE BRAZED, CERAMIC, DIP-16 visit Intersil
ISL54302IRZ-T Intersil Corporation 12V, 1.5? Quad SPST Switch with Latched Parallel Interface; QFN20; Temp Range: -40° to 85°C visit Intersil Buy
ISL54302IRZ Intersil Corporation 12V, 1.5? Quad SPST Switch with Latched Parallel Interface; QFN20; Temp Range: -40° to 85°C visit Intersil Buy

ic 74373 D latch

Catalog Datasheet MFG & Type PDF Document Tags

IC 74373

Abstract: function of latch ic 74373 (74373) Input from External Pins 8-Bit Input Latch(74373) Input from Internal Bus 8-Bit Output Latch , used. OUTPUT LATCHES LB U S O is a flow-through output latch similar to the 74373. The latch enable , - Vcc R l < 8190 D E V IC E ^ O U TPUT ^ 3350 : r 2 = TO T EST SYSTEM - C i (IN C LU D ES JIG CAPACITANCE) D EV IC E INPUT R IS E AND FALL T IM ES < 3ns P o w e r s u p p ly , as the d e v ic e o u tpu ts d is c h a rg e the load c a p a c ita n c e s T h e s e tra n sien ts
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EP1200

Abstract: (WS) 8-Bit Input Latch(74373) Input from External Pins 8-Bit Input Latch(74373) Input from Internal Bus RINP8 A RBUSLA LINP8 LBUSI LBUSO BUSX 8-Bit O utput Latch(74373) Output to , used. O U T P U T LATCHES LBUSO is a flow -through output latch sim ilar to the 74373. The latch , output latch. A truth table of the LBUSO function is shown in Figure 15E. 7 D ES IG N G U ID E L , (A) RS TO II T rs d , Read Strobe Delay (Delay to read the data from an Output Latch into
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IC 74ls244 latch

Abstract: pin diagram of ic 74373 . 8 PØ 8 ALE PSEN 8 3 8 A0-A7 LATCH 74LS138 8031 74373 When using the , 5x7 pattern and a single CMOS integrated circuit chip. The IC chip contains the column drivers, row , 0 1 1 D 0 1 1 1 E 1 1 1 1 F 6 1 0 0 0 1 8 5 1 1 1 1 0 7
Siemens
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IC 74ls244 latch pin diagram of ic 74373 IC 74373 IC 74373 pin diagram 74LS138 led matrix function of latch ic 74373 DLX713X DLO7135 DLG7137

LM 74138

Abstract: 74373 latch ic 1 0 1-533 82303 Address Latch Transparent Latch LATCH D [16:1 9] A [2 0 :2 3 ]P Q[1 6 :1 , 2G# 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 - O B U S Y ^>- -D>°- E R R O R ifO CLOCKED LATCH x 2 , 82304, 82303and 82077 Floppy Disk Controller Replace 50 IC's in IBM Design Integrated Parallel Port , form factor constraints by replacing 50 IC devices in an equivalent IBM system. The 82303 integrates , ) X D (0 :7 ) M IO # -1- H LM IO # + - L VGAMS# JLVG AM S# « - f CARD SETUP PORT BUS
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LM 74138 74373 latch ic ic 74373 D latch truth table for ic 74138 Latches 74373 pin DIAGRAM OF IC 74240 M60STR P103RD P103W P101RD CDSU06 CDSU18

82303

Abstract: reduce system cost, design effort, and form factor constraints by replacing 50 IC devices in an , MicroChannel M IO# indicator. The M IO # /L M IO # pin combination may be used as a general purpose latch if , a general purpose latch if LVGAMS# is not required. IOR#, IOW # 49,48 I 82303 read , Current ±1 0 (J.A Vss < VouT < V cc 2.4 V NOTES: 1. C D S U # [1:8], XA [0:2, 10:23 , :2,10:23] DLYfrom A D L# 1 35 100 Tu A [0 :2 ,10:23], VGAMS#, MIO# Setup to ADL# T T17
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82303

function of latch ic 74373

Abstract: full adder using ic 74138 | L = O V F O = 3, 2 = 3 mm V|H = V d D , V | L = 0 V F O = 3 ,2 = 3 mm tpdi B F IC tpdo , Dual 2-in put OR gate S-R N A N D latch S-R NOR latch Internal through driver-1 Internal through driver , -type latch w ith reset D -type flip flo p F lip flo p 1-50 DFR D -type flip flo p w ith , /reset and L S S D D-type latch Toggle flip flop with reset Toggle flip flop with set/reset 8 8 8 8 8 , U STD U SC D D F IN D F IC DCK DCKN DST D SC D STB D SC B D STD D SCD 1 1 1 1 1 1 1 1 1 1 1
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MSM70000 full adder using ic 74138 pins and their function in ic 74163 encoder IC 74147 74541 buffer 74373 cmos dual s-r latch sn 74373 MSM71000/72000/73000/74000 MSIW71000 MSM74000

IC 74373

Abstract: pin configuration of ic 74373 address #0FFFFh. - 10- W78E54B '^fctEiì3?F E le c t r o n ic s C o rp , D7 D6 D5 D 4D 3 D2 D , 1.7 W 7 8 E5 4 B / ?5 A12 / 74373 ^A1Q ? 1 4 v i 1 23 /A12-2. , W78E54B i.lV in b o n d E lectronics Corp. 8-BIT MTP MICROCONTROLLER GENERAL DESCRIPTION , : January 1999 Revision A2 W78E54B E le c tr o n ic s C o r? PIN CONFIGURATIONS 40-Pin DIP , 44-Pin PLCC (W78E54BP) T 2 E T X 2 / I N T 3 P D 4 n P1.5 c P1.6 c P1.7 c RST c RXD, P3.0 c INT2, P4
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pin configuration of ic 74373 DD 127 D w78e54b-24 table 74373 ic 74373 IC S2-57S S-S43SS

ic 74226

Abstract: jk flip flop 74103 RICOH CORP/ ELECTRONIC 1SE D 7 7 4 4bTO 0G0Q7Qt, b RICOH RP3G01 0 2 GENERAL DESCRIPTIO N T h e R P 3 G 01 and R P 3 G 0 2 a r e A n a lo g /D ig ita l se m ic u s to m g a te a r r a y s fa b r ic a te d w ith m e ta l g a te B i-C M O S p ro cess. T h e R P 3 G 0 1 and R P 3 G 0 2 c o n , g b ip o la r e le m e n ts and lo w -p o w e r d is s ip a tio n d ig ita l c ir c u it e m p lo y in g th e C M O S l o g i c , b o t h o f w h ic h a r e in te g r a te d o n o n e c h ip . A s t h
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ic 74226 jk flip flop 74103 ic D flip flop 7474 7471 rs flip flop 4011 flip flop IC 7400 SERIES list 3W1X879 00GG71S

a73n

Abstract: 3702S W78LE812 i.lV in b o n d E le c tro n ic s C orp . 8-BIT MTP MICROCONTROLLER GENERAL , Release D ate: February 1999 Revision A2 W78LE812 E le c tr o n ic s C o r? PIN CONFIGURATIONS , Publication Release D ate: February 1999 Revision A2 W78LE812 '^fctEiì3?F E le c t r o n ic s C o rp , Pointer Port 0 Latch P O .O e 3 - t P0.7 I a-5 T s'S iiiS i-'l "I i t t D P T R iT e m p f , .5 INT8.P1.B INT9.P1.7 RST A9CTRL.RXD, P3.D A13CTR.LTXD, P3.1 A14GTRLJNTD, P3.2 oectrl,intT 7 p3.3 T D , P3
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3702S a73n 357S5 S-2-27- S85-2-S7 SC505

interfacing of RAM and ROM with 8085

Abstract: IC 74373 integrated circuit chip. The IC chip contains the column drivers, row drivers, 128 character generator ROM , 1 9 0 1 0 1 A 1 1 0 1 B 0 0 1 1 C 1 0 1 1 D 0 1 1 1 E 1 1 1 , Figure 7. Block diagram for 8-digit DLO4135/DLG4137 8 ALE PSEN 74LS138 8 PØ 74373 , P1,A R3,START 8 3 8 A0-A7 Eight DLX413X 8080 or 8085 System DECODER LATCH OE , ,DADD D,DPAD B,LEN A,M M,A D H B DISP1 ; ; ; ; ; ; ; ; ; ; DATA TO BE DISPLAYED
Infineon Technologies
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interfacing of RAM and ROM with 8085 74LS244 buffer ic 74373 datasheet IC 74ls244 latch datasheet 8085 microprocessor hex code 8085 hex code DLO4135 DLG4137 1-888-I

82306

Abstract: 74590 -7 5 H . REAL TIM E CLOCK ADDRESS LATCH ENABLE. REAL TIM E CLOCK R E A D /W R IT E STROBES. PARALLEL , Reset Pulse W idth R C # Pulse W idth TM RCLK H ig h /L o w Time P IC C S #, F D A C K # Setup P IC C S , B1 CLK RAMD6 RAMD5 D PRE# CLR# RAMPO CLOCKED LATCH Q 0# CHRDY LSI# D " XDO (- 1 > ° - , Package High-lntegration-The 82304, 82303 and 82077 Floppy Disk Controller Replace 50 IC's in IBM , , significantly reduce system cost, design effort, and form factor constraints by replacing 50 IC devices in an
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82306 74590 8259 Programmable Peripheral Interface IC 8259 internal pin diagram pin diagram of 74245 BUFFER IC 74245 BIDIRECTIONAL BUFFER IC RAMD11 RAMD12

interfacing of RAM and ROM with 8085

Abstract: IC 74ls244 latch a single CMOS integrated circuit chip. The IC chip contains the column drivers, row drivers, 128 , 0 1 8 1 0 0 1 9 0 1 0 1 A 1 1 0 1 B 0 0 1 1 C 1 0 1 1 D 0 1 , DECODER LATCH OE EPROM 27xx Data I/OW A0 A1 Address A2 Decoder 8 ALE 74LS138 8 PØ 74373 8031 ORL ORL MOV MOV MOV START: INC DATA: MOV OUTL MOV RR MOV WRITE , INX INX DCR JNZ RET H,DADD D,DPAD B,LEN A,M M,A D H B DISP1
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8080 intel microprocessor pin diagram interfacing of ram with 8085 IC 8085 pin diagram c program for 8*8 DOT LED MATRIX display 8085 Function Generators pin diagram of LED dot matrix display 5x7 using d

IC 74373

Abstract: matrix de led 5x7 LATCH 74LS138 8031 74373 When using the DLX713X on a separate display board having more , arranged in a 5x7 pattern and a single CMOS integrated circuit chip. The IC chip contains the column , 1 1 0 1 B 0 0 1 1 C 1 0 1 1 D 0 1 1 1 E 1 1 1 1 F 6 1 0 0
Infineon Technologies
Original
matrix de led 5x7 block diagram of 74LS138 1 line to 16 line IC 74ls244 74ls244 latch siemens appnote 36 001B

eb 102H

Abstract: latch and subsequently clear keyboard and mouse interrupts. S Y STEM S T A T U S AN D C O N T R O L , effort, and form factor constraints by replacing 50 IC devices in an equivalent IBM system. The 82304 , Reference Manual, 82077 data sheet, and 8259A data sheet. CA R D SETUP PORT SUPPORT The 82304 provides , edge-triggered mode is integrated. BU S IN TERFACE AN D C O N T R O L The Bus Interface and Control unit , 3F0-3 F 7H . The 82304 also inputs the 82077â'™s D M A acknowledge in support of the system feedback
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eb 102H

IC AND GATE 7408 specification sheet

Abstract: 74LS96 |d create an ED IF file with V iew log ic softw are, the fo llow ing a pplicatio ns are required: LI , ic Edito r or Text Editor and then m ap it in an LMF. Figure 3 d em onstra tes this process. D , 0 0 Allow s M A X 5000 E P L D designs to be created with workstation C A E tools and transferred to M A X + P L U S for com pilation; com piled designs can b e retu rned to the w o rk s ta tio n for d , functions. Altera EDIF netlist w'riter produ ces post-synthesis logic and delay in fo rm a tio n used d u
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IC AND GATE 7408 specification sheet 74LS96 74LS183 SN 74168 7486 XOR GATE IC 74LS192

truth table for ic 74138

Abstract: 16CUDSLR Sim ulator (FS1M) V irtual Logic A nalyzer (VLA) Log ic M a p II p rog ra m m i ng so ft w a re D ocum , achine, tru th table, and netlist design entry. These en try m eth o d s can be com bined, allow ing the desig n er to choose the m ethods that best suit each design. Figure 1 show s a block d iagram of A+PLUS , produce an in d u stry -sta n d a rd JEDEC File (.JED) for EPLD p ro g ra m m in g . T he A D P im p lem , . The ADP also p ro d u ces docu m entation th at show s m inim ized logic and EPLD utilization. A+PLUS
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16CUDSLR ALU IC 74183 IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184

74191, 74192, 74193 circuit diagram

Abstract: IC 7402, 7404, 7408, 7432, 7400 , ver. 3 Data Sheet LI Software support for Classic, M A X 5000, M A X 7000, and ST G E P L D s Runs on H ew lett Packard /A p o llo Series 3000, 3500, 4000, 4500, and HP400 computers w ith D o m ain , Schematic capture w ith Mentor G raphics' N E T E D software A H D L supporting state machines, Boolean , cross-compatibility via bidirectional E D IF 2 0 0 netlist interface Logic synthesis and m inim ization for efficient , designs among m ultiple E P L D s Generates post-synthesis timing simulation data for use w ith Logic
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74191, 74192, 74193 circuit diagram IC 7402, 7404, 7408, 7432, 7400 Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions IC-24 QIC-24

74373 cmos dual s-r latch

Abstract: 74373 verilog ill d eliver the best perform ance and the desired I/O interface. SEC A S IC 0.5^,171 Processes , er dissipation ( P DC) and d ynam ic pow er d issipation (P AC). P TOTAL = P d C + PAC , LD 6 LD 6D 2 LD 7 LD 7D 2 LD 8 LD 8D 2 LD S2 LD S6 LSO LS0D2 LS1 LS2 D Latch w ith A ctive High D Latch w ith A ctive High, 2X Drive D Latch w ith A ctive High, Scan D Latch w ith A ctive High, Scan, 2X Drive D Latch w ith A ctive High, Q O u tp u t O nly D Latch w ith A ctive High, Q O u tp u t Only, 2X
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74373 verilog A022A 74152 PIN DIAGRAM application of ic 74153 T749 LN 741 KGL80 VSS30 VSS30I VSS30P VSS50

16CUDSLR

Abstract: 7474 D flip flop free PL D s H ierarch ical d esig n entry m eth o d s for b oth g rap h ic and text d esig n s M u , , arithm etic and relational op eration s D elay p red iction and tim ing an aly sis fo r g ra p h ic an d , rap h ic D esign Files (.G D F) w ith the M A X + P L U S G ra p h ic Editor, and T ext D esign Files , Editor. T h e G ra p h ic E d itor offers ad van ced featu res such as m u ltiple h ierarchy lev els, sy , G rap h ic and T ext E d ito rs w ith the d elay p red ictio n featu re. A fter the so u rce and d
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7474 D flip flop free alu 74382 pin diagram of ic 74190 ALU IC 74381 HFJV1 MUX 74151

buffer 74244

Abstract: W81E381 3.1.1 48- pin LQFP package pin description TYPE PWR PWR PWR I/O I/O I O I X I L I/O D I/O I/O I , oscillator is running resets the device. SYMBOL USB Pins AVDD AVSS V33 D+ DXTALI XTALO Extra Pins PLLEN uC , 74373, or a buffer input port like an on-chip 74244. I/O H I O PWR PWR 34,35,42,43, PORT 3 , : input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain, PWR: Power pins, X , USB Pins AVDD AVSS V33 D+ DXTALI XTALO SCPWR SCIO SCCLK SCRST SCPRSNT Extra Pins PLLEN XCVREN SOFTCNEN
Winbond Electronics
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buffer 74244 W81E381-Y P10-12
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