NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 1:1 +/- 2% 100Khz 4.0V pk Hi  Pot 1.5KV 1Sec ISDN Line Transformer Tx Measurement , ) 0.6uH Max 100Khz 0.1V Turns Ratio 1:1 CT +/- 2% 100Khz 4.0V pk Hi  Pot 1.5KV , Mode Choke Measurement Value Tolerance Test Parameters Inductance (Tip) 37.8uH +/- , [7.62] PACKAGING 0.039 [1.00] 0.433 [11.00] Recommended PCB Layout Tape Format Tape , DIRECI N FEED T O OF COVR AP E T E 65 WIDE Ø1 .50 20 .00 2.0 0 +/- 0.15 4.0 0 ... | Original |
3 pages, |
FOOTPRINT PCB fuse CHOKE 0.6uH smd transistor NJ hi pot test pcb GR1089 EN300 GR1089 abstract |
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| Abstract: ) - DPM 116 Specification IN HI (7) + 2V 20V 200V 2kV 200uA 2mA 20mA 200mA , V+ V+ ±200mV IN HI 6 V+ 7 IN HI + 8 - 510K 7 14V max 7V min IN LO , of 200mV full scale. 6 V+ 7 IN HI + V1 8 IN LO R= 0.2 IFSR V2 V5 VCheck Link , without prior warning 6 V+ + 7 IN HI 8 IN LO - IN HI 8 IN LO V5 V- Measuring a supply voltage. (min. 7.5V, max. 14V). V+ 6 IIN 7 IN HI V+ V+ 100K 6R2 + ... | Original |
2 pages, |
hi pot test pcb dpm 116 datasheet abstract |
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| Abstract: V+ + 11 XDP Vin BAT 9 - TEST Vref BC 237 - V- 470K Driving , closed + 8 V+ 3 IN HI 1M 4 5 Normal 2 6 5 V+ IN HI IN LO REF HI 8 1M V+ 6R2 10nF Out 2 IN LO 4 REF HI 5 REF LO V1 Check Link REF is closed + Æ , - 7660 5 3 + - 8 V+ V+ IN HI Check Link REF is closed + 0-200mV IN LO - , g REF LOW V+ GND TEST BAT XDP 17.5 (0.69) 11 ° REF Hi f e 1 h ... | Original |
4 pages, |
BCX19 119340 3.5 digits lcd display low bat datasheet abstract |
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| Abstract: 1.0 OHMS MAXIMUM PINS:(3-6)=1.2 OHMS MAXIMUM 4. HI POT: PINS(1,4,2)T0(J 1 ,J2)= 1500VAC 1500VAC FOR 60 SECONDS , a o o Y< 8.89 gu lO O Ojg OOjOOO OOjOOO OOjO ^-I a 13,98 .1. 13,98 1 13,98 19- D1 + - -o o °D2 D3Î -D4 7.85 12.93 + - o o o o + - 53.34 J o < I 'f 4 01.60(3) / 00.90(40) a ^ o el + - o o o o + -> Y>t \ 01.60(2) 58.9 o «-tri inT ° \03.2O(2) 01.00(16) 59.10 TOP PANEL GROUND 21.35 2.28 4.06 SUGGESTED PCB , TEST NDTES:(25±5*C) 1 .TR:(100KHz,0.1V); PINS:(1-2):(J1-J2)= 1:1 ±3% PINS:(3-6):(J3-J6)= 1:1 ±3% 2.LX ... | OCR Scan |
2 pages, |
PD-23 8P10C- datasheet abstract |
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| Abstract: and bottom layout of the test PCB. C7 100nF C8 100nF VCC PSIN PSIN VDD iC-NV , VDD SIN + iC-NV RCLK NSIN + A INPUT SIN PCOS B + Z - NCOS COS + CONVERSION CORE INPUT COS PZERO + NZERO DIGITAL PROCESSING VCC VCC , (VDD) Supply Current in VDD fin()= 200kHz; A, B, Z open 004 Vc()hi Clamp Voltage hi at NSIN, PSIN, NCOS, PCOS, NZERO, PZERO, SG1, SG0, ROT, SF1, SF0, VREF, RCLK Vc()hi= V() -VCC; I()= ... | Original |
12 pages, |
INTERPOLATOR SIN COS G008 G003 datasheet abstract |
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| Abstract: circuitry to power and test all of its compatible audio power amplifier EVMs and thus eliminate the need , mode/mute jumper circuitry (JP6, JP7, JP8). To begin with, set JP7 to Lo, JP8 to Hi, and JP6 to Mode. , + C6 C3 C5 DL R1 OUT- 4861 C2 U1 R2 C4 C1 GND OUT+ R3 IN+ , ultra-low current mode. u Gain Control Pot R4 Lower gains produce better distortion performance (see , Shutdown (+ VDD to Mute) Shutdown 2 Bypass GND IN + VDD 6 4 IN - Vo + C5 ... | Original |
18 pages, |
TPA4861D tpa4861 TPA4860 TPA302 3323p-1-204 application note audio amplifier C3216X5R1A225 AUDIO AMPLIFIER SCHEMATIC tpa4861 hear stereo to 5.1 converter circuit diagram "power factor correction" schematic PIC TPA4861 SLOU004 TPA4861 abstract |
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| Abstract: circuitry to power and test all of its compatible audio power amplifier EVMs and thus eliminate the need , mode/mute jumper circuitry (JP6, JP7, JP8). To begin with, set JP7 to Lo, JP8 to Hi, and JP6 to Mode. , + C6 C3 C5 DL R1 OUT- 4861 C2 U1 R2 C4 C1 GND OUT+ R3 IN+ , ultra-low current mode. u Gain Control Pot R4 Lower gains produce better distortion performance (see , Shutdown (+ VDD to Mute) Shutdown 2 Bypass GND IN + VDD 6 4 IN - Vo + C5 ... | Original |
17 pages, |
TPA4861D TPA4861 TPA4860 TPA302 stereo to 5.1 converter circuit diagram SLOU004 TPA4861 abstract |
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| Abstract: the test PCB. C7 100nF VCC PSIN PSIN VCC, VDD C8 100nF VDD iC-NV SIN , processing Sensor bridge calibration supportable by analog/digital test signals Low power consumption from , sensor systems PACKAGES TSSOP20 TSSOP20 BLOCK DIAGRAM VCC PSIN VDD SIN + RCLK TRANSITION DISTANCE PRESET - - NSIN + A INPUT SIN PCOS B + Z - - NCOS COS + PZERO TRANSITION DISTANCE CONTROL CONVERSION CORE INPUT COS + NZERO ... | Original |
18 pages, |
photodiode sin INTERPOLATOR SIN COS G008 G003 ET2010 "MR sensor" so20w signal 11uA incremental for TTL datasheet abstract |
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| Abstract: DAC1136/1138 DAC1136/1138 deliver exceptional accuracy for a broad range of display, test and instrumentation , includes 1000 hour stability data for the reference zener and linearity test data. MSB 1 BIT 2 2 BIT 3 3 , Diagram and Pin Designations DIGITAL-TO-ANALOG CONVERTERS VOL. II, 10-27 CDPPIPIP AT I ft M C ^p'cal @ + , 0mA - 1mA to + 1mA 0 to + 5V, 0 to +10V, ± 5V, ± 10V DIGITAL INPUTS TTL/CMOS; See Figure 2 , ) Voltage(ZOur-200!!) Noise (BW = 0,1-lOHz) Tempco + 6.000V(MaximumError, ±0.024V) 3(iV pk-pk 5ppm/°C ... | OCR Scan |
8 pages, |
Model 234L in753a DAC1138 AD542K 74LS 234L DAC1136 C1136 DAC1136/1138 DAC1I38 DAC1133K DAC113SK DAC1136/1138 abstract |
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| Abstract: case of pot., mounted to P.C.B. only with terminals. O 2 kgf*cm over : In case of pot., mounted to , Maximum operating voltage : A.C.150V » D-c- ' 10v 6- Dielectric test : Units shall be designed to , -f-H- -j-i- -ff hi- -I. • î . - f-^-T- ^- ., ,i. j -r~: px: . : . 1 â- î â- 1 , î PERCENT VOLTAGE CHECK POINT SO% TRAVEL FROM TERM. 1 80 TOLERANCE 10-25 + 100 TERM.3 APPD. /I , force + 100 gf max (Note 1) Measuring temperature : 5*C - 35*C Measuring point : mm from lever end ... | OCR Scan |
8 pages, |
potentiometer alps alps rs6011 alps potentiometer SSV96-0312 RS6011Y14 SSV96-0312 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| Molex - Modular Jack - Vertical, Standard Profile for .062 and .125 PCB, 42410 Modular Jack - Vertical, Standard Profile for .062 and .125 PCB, 42410 Features and Benefits Meets UL 1086 Section 8 Electrical Probe and UL 1863 Section 20 Childs Finger Test No exposed leads to meet British Telecom 4000V test Contact tips guided wiTHin FCC-specified target zone-Positive alignment prevents shorting 100% tested for hi-pot and continuity Reference Information Product Specification: PS www.datasheetarchive.com/files/molex/docs/wcd00004/wcd004ad.htm |
Molex | 30/06/1999 | 6.13 Kb | HTM | wcd004ad.htm |
| Molex - Modular Jack - Vertical, Low Profile, for .062 and .125 PCB, 42878 Modular Jack - Vertical, Low Profile, for .062 and .125 PCB, 42878 Features and Benefits Meets UL 1086 Section 8 Electrical Probe and UL 1863 Section 20 Childs Finger Test No exposed leads to meet British Telecom 4000V test Contact tips guided within FCC-specified target zone-Positive alignment prevents shorting 100% tested for hi-pot and continuity .500 height is industry lowest Reference www.datasheetarchive.com/files/molex/docs/wcd00004/wcd004a8.htm |
Molex | 30/06/1999 | 5.64 Kb | HTM | wcd004a8.htm |
| Molex - Modular Jack - Vertical for .062 PCB, 42410 Saved by the Datasheet Archive: 20/12/1997 Modular Jack - Vertical, for .062 PCB, 42410 Features and Benefits Meets UL 1086 Section 8 Electrical Probe and UL 1863 Section 20 Childs Finger Test No exposed leads to meet British Telecom 4000V test Contact tips guided within FCC-specified target zone-Positive alignment prevents shorting Every jack must pass on-line functional tests, including hi-pot and continuity All packaging www.datasheetarchive.com/files/molex/docs/00004/00409.htm |
Molex | 20/12/1997 | 7.44 Kb | HTM | 00409.htm |
| Molex - Modular Jack - Low Profile, for .062 PCB, 42878 Saved by the Datasheet Archive: 20/12/1997 Modular Jack - Low Profile, for .062 PCB, 42878 Features and Benefits Meets UL 1086 Section 8 Electrical Probe and UL 1863 Section 20 Childs Finger Test No exposed leads to meet British Telecom 4000V test Contact tips guided within FCC-specified target zone-Positive alignment prevents shorting Every jack must pass on-line functional tests, including hi-pot and continuity All packaging www.datasheetarchive.com/files/molex/docs/00004/00408.htm |
Molex | 20/12/1997 | 7.46 Kb | HTM | 00408.htm |
| on-line functional tests, including hi-pot and continuity Reference Information PCB Right Angle Flangeless Modular Jack: 41687 Saved by the Datasheet Archive: 20/12/1997 Modular Jack PCB - Right Angle Flangeless, 41687 Features and Benefits 50 " Gold meets FCC 68 requirements Keying options available Top-covered leads meet British Telecom 4000V test : -40 to +80°C DRAWING: Top, Front, Side View and PCB Layout Preferred Version in the www.datasheetarchive.com/files/molex/docs/00006/0068f.htm |
Molex | 20/12/1997 | 6.79 Kb | HTM | 0068f.htm |
| on-line functional tests, including hi-pot and continuity Reference Information Product PCB Right Angle Flush Mount Modular Jack: 41369 Saved by the Datasheet Archive: 20/12/1997 Modular Jack PCB - Right Angle Flush Mount, 41369 Features and Benefits 50 " Gold meets FCC 68 requirements Keying options available Top-covered leads meet British Telecom 4000V test : See Table Temperature: -40 to +80°C Drawing: Top, Front, Side View and PCB www.datasheetarchive.com/files/molex/docs/00003/003fc.htm |
Molex | 20/12/1997 | 7.03 Kb | HTM | 003fc.htm |
| Surface mount compatible 100% tested for hi-pot and continuity Duplex-plated 50 " Gold meets FCC part 68 requirements Meets UL 1863 Sec. 8 Electrical Probe and UL 1863 Sec. 20 Child Finger Test +80 C Drawing: Top, Front, Side View and PCB Layout ORDERING INFORMATION AND www.datasheetarchive.com/files/molex/docs/00003/003fa.htm |
Molex | 20/12/1997 | 5.24 Kb | HTM | 003fa.htm |
| -circuit jacks Surface mount compatible 100% tested for hi-pot and continuity Duplex-plated 50 " Gold Test Reference Information Product Specification: PS-43202 PS-43202 PS-43202 PS-43202 Packaging: Anti-static trays Temperature: -40 to +80 C Drawing: Top, Front, Side View and PCB Layout ORDERING INFORMATION www.datasheetarchive.com/files/molex/docs/00003/003f6.htm |
Molex | 20/12/1997 | 5.75 Kb | HTM | 003f6.htm |
| on-line functional tests, including hi-pot and continuity Reference Information Product Modular Jack - Right Angle, Standard Profile, Flush Mount 41369 Modular Jack - Right Angle, Standard Profile, Flush Mount, 41369 Features and Benefits 50 " Gold meets FCC 68 requirements Keying options available Top-covered leads meet British Telecom 4000V test : See Table Temperature: -40 to +80°C Drawing: Top, Front, Side View and PCB www.datasheetarchive.com/files/molex/docs/wcd00004/wcd0049b.htm |
Molex | 30/06/1999 | 6.74 Kb | HTM | wcd0049b.htm |
| Telecom 4000V test Contacts are duplex plated after stamping, eliminating bare edges in the mating area Every jack must pass on-line functional tests, including hi-pot and continuity tails Temperature: -40 to +80°C Drawing: Top, Front, Side View and PCB Layout www.datasheetarchive.com/files/molex/docs/wcd00004/wcd0049e.htm |
Molex | 30/06/1999 | 6.59 Kb | HTM | wcd0049e.htm |