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CS5376A-IQZR Cirrus Logic Highly Integrated, Multi-Function 4-Channel Decimation Filter visit Digikey Buy
CS5529-ASZR Cirrus Logic Converters - Analog to Digital (ADC) IC Prgrmbl Dlt Sigma ADC w/6-Bit Latch visit Digikey Buy
CS5372A-ISZ Cirrus Logic Telecom Circuit, 1-Func, PDSO24, LEAD FREE, SSOP-24 visit Digikey Buy
CS5371A-ISZ Cirrus Logic Telecom Circuit, 1-Func, PDSO24, LEAD FREE, SSOP-24 visit Digikey Buy
CS42436-DMZR Cirrus Logic Consumer Circuit, CMOS, PQFP52, LEAD FREE, MS-022, MQFP-52 visit Digikey Buy
CS4270-CZZR Cirrus Logic Consumer Circuit, PDSO24, 4.40 MM, LEAD FREE, MO-153, TSSOP-24 visit Digikey Buy

function of latch ic 74138

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: commonly used TTL SSI and MSI functions. These aid the first time user since the function of these blocks , is shown in the final figure of this data sheet. The functions included are; 7485 74279 74151 74138 74157 - 4 bit magnitude comparator - quad S-R latch - 8 input multiplexer - 1 of 8 decoder - quad 2 , there are detailed logic diagrams (along with the LogiCaps Macro symbol and function table) for some of , EP1800 to allow maximum access to each function. However, the internal logic capabilities of this design -
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full adder using ic 74138 full adder using Multiplexer IC 74151 decoder IC 74138 TTL 74194 74151 multiplexer pin configuration of IC 74138 EP1800JC-EV1 0UT20 0UT21 OUT22 0UT23 OUT10
Abstract: to be used bi-directionally. This signal is a function of the Control port direction bit (bit 5) and , 82304, 82303and 82077 Floppy Disk Controller Replace 50 IC's in IBM Design Integrated Parallel Port , form factor constraints by replacing 50 IC devices in an equivalent IBM system. The 82303 integrates , signals in support of system setup functions. A ( 0 : 2 , 1 0 : 2 3 ) - r X A ( 0 : 2 , 1 0 :2 3 , address latches, and a variety of system board setup functions. The 82303, in conjunction with its sister -
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LM 74138 74373 latch ic ic 74373 D latch function of latch ic 74373 truth table for ic 74138 specifications of 74373 latch ic M60STR P103RD P103W P101RD CDSU06 CDSU18
Abstract: Functions) Mentor Graphics Function AND# BUF DELAY DFF INV JKFF LATCH NAND# NOR# OR# XFER XNOR2 XOR2 , file. For each C N F , a Ffierarchy Inte rconnect File (.HIF) and a G raph ic Design File (.GDF) are , logic schem atic in the M A X + P L U S Graph ic Editor. Altera Corporation Page 320 Data Sheet , design logic solely with w orkstation C A E tools, or to mix design inputs from a variety of platforms , meet their needs. L M F s are used with the Altera ED IF Netlist Reader to convert functions of -
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IC AND GATE 7408 specification sheet 74LS183 74LS96 7486 XOR GATE SN 74168 IC 74LS192
Abstract: '¢ Internal Basic Block Table (69 types) Type No. Function block name Logic function Max. No. of fan-outs ,   b72M24Q GGDÃ244 T â  t-42-41 Type No. Function block name Logic function Max. No. of ' fan-outs Delay , block name Logic function Max. No. of fan-outs Delay time tpd^ns) 1-55 TFRE Toggle Rip Flop with , '" Type No. Function block name Logic function Max. No. of fan-outs Interface level TTL CMOS , -42-41 Type No. Function block name Logic function Max. No. of fan-outs Interface level TTL CMOS -
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IC 3-8 decoder 74138 pin diagram Multiplexer IC 74151 ic 74151 ic 74148 block diagram MSI IC 74138 decoder Demultiplexer IC 74154 MSM91H000 72MS40 DQQ023 MSM70H000 MSM70H00
Abstract: MB66xxxx MB67xxxx F-MACROS F-Macros are created and offered by Fujitsu to emulate the function of popular , function of many popular Industry-standard TTL devices and RAM macros which provide from 1K to 2K of , Fujitsu MB65xxxx/MB66xxxx/MB67xxxx family are a series of high performance CMOS gate arrays designed to , , 2304 bits of RAM, 4608 bits of ROM or for bus Interface circuits with hlgh-drtve requirements. The AVB , Interfacing with bus organized loglc.The AVM (MB66xxxx) series of memory arrays Include, In addition to the -
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up down counter using IC 7476 74154 shift register IC sk 7443 DN 74352 74183 adder 74169 pin configuration 0010S MB65XXXX MB66XXXX MB67XXXX
Abstract: =1) D1 is the value of the v a ri able length output delay. Functional Summary Function FIR Filter , latch to the slave or active latch. There are three methods of perform ing these operations: The firs t , tim e, a new coe fficie n t on bus Cl is loaded into the m aster latch of the filte r cell w hose , precision of a 1-D or 2-D filte r is expandable using more L64230 processors w ith minimal external logic , clip the output to a single bit. Data throug hpu t of 20 MHz (WCCOM) makes the processor suitable fo r -
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74138 decoder A3029 L64210/L64211 L64200 155-P MIL-STD-883C
Abstract: File-Primitives Mentor Graphics Generic Function AND# BU F DELAY DFF INV JK F F LATCH NAND# NOR# OR# XFER XNOR2 XOR2 MAX+PLUSII Primitive Function AND# SC LK M C ELL DFF2 NOT JK F F 2 MLATCH NAND# NOR# OR# TRI , pplications for the most up-to-date list of m appings. Table 2. Mentor Graphics Library Mapping File-Macrofunctions (P arti of 3) Mentor Graphics 74LSTTL Function 74LS00 74LS02 74LS04 74LS08 74LS10 74LS11 74LS20 , /HP Data Sheet Table 2. Mentor Graphics Library Mapping File-Macrofunctions (Part 2 of 3 -
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74191, 74192, 74193 circuit diagram IC 7402, 7404, 7408, 7432, 7400 Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions HP400 IC-24 QIC-24
Abstract: truth table C om plete sym bol library of basic gates and over 120 TTL m acro functions S u p p o rt for , cycles Elim ination of un u sed gates A utom atic pin and p art assignm ents SALSA logic m inim ization , Easy definition of in p u ts w ith state tables, vector patterns, or predefined patterns State table or , desig n er to choose the m ethods that best suit each design. Figure 1 show s a block d iagram of A+PLUS. A+PLUS includes the A ltera Design Processor (ADP), w hich consists of integ rated m od u les that -
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16CUDSLR IC 74151 diagram and truth table ALU IC 74183 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184
Abstract: name Logic function No. of unit cells (No. of gates) 11 13 10 12 8 3 3 1 1 4 4 6 4 10 11 13 15 3 , U F IC UCK UCKN U ST u se U STB U SC B Logic function Through input buffer Through input buffer , block table Type No. Functional block name U SCB Logic function No. of buffer cell 1 TTL CMOS TTL CMOS , interface block table Type No. Functional block name BC B C IC BCST BCSC BC SD BC SE Logic function Through , > Logic function Equivalent T T L code 7442 7485 7491 7492 7 493 7494 7 495 74138 1/2 74 13 9 -
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MSM70000 pins and their function in ic 74163 encoder IC 74147 74373 cmos dual s-r latch MSM7000 sn 74373 74541 buffer MSM71000/72000/73000/74000 MSIW71000 MSM74000
Abstract: CELL An unprogrammed gate array is an array of b a s ic c e lls . Thus the "gates" in a gate array are , of a user macro is that it allows the designer to compose a macro function from unit cells once, then , F-Macros are created and offered by Fujitsu to emulate the function of popular industry-standard TTL , s c rip tio n . The logic description defines the logical function of the circuit to be implemented , duplicate the function of many popular industry-standard TTL devices and RAM macros which provide from 1K to -
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and pin diagram of IC 7491 circuit diagram for IC 7483 full adder application of ic 74153 ic 74139 decoder pin diagram IC 74195 pin diagram of ic 74190 C4002 C1502
Abstract: o ta l D o se . D E S IG N A D V IC E Although the use of the MBRT Library guarantees total , function of total dose level. Each cell has its own total dose parameters. By simply indicating the total , CHIP SPECIAL FUNCTION - test mode E X T E N S IV E M A C R O L IB R A R Y IN C L U D IN G OVER 150 , process features effective channel length of 1.5 n for both N and P tran sisto rs, and achieves operating speeds up to 30-35 MHz at 70 Krads (Si) with the inhe rent low power consumption of CMOS technology -
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transistor KD 617 ic 7442 encoder 0850R ttl ic 7485 ttl 7442 fan out 74283 BCD adder 0850RT 1300RT 2000RT 2700RT 3200RT 4000RT
Abstract: n c tio n E q u iva le n t T T L code 7442 7485 7491 7492 7 4 93 7494 7 4 95 74138 N o. of u n it , slice m e th o d using the high p erfo rm a n c e silicon gate 2 m ic ro n H C M O S process w ith th e , o f th e s c h m itt trigger, c ry s ta l/ ceram ic o r C R o sc illa to r, p u ll-u p /p u ll-d o w , using any intern al gate, w h ic h are g reatly required by custom ers. In a d d itio n , th e I/O in p , n o f the n u m b e r o f gates and the n u m b e r o f pads (the n u m b e r o f p in s), w h ic h -
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74138n buffer 74374 G701 of IC 74191
Abstract: aster latch to the slave or active latch. There are three methods of perform ing these operations , . During this time, a new coe fficient on bus Cl is loaded into the m aster latch of the filte r cell w , precision of a 1-D or 2-D filte r is expandable using more L64230 processors w ith minimal external logic , on chip to clip the o u p u tto a single bit. Data throughput of 20 MHz (WCCOM) makes the processor , , tem plate matching, ero­ sion and dilation Compatible w ith the L64200 fam ily of products 1024 -
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Abstract: PL D s H ierarch ical d esig n entry m eth o d s for b oth g rap h ic and text d esig n s M u , , arithm etic and relational op eration s D elay p red iction and tim ing an aly sis fo r g ra p h ic an d , create, verify, and program com p lex logic d esig n s. Figure 1 sh o w s a b lock d iagram of M A X +P L , ith a variety of d esign entry m ethods. M A X +P L U S su p p orts hierarch ical en try o f b oth G rap h ic D esign Files (.G D F) w ith the M A X + P L U S G ra p h ic Editor, and T ext D esign Files -
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7474 D flip flop free alu 74382 HFJV1 IC 74373 truth table CI 7446 ALU IC 74381
Abstract: consider the testability of the circuit with as much care as the function of the circuit itself. There are , Survey (Selection) (cont'd) Cell Name Function No. of core cells (Equivalent Gates) 5 5 *) 7 9 8 10 9 11 , MUX41H M150C M151C CB4C CB41 CUD42 M160C M161C M162C M163C PS4 Function No. of Equivalent Gates 20 45 14 , Propagation delays of the SCxD4 series are a function of several factors, namely · Fanout · Interconnection , 0 M H z , has 2 2 in p u ts a n d 4 0 o u tp u ts of w h ic h 10 are of 4 m A d riv e s tre n g th a -
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74LS82 74245 BIDIRECTIONAL BUFFER IC ic 4583 schmitt trigger core bit excess 3 adder using IC 7483 la 4508 ic schematic diagram advantages for ic 7473 TC140G SC12D4 SC18D4 SC27D4 SC37D4 SC44D4
Abstract: method that uses a ring of registers at an IC's boundary to control and monitor access during testing , expectations." CDS is a trademark of Crosspoint Solutions, Inc. Macintosh is a registered trademark of Apple Computer, Inc. UNIX is a registered trademark of AT&T Technologies, Inc. Verilog is a registered trademark of Cadence. DEC is a registered trademark of Digital Equipment Corporation. Exemplar is a trademark of Exemplar Logic, Inc. HP is a registered trademark of Hewlett Packard, Inc. Apollo is a registered -
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74151 MUX 8-1 full subtractor using ic 74138 pin configuration IC 74151 modulo 16 johnson counter MUX 74151 MUX 74157 CP20K CP20420
Abstract: as the function of the circuit itself. There are two main objectives in designing for testability , Features Table 3 a Primitive Core Cell Survey (Selection) Cell Name Function No. of core cells , Table 3 a Primitive Core Cell Survey (Selection) (cont'd) Cell Name Function No. of core cells , Features Table 3 b Soft-Macro Cell Survey (Selection) Cell Name Function No. of Equivalent Gates FA2 2 , Calculations Propagation Delays Propagation delays of the SCxD4 series are a function of several factors -
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74ls150 ph 4531 diode 4583 dual schmitt trigger ic D flip flop 7474 74245 BUFFER IC ic 7483 BCD adder
Abstract: em ark o f E xem plar L o g ic, Inc. H P is a re g iste re d tra d e m a rk o f H e w lett P ack ard , retrieval sy stem , or tra n sm itte d in any form or by any m eans, ele ctro n ic, m e c h an ic a l, p h , CP20K Series also features the industry's m ost flexible I/O and the highest num ber of I/Os. Each , m ing. Typical TPT and RLT Usage for Macrocell Implementation Number of TPTs' Number of , using TPTs a n d RLTs 1 MX41 Figure 2 6 Macrocell Function ND2 ND3 W hen RLTs -
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Abstract: ) lsi i a k;ic Architecture (Continued) Each of the 64 taps accepts two's complement or unsigned 8 , filter sections (FIR1 to FIR7), the corresponding alternate function, if any, is disabled. When part of , latch, then transferring it to the slave latch. There are three methods of loading and transferring , .0-REGADR.5. On the next rising edge of CLK the coefficient is transferred to the slave latch, thus loading the , Coefficient FIR4-FIR7 TC When 32COEFF is set HIGH, any coefficient loaded into the master latch of FIFty.x is -
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L64240 images of pin configuration of IC 74138 DI-74 18 x 16 barrel shifter L64240-15IWCCOM
Abstract: sections (FIR1 to FIR7), the corresponding alternate function, if any, is dis­ abled. When part of the , multiplier of each filter cell consists of first loading the coefficient to the master latch, then transfer­ ring it to the slave latch. There are three meth­ ods of loading and transferring coefficients , latch of the fil­ ter cell whose location has been determined by REGADR.0-REGADR.5. On the next rising edge of CLK the coefficient is transferred to the slave latch, thus loading the active coeffi -
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