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M38510/34201B2A Texas Instruments 4-Bit Binary Full Adders With Fast Carry 20-LCCC -55 to 125 visit Texas Instruments
M38510/31202BFA Texas Instruments 4-Bit Binary Full Adders With Fast Carry 16-CFP -55 to 125 visit Texas Instruments
CD74AC283M96 Texas Instruments 4-Bit Binary Full Adder with Fast Carry 16-SOIC -55 to 125 visit Texas Instruments
SNJ54LS283J Texas Instruments 4-Bit Binary Full Adders With Fast Carry 16-CDIP -55 to 125 visit Texas Instruments
CD54ACT283F3A Texas Instruments 4-Bit Binary Full Adder with Fast Carry 16-CDIP -55 to 125 visit Texas Instruments
5962-9758701Q2A Texas Instruments 4-Bit Binary Full Adders With Fast Carry 20-LCCC -55 to 125 visit Texas Instruments

full adder using ic 74138

Catalog Datasheet MFG & Type PDF Document Tags

full adder using ic 74138

Abstract: full adder using Multiplexer IC 74151 /checker 7483 - 4 bit full adder 74190 - up/down decade counter 7449 - BCD to 7 segment decoder 7474 - , evaluation. · TTL/CMOS I/O compatibility. · Design implemented using Altera's A+PLUS Development System · , as special processors, dedicated peripheral controllers and intelligent support chips. IC count can , is shown in the final figure of this data sheet. The functions included are; 7485 74279 74151 74138 , Most functions within the chip can be evaluated independently (an exception is the 74138 and 74157
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up down counter using IC 7476

Abstract: full adder using Multiplexer IC 74151 Comparator 42 ADDER FAMILY A1N A2N 1-blt Fun Adder 2-blt Full Adder a A4H - 4-blt Full , Industry-standard TTL devices. They are Identical In application to user macroa. Using F-Macros, a designer may , design flow to produce the array design. Designers may prepare their logic description using FLDL or use other description media which Fujitsu will convert to FLDL. Designers using Daisy, Valid or Mentor , may submit test descriptions utilizing other media and Fujitsu wlU convert to FTDL. Designers using
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IC 3-8 decoder 74138 pin diagram

Abstract: full adder using ic 74138 /8 50 9 ONE BIT FULL ADDER WITH FAST CARRY PATH PARALLEL CARRY GENERATOR 4 BIT ALU CARRY LOOK AHEAD GENERATOR (WITH G & P) CARRY LOOK AHEAD GENERATOR DUAL CARRY SAVE FULL ADDER 2 BY 4 PARALLEL BINARY MULTIPLIER 4 BIT FULL ADDER WITH FAST CARRY 4 BIT FULL ALU/FUNCTION GENERATOR 4 BIT ALU/FUNCTION GENERATOR 8 BIT SERIAL MULTIPLIER 2 BIT BINARY FULL ADDER 4 BIT BINARY FULL ADDER WITH FAST CARRY ONE BIT , FULL ADDER ONE BIT HALF ADDER I/O B U F FE R S A ND C O R N E R C ELLS (F A M IL Y 6) TRI-STATE OUTPUT
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full adder using Multiplexer IC 74151

Abstract: 74151 MUX 8-1 -lnput Exclusive NOR Full Adder D-Latch, gated D Flip-flop, Q and Q with Set D Flip-flop, Q Only RAM cell 16X9 , -Bit Full Adder 10 HA1 1-Bit Half Adder 5 D Flip-Flops FDP1B D Flip-Flop w/ Clear & Set, 7 POS , -Bit Fast Adder 277 CBM6C FA2 2-Bit Binary Full Adder (7482) 20 FA4 4-Bit Binary Full Adder 44 CBM7C FAS2 2-Bit Binary 2's Complement Full Adder, Subtractor 25 CBM8C CLS82 2-Bit Binary Full Adder (7482 , on the nature of the circuit) using the automatic placement and automatic routing capabilities of the
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full adder using Multiplexer IC 74151 74151 MUX 8-1 full subtractor using ic 74138 pin configuration IC 74151 Multiplexer IC 74151 modulo 16 johnson counter CP20K CP20420

IC 3-8 decoder 74138 pin diagram

Abstract: full adder using ic 74138 COMPARATOR MC4 4 -b it Magnitude Comparator 42 ADDER FAMILY A1N A2N 1-bit Full Adder 2- bit Full Adder 8 16 A4H - 4-b it Full Adder - 50 - SCHMITT TRIGGER DELAY UNIT CELLS , common logic Macros. FEATURES · · · · · · 1.4 ns g a te d e la y ty p ic a l. (2 -in p u t N A N D g a te ,F .O .= 2 ) S ta tic R A M or RO M on c h ip . S ilic o n -g a te 1.8 m ic ro n d ual m e ta l , s s -0 .5 -80 -40 -65 Ceramic T y p ic a l - M a x im u m 6.0 VDD + 0.5 VDD + 0.5 140 70 150
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IC 3-8 decoder 74138 pin diagram full adder using ic 74138 pin diagram for IC 7483 for 4 bit adder chip and pin diagram of IC 7491 circuit diagram for IC 7483 full adder DN 74352 MB65XXXX MB66XXXX MB67XXXX C4002
Abstract: FA1 Full Adder 7 2 LDNN D-Latch, gated 2 1 FDP1SB D Flip-flop, Q and Q , an IC â'™s boundary to control and m onitor access during testing (see Figure 9). Full scan , -CLK, Q Only 11 Multiplexers JK Flip-Flops Adders FA1 1-Bit Full Adder 10 HA1 1 , 12 21 277 FA16 16-Bit Fast Adder FA2 2-Bit Binary Full Adder (7482) 20 FA4 4-Bit Binary Full Adder 44 FAS2 2-Bit Binary 2's Com plem ent Full Adder, Subtractor 25 2 -
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IC 3-8 decoder 74138 pin diagram

Abstract: binary to gray code conversion using ic 74157 74259 35 9-BIT ODD/EVEN PARITY GENERATOR/CHECKER 74280 36 4-BIT BINARY FULL ADDER WITH , (Note) lo -10 ~ +10 mA Storage temperature T«, -65 - +150 °C Note: Values apply when using , ) 190K ~ 20 M (3) 30K - 33 M Note: 1) CR oscillation circuit (using BSCC block) 2) Ceramic oscillation circuit (using BLÇC, BHCC blocks) 3) Crystal oscillation circuit (using BLCC, BHCC blocks) â , Vout = Vss -10 â'" â'" *1 . Using 4mA type buffer *4 . Using 20mA type buffer *2 . Using 8mA
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binary to gray code conversion using ic 74157 16 bit odd even parity checker using two IC 74180 binary to gray code conversion using ic 74139 7444 series Excess-3-gray code to Decimal decoder ic 74151 ic 74148 block diagram MSM91H000 72MS40 DQQ023 MSM70H000 MSM70H00

74LS82

Abstract: 74245 BIDIRECTIONAL BUFFER IC bit binary full adder (74LS82) 4 bit binary full adder 4 bit equality comparator 8 bit equality , layers of metal interconnect. A full master spectrum is offered with complexities ranging from 2,300 to , iring" is added using 2 layers of aluminium interconnect. The gate array masters themselves consist of , lls fo r g iv e n m e m o ry c o n fig u ra tio n s . High Density on-chip ROM Using a similar , standard drive strength version and enhanced drive strength indicated by a suffixed letter " P" . A full
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74245 BIDIRECTIONAL BUFFER IC ic 4583 schmitt trigger core bit excess 3 adder using IC 7483 la 4508 ic schematic diagram advantages for ic 7473 4 BIT COUNTER 74669 TC140G SC12D4 SC18D4 SC27D4 SC37D4 SC44D4

74ls82

Abstract: 74245 BIDIRECTIONAL BUFFER IC bit binary full adder (74LS82) 20 FA4 4 bit binary full adder 45 CMP4 4 bit equality comparator 14 , layers of metal Interconnect. A full master spectrum is offered with complexities ranging from 2,300 to , using 2 layers of aluminium interconnect. The gate array masters themselves consist of an inner core of , showing number of core cells for given memory configurations. High Density on-chip ROM Using a similar , "P". A full description of the cell naming convention can be found in the Lib D4 cell catalogue. A
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74ls150 ph 4531 diode 4583 dual schmitt trigger ic D flip flop 7474 74245 BUFFER IC ic 7483 BCD adder

full 18*16 barrel shifter design

Abstract: IC 3-8 decoder 74138 pin diagram expanded circuit would require another three TTL IC packages, brining the total to eleven if done using , . Two Flip-Flops Implemented in the NAND Foldback Strucutre One straightforward example of using a , distinct address selections can be made using only the dedicated outputs. The designer can combine , data (bit reversal) or byte swapping to name a few. Part of an eight bit, look-ahead parallel adder , Q D CLK CLK Figure 5.CLK Partial NAND Gate CLK Equivalence of the 8-Bit Look-Ahead Adder
Philips Semiconductors
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full 18*16 barrel shifter design TTL SN 7404 pn sequence generator using d flip flop 12 bit comparator images of pin configuration of IC 74138 8 bit barrel shifter PLHS501 AN049

function of latch ic 74373

Abstract: full adder using ic 74138 ECKERS C ARRY SAVE FULL ADDER P R ESE T T A B LE D EC A D E COUNTER/ LATCH P R E S E T T A B L E 4 -B IT , using the high performance silicon gate H C M O S process with the dual-layer metal structure. This , oscillator, pull-up/pull-down input circuit, and clock driver through the input/output cells, w ithout using , input, output, bi-direction, V q q , and V g s or|ly with rnetal connection. The L S I development using , evaluation. Since the system fully supports the design using the engineering w ork station ( D A IS Y , M E N
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MSM70000 function of latch ic 74373 pins and their function in ic 74163 encoder IC 74147 74541 buffer 74373 cmos dual s-r latch sn 74373 MSM71000/72000/73000/74000 MSIW71000 MSM74000

AMD K6

Abstract: 74147 decimal to binary encoder controls one data selection in the LCA device. The memory cell outputs Q and Q use full Ground and Vcc , type output can be obtained by using the same signal for driving the output and three-state signal , ) Optional pull-up resistor Direct/registered Inverted/true Full speed/slew limited Optional , through the switch matrix can be made by automatic routing, or by using Editnet to se­ lect the desired , inputs of logic blocks. Using this global buffer for a clock signal provides a skew free, high fan-out
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AMD K6 74147 decimal to binary encoder C10BCPRD C10BCRD C10BPRD C10JCR C12JCR C16BARD

DM024

Abstract: oti 2168 -NOR eoi 3-Input Exclusive OR eo3 eonl 2-OR, 2-NAND into 2-NAND fai a Full Adder hai Half Adder , -Input AND Internal Power and Ground Ring Structure Using 5 V Power Supply for 5 V Outputs Internal Power and Ground Ring Structure Using 3.3 V Power Supply for 3.3 V Outputs LCA300K 2-Layer Metal Products , products are designed using the LCA300K/LCA310K Gate Array series product family libraries. This databook , The timing data given on the macrocellâ'™s data page are calcu­ lated using LSI Logicâ'™s modeling
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DM024 oti 2168 transistor bf 175 CM17B D-102 5304A0M LCA310K CW33000 CW803 CW807

dm024

Abstract: A992 transistor and its equivalent -OR, 2-NAND into 2-NAND fala Full Adder hal Half Adder mux21h Non-Inverting Gate MUX mux211 , Operation Data Page for an2, a 2-Input AND 3.1 Internal Power and Ground Ring Structure Using 5 V Power Supply for 5 V Outputs 3-3 Internal Power and Ground Ring Structure Using 3.3 V Power , are designed using the LEA 300K E m bed­ ded Array ASICs product fam ily libraries. This databook , 2). T he tim ing data given on the m acrocellâ'™s data page are calcu­ lated using LSI L ogicâ'™s
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A992 transistor and its equivalent LB 11917 LEA300K DB04-000048-00 FALU32 FMPY32 FALU32P FMPY32P

0221l

Abstract: APPLICATION NOTES CD 7474 IC R IS T IC S S W IT C H IN G D E LA Y T IM E A R IT H M E T IC O PERATORS 1 - B I T FULL ADD ER (H A , comprises 14 gate arrays, each fabricated using Tl's 1-|.im advanced silicon-gate CMOS EPIC process. The , user-defined software macros can be created using the TGC100 Library macros. Library Release 4.0 contains the , Gate Arrays design flow User-defined semicustom integrated circuits, designed using Tl's TGC100 , functionality using customer-supplied test patterns at f 1 MHz, V qc = 5 V, and T * = 25°C. prototype and
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0221l APPLICATION NOTES CD 7474 IC TGC119 bit-slice IPF 830 cI 74150

headland 386

Abstract: b2211 -Input Exclusive OR 2-OR, 2-NAND into 2-NAND Full Adder Fast Full Adder Half Adder Non-Inverting Gate MUX 3 , -Input AND Internal Power and Ground Ring Structure Using 5 V Power Supply for 5 V Output Buffers Internal Power and Ground Ring Structure Using 3.3 V Power Supply for 3.3 V Output Buffers 1.2 1.3 1.4 1.5 , using the LC B 300K /LCB 310K Cell-B ased A SICs product fam ily libraries. This databook also contains , data given on the m acrocellâ'™s data page are calcu­ lated using LSI L ogicâ'™s m odeling enhancem
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headland 386 b2211 transistor zo 607 MA 7S LCB300K DB04-000049-00

7N121

Abstract: MC88000 synchronous to the input clock (CLK), multiple processors can be - - ­ resynchronized using the WAIT , ), multiple processors can be resynchronized using the - - ­ WAIT instruction and asserting I R Q B to , asserted synchronous to the input clock (CLK), multiple processors can be resynchronized using the - - , Arbitration Protocol The bus is arbitrated by a central bus arbitrator, using individual request/grant lines , designed to accommodate various IC family members with different memory and on-chip peripheral requirements
Motorola
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DSP96002 7N121 MC88000 7483 logic circuit adder and subtracter MVS2 semiconductors replacement guide 32 bit booth multiplier for fixed point 32-BIT

mvb bus schematics

Abstract: mc88000 ­ resynchronized using the WAIT instruction and asserting I R Q A to exit the wait - - ­ , synchronous to the input clock (CLK), multiple processors can be resynchronized using the - - ­ WAIT , the input clock (CLK), multiple processors can be resynchronized using the - - ­ WAIT , bus is arbitrated by a central bus arbitrator, using individual request/grant lines to each bus master , architecture is designed to accommodate various IC family members with different memory and on-chip peripheral
Motorola
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mvb bus schematics DSP56001 users manual real time application and product for fir IC 7492 D15114 JVC KS F 185

asynchronous fifo vhdl

Abstract: 8 BIT ALU design with verilog/vhdl code .15 3.2.1.3 Using SpDE , .18 3.2.2.3 Using the Waveform Editor, Active HDL Simulator, and the Data 3.2.2.4 Using Precision RTL Synthesis .18 3.2.2.5 Using SpDE, Active HDL Simulator, and the Data Analyzer , .20 3.2.4.3 Using Precision RTL - SpDE
QuickLogic
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asynchronous fifo vhdl 8 BIT ALU design with verilog/vhdl code 74139 for bcd to excess 3 code vhdl code for 8bit bcd to seven segment display 32 BIT ALU design with verilog/vhdl code 74594

A5 GNC mosfet

Abstract: SL1626 . and directives for using its assembler program. (244 pages; $15. or $25 with the AMI 6800 Hardware , (105 pages) documentation ot how to interface .Mih the National (155 timesharing svstem when using the , '™ll find it out in seconds by using the MASTER. . The 1C MASTER saves you time and lots of it. no , largest electronic publisher in the world. Contents Quick Guide to IC Master . 2 Part Number Index , has been expended to make IC MASTER accurate and complete, but IC MASTER cannot assume responsibility
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A5 GNC mosfet SL1626 HA1452 TCA345 INTERSIL application bulletin teledyne 39843 AMI6800H AMI6800 VMI6800
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