NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: OVERVIEW The CP1306 CP1306 is a single channel PCM / ADPCM codec fabricated in advanced low-power mixed-mode CMOS process. The CP1306 CP1306 encodes the analog voice band signal to 64 Kbps PCM (G.711) or 32 Kbps ADPCM (G.721) serial data, and decodes 64 Kbps PCM (G.711) or 32 Kbps ADPCM (G.721) serial data to , 1 channel PCM / ADPCM codec with Digital Signal Processing(DSP) technique â- Voice companding algorithm: • ITU-T G.711 PCM (M-law) @ 64 Kbps • ITU-T G.721 ADPCM @ 32 Kbps â- Transmit/Receive ... | OCR Scan |
2 pages, |
g721 CP1306 analog voice G.711 CP1306 abstract |
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| Abstract: The ProSLIC evaluation board can easily be connected to many PCM bus sources. One industry standard for PCM testing is the Wandel and Goltermann model PCM-4. The PCM-4 tests telephone linecard voice parametrics in the two-wire and PCM domains. This document describes the connections from a typical PCM-4 to the ProSLIC evaluation board. The PCM-4 should be an option "E" which generates a 2.048 MHz PCM , Figure 1. Connect the PCM-4 Ext. Frame (63) BNC"T" to the ProSLIC evaluation board FSYNC. See Figure 1. ... | Original |
6 pages, |
Si322x Si321X Si3210 ProSLIC PCM-4 AN39 fsync in PCM PCM-4 wandel datasheet abstract |
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| Abstract: AN187 AN187 C O N N E C T I N G T H E S I 3050/19 T O T H E W&G PCM-4 Overview The Si3050 evaluation board can easily be connected to many PCM bus sources. One industry standard for PCM testing is the Wandel and Goltermann model PCM-4. The PCM-4 tests telephone linecard voice parametrics in the two-wire , PCM-4 Ext. Frame (63) BNC"T" to the Si3050 evaluation board FSYNC. See Figure 1. Connect the PCM-4 RX , current source (loop current) to operate in the offhook state. The PCM-4 does not provide this loop ... | Original |
4 pages, |
AN187 Si3050 fsync in PCM PCM-4 PCM-4 wandel AN187 abstract |
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| Abstract: SDO SDI PCLK FSYNC PCLK FSYNC RX DTX TX DRX GPO RST GND Figure 1. Si3050 in PCM/SPI Mode Block Diagram Rev. 0.1 12/02 Copyright © 2002 Silicon Laboratories AN77-DS01 AN77-DS01 AN77 Power Up RST Low Pulse Write Register 33 // Enable PCM mode 20h = ALaw 28h = , the steps necessary to program the Si3050 DAA for basic operation using either the PCM/ SPI or GCI , 3.3 V Si3050 VD FSYNC FSYNC PCLK VA PCLK RX DTX TX DRX GPO RST ... | Original |
6 pages, |
Off-Hook AN77 fsync in PCM Si3050 datasheet abstract |
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| Abstract: ® DEM-PCM1800 DEM-PCM1800 INSTRUCTION MANUAL DESCRIPTION In Master Mode, LRCK, BCK, FSYNC, and DATA, are outputs. In Slave Mode, DEM-PCM1800 DEM-PCM1800 requires LRCK, BCK, FSYNC inputs, and outputs DATA. DEM-PCM1800 DEM-PCM1800 is , DIAGRAM Power Supply Digital Inerface Lch IN PCM1800 PCM1800 A/D Rch IN Mode Control Switch , DEM-PCM1800 DEM-PCM1800 Printed in U.S.A. November, 1997 DEM-PCM1800 DEM-PCM1800 BASIC CONNECTIONS AND OPERATION · Audio , analog inputs are VINL, VINR connector CN2. · LRCK, BCK, DATA, are outputs for PCM Audio data. · ... | Original |
3 pages, |
PCM1800 DEM-PCM1800 fsync in PCM DEM-PCM1800 abstract |
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| Abstract: All of the PCM CodecÂFilter Products Described in this Document are: · Manufactured in a 0.8 Micron , clock (BCLK), and 256 kHz are derived for use by the PCM CodecÂFilter. FSYNC Frame sync (FSYNC) is , AVAILABLE J15: NOT AVAILABLE J16: FST = FSYNC J16 connects the onÂboard generated FSYNC to the PCM , compatibility. J20A: FSR = FSYNC J20A connects FSR (Pin 7) of the PCM CodecÂFilter to FSYNC. J20B: FSR = VDD J20B connects FSR (Pin 7) of the PCM CodecÂFilter to VDD to select channel B2 in the IDL or GCI ... | Original |
16 pages, |
MC145532 MC14LC5480EVK 6 Pin RJ11 Board Jack RJ11 diagram fsync in PCM header 2X20 pin hearing aids coil J10B J20A MC14LC5480 Motorola linear power supply MC145484 hearing aid microphone MC14LC5480EVK/D MC14LC5480EVK MC14LC5480EVK/D abstract |
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| Abstract: All of the PCM CodecÂFilter Products Described in this Document are: · Manufactured in a 0.8 Micron , clock (BCLK), and 256 kHz are derived for use by the PCM CodecÂFilter. FSYNC Frame sync (FSYNC) is , : NOT AVAILABLE J16: FST = FSYNC J16 connects the onÂboard generated FSYNC to the PCM CodecÂFilter , compatibility. J20A: FSR = FSYNC J20A connects FSR (Pin 7) of the PCM CodecÂFilter to FSYNC. J20B: FSR = VDD J20B connects FSR (Pin 7) of the PCM CodecÂFilter to VDD to select channel B2 in the IDL or GCI ... | Original |
16 pages, |
MC14LC5480EVK J20A MC145481 MC145482 MC145483 MC145484 MC145532 circuit diagram of digital hearing aid MC14LC5480 J10B fsync in PCM J11A MC14LC5480EVK/D MC14LC5480EVK/D abstract |
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| Abstract: the clocking circuitry, and one of the PCM Codec Filters listed in Table 1Â1. User I/O to the board , sync (FSYNC), bit clock (BCLK), and 256 kHz are derived for use by the PCM CodecÂFilter. FSYNC , generated FSYNC to the PCM CodecÂFilter (Pin 14) FST as well as Pin 1 of the 2x20 connector (P13). J17A , compatibility. Freescale Semiconductor, Inc. J20A: FSR = FSYNC J20A connects FSR (Pin 7) of the PCM CodecÂFilter to FSYNC. J20B: FSR = VDD J20B connects FSR (Pin 7) of the PCM CodecÂFilter to VDD to select ... | Original |
16 pages, |
circuit diagram of digital hearing aid ic for hearing aid J11A J20A MC145481 MC145482 MC145483 MC145484 MC145532 MC14LC5480 MC14LC5480EVK pin RJ11 J10B MC14LC5480EVK/D MC14LC5480EVK/D abstract |
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| Abstract: 01W127A 01W127A PCM CODEC for Digital cellular phones BU8776KN BU8776KN Dimension (Units : mm) 7.2 ± 0.1 , power supply (VDD=2.7~3.3V) 2) 14bit high-precision linear u/A-LAW CODEC 3) Transmission filter in , for PDC, N-CDMA 6) Serial I/F for register setting adapted for 3-wire serial type 7) Selectable PCM , 7.2 ± 0.1 7.0 ± 0.1 37 5 0. Description BU8776KN BU8776KN is PCM CODEC deveolped for digital , TEXTDI 33 TEXTDO 34 C1 R8 PLLLPF 35 FSYNC 36 STB SCL SDA 8KHz ... | Original |
2 pages, |
VQFP48 QFN48U GSM DTMF BU8776KN BU8733KV BU8732AKV BU8731KV BU8730KV 01W127A 01W127A abstract |
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| Abstract: edge of FSYNC. The first is shown in Figure 2. where the beginning of the channel block aligns with the rising edge of the FSYNC. In the second option, the channel block is delayed one period of the , operating as a slave to a systems clock, such as a DSP generated serial clock and FSYNC. When operating in , or operating as a systems clock Master. When operated in this mode the duty cycle of the FSYNC is 50% , the FSYNC as shown in Figure 4 and Figure 5. Notice that the last bit of the Channel N block is ... | Original |
4 pages, |
AN301 AN282 fsync in PCM CS8421 AN301 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| available in the following formats: Portable Document Format and Raw Text Format ST5451 ST5451 ST5451 ST5451 ISDN FRAMES IN TRANSMISSION (64bytes FIFO Tx) AND EIGHT FRAMES IN RECEPTION (64bytes FIFO Rx) COMPATIBLE WITH CMOS cir- cuit fully developed by ST and dif- fused in advanced 1.2 m m HCMOS3 technology. The device is intended to be used mainly in ISDN applications, in Terminal (TE) and in Line Termi- nations (LT a wide range of PCM signals go- ing from GCI (General Circuit Interface) to DSI (Digital System www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1437-v2.htm |
STMicroelectronics | 14/06/1999 | 46.54 Kb | HTM | 1437-v2.htm |
| available in the following formats: Portable Document Format and Raw Text Format ST5451 ST5451 ST5451 ST5451 ISDN FRAMES IN TRANSMISSION (64bytes FIFO Tx) AND EIGHT FRAMES IN RECEPTION (64bytes FIFO Rx) COMPATIBLE WITH CMOS cir- cuit fully developed by ST and dif- fused in advanced 1.2 m m HCMOS3 technology. The device is intended to be used mainly in ISDN applications, in Terminal (TE) and in Line Termi- nations (LT a wide range of PCM signals go- ing from GCI (General Circuit Interface) to DSI (Digital System www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1437.htm |
STMicroelectronics | 02/04/1999 | 46.58 Kb | HTM | 1437.htm |
| ACCESS WITH MULTIPLEXED BUS m P CAN HANDLE AND STORE AT THE SAME TIME TWO FRAMES IN TRANSMISSION (64bytes FIFO Tx) AND EIGHT FRAMES IN RECEPTION (64bytes FIFO Rx) COMPATIBLE WITH ALL THE STMicroelec developed by STMicroelectronics and diffused in advanced 1.2 m m HCMOS3 technol - ogy. The device is intended to be used mainly in ISDN applications, in Terminal (TE) and in Line Termi - nations (LT). ST5451 ST5451 ST5451 ST5451 range of PCM signals go - ing from GCI (General Circuit Interface) to DSI (Digital System www.datasheetarchive.com/files/stmicroelectronics/books/ascii/docs/1437.htm |
STMicroelectronics | 25/05/2000 | 50.03 Kb | HTM | 1437.htm |
| . DMA ACCESS WITH MULTIPLEXED BUS m P CAN HANDLE AND STORE AT THE SAME TIME TWO FRAMES IN TRANSMISSION (64bytes FIFO Tx) AND EIGHT FRAMES IN RECEPTION (64bytes FIFO Rx) COMPATIBLE WITH ALL THE cir - cuit fully developed by STMicroelectronics and diffused in advanced 1.2 m m HCMOS3 technol - ogy. The device is intended to be used mainly in ISDN applications, in Terminal (TE) and in Line Termi - nations (LT). ST5451 ST5451 ST5451 ST5451 can handle HDLC packets either on 16Kbit/s D channel or 64 www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1437-v1.htm |
STMicroelectronics | 25/05/2000 | 48.22 Kb | HTM | 1437-v1.htm |
| -type #pins | PCM4201PW 1.65V-3.6V TSSOP 16 | PCM4201PWG4 1.65V-3.6V TSSOP 16 | PCM4201PWR 1.65V-3.6V TSSOP 16 | PCM4201PWRG4 | |* | [IBIS Ver] 3.2 [File name] pcm4201.ibs |SIMDE Ver V3.0 - 201101 - RHL4 - Build 457 simulations in TISPICE | - Model matched to SPICE simulation | - C_comp although listed in numerical order of : * |* - For model RATE_SM there will be a leakage current in the * |* clamp I-V table because of the www.datasheetarchive.com/download/10864294-915941ZC/sbam149.zip (pcm4201.ibs) |
Texas Instruments | 06/05/2012 | 98.84 Kb | ZIP | sbam149.zip |
| is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied as in video=geodefb:off +identifier=value as in video=geodefb:vfreq=85 +noidenfier as in += = +vfreq - Set initial video refresh rate in cycles per second +vmode - Set initial mode to - Maximum amount of memory to use for the FB (in Kbytes) +accel - HW accleration support (0=disabled + +The permissible mode parameter combinations are defined by the cimarron +driver, and in cimarron by www.datasheetarchive.com/download/55429351-72918ZC/bsp_linux_2.6.11_board_support_package.zip (Patches_Linux2.6.11_Common_02.03.0100.patch) |
Digital Logic | 18/06/2007 | 954.19 Kb | ZIP | bsp_linux_2.6.11_board_support_package.zip |