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Part Manufacturer Description Datasheet BUY
SERDESUR-65USB Texas Instruments FPD Link II - DS90UR905Q & DS90UR906Q EVK visit Texas Instruments
DS99R124QSQX/NOPB Texas Instruments 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter 48-WQFN -40 to 105 visit Texas Instruments
DS90UR907QSQX/NOPB Texas Instruments 5 - 65 MHz 24-bit Color FPD-Link to FPD-Link II Converter 36-WQFN -40 to 105 visit Texas Instruments
DS99R124AQSQX/NOPB Texas Instruments 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter 48-WQFN -40 to 105 visit Texas Instruments
DS99R124AQSQE/NOPB Texas Instruments 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter 48-WQFN -40 to 105 visit Texas Instruments
DS90UR908Q-EVK Texas Instruments DS90UR908Q-EVK FPD-Link II to FPD-Link Converter Evaluation Kit visit Texas Instruments

fpd 007

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: signal, can be changed in Event control register 0x1d Pin can be used for FPD output, PWM output or Dome , 0.236 ± 0.003 4.10 ± 0.07 0.161 ± 0.003 2.05 0.081 0.95 0.037 3 0.70 ± 0.05 2Xø 0.028 ± 0.002 1.15 , 0.236 ± 0.003 2.16 3.14 ± 0.07 0.085 0.123 ± 0.003 0.20 2X 0.008 Pin # 1 2.60 0.102 2X R , , unless otherwise noted. 3. Formula for dimension, T = (0.9/n)-0.07 where n = Refractive Index 4. Mirror , VDD IDD_LED+ Total I VDD IDD_LED+ Total Typical 1.56 1.34 2.90 0.2 0.15 0.35 0.04 0.03 0.07 0.02 Avago Technologies
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L-1225R lexan 121 21051 CRC07 lexan 21051 HF05084R ADBS-A350 ADBL-A321 AV02-2806EN
Abstract: height restricted electronic equipment and applications Suitable for FPD device, HDD, CD-RW, LCD , Unit : pF Ex.: 475:47×105 106:10×106 - 39- K K 007 007 T T Tolerance Rated Voltage Packaging Ex.: K: +/- 10% M:+/- 20% Z :+80/-20% Ex.: 007: 6.3Vdc 010: 10Vdc 016 -
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Capacitor MLCC 1210 10uF 25V capacitor 22uf 16v 1206 x5r MLCC 16V 10uF 10uf 0805 Capacitor dimension 70 M 20 B lcd tic 226 500/C
Abstract: Multilayer Ceramic Chip Capacitors (MLCC) Holy Stone VAC Series [ Low Profile X5R,Y5V Capacitors ] Supporting low profile application sets with varieties of low profile MLCCs Features. Application For thin profile circuit. Suitable FPD device, HDD, CD-RW, LCD device, cellular phone modules and portable device.etc. High capacitance & rated voltage with maximum height of 0.95 mm , :10×106 K K Tolerance Ex.: K: +/- 10% M:+/- 20% Z :+80/-20% 007 007 Rated Voltage Ex.: 007 Holy Stone Enterprise
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HOLYSTONE SPECIFICATION MLCC 22uF 16V X5R 10 1206 15uF MLCC 475 10v mlcc 0805 x5r 22uF 10V mlcc soldering
Abstract: VAC Series [ Low Profile X5R,Y5V Capacitors ] Supporting low profile application sets with varieties of low profile MLCCs Features. Application For thin profile circuit. Suitable FPD device, HDD, CD-RW, LCD device, cellular phone modules and portable device.etc. High capacitance & rated voltage with maximum height of 0.95 mm Surface Mount Suited for Wave and Reflow Soldering , /-20% 007 007 Rated Voltage Ex.: 007: 6.3Vdc 025: 25Vdc T T Packaging T: Taping & & Reel -
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475 16V X5R 0805
Abstract: signal, can be changed in Event control register 0x1d Pin can be used for FPD output, PWM output or Dome , 0.236 ± 0.003 4.10 ± 0.07 0.161 ± 0.003 2.05 0.081 0.95 0.037 3 0.70 ± 0.05 2Xø 0.028 ± 0.002 1.15 , 0.236 ± 0.003 2.16 3.14 ± 0.07 0.085 0.123 ± 0.003 0.20 2X 0.008 Pin # 1 2.60 0.102 2X R , , unless otherwise noted. 3. Formula for dimension, T = (0.9/n)-0.07 where n = Refractive Index 4. Mirror , VDD IDD_LED+ Total I VDD IDD_LED+ Total Typical 1.56 1.34 2.90 0.2 0.15 0.35 0.04 0.03 0.07 0.02 Avago Technologies
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makrolon 2405 2405 lexan st-4 hub fpdt switch marking code RES3 L1225
Abstract: (Schmitt trigger input)/ O (CMOS output) Pin can be used for FPD output, PWM output or Dome/ Button , outline drawing Pin # 1 1 6.00 ± 0.08 0.236 ± 0.003 4.10 ± 0.07 0.161 ± 0.003 2.05 0.081 , 0.45 0.018 1.15 0.045 2 6.00 ± 0.08 0.236 ± 0.003 Pin # 1 2.16 3.14 ± 0.07 0.085 , otherwise noted. 3. Formula for dimension, T = (0.9/n)-0.07 where n = Refractive Index 4. Mirror finish , 0.35 0.50 mA   DC average supply current in Rest2 mode I VDD 0.04 0.07 mA Avago Technologies
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Abstract: . LVDS LVDS-090 2.1a. LVDS-007 2.2. PECL LVDS LVDS ECL PECL PECL VEE 1V DC , DS90C031/ DS90C032 3V DS90LV047A/DS90LV048A / LVDS LCD FPD ( ) LDI (LVDS ) LCD , ( FPD ) LVDS 2 LVDS 0.1uF 1 EMI EMI 100mV 1. ( ) 50 2. PCB 3. 2 , ) LVDS-045 6.2. FPD 1. 2. 6.2.3 2S + - S W + - LVDS , SCANSTAEVK LVDS : www.national.com/jpn/appinfo/FPD LVDS.national.com/jpn 8-1 A.1 LVDS National Semiconductor
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tektronix 463 LVDS-008 ROGERS4350 GETEK FR4 10G BERT AN-81 national
Abstract: . LVDS LVDS-090 2.1a. LVDS-007 2.2. PECL LVDS LVDS ECL PECL PECL VEE 1V DC , DS90C031/ DS90C032 3V DS90LV047A/DS90LV048A / LVDS LCD FPD ( ) LDI (LVDS ) LCD -
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LVDS-007 DS90LV047A DS90LV048 LVDS-006 IC 232 rs422 cat5 RS-422PECLLVDS RS-422 DS90LV047A/048A LVDS-005
Abstract: Pin can be used for FPD output, PWM output or Dome/ Button click input. If configure as input do not , current IVDD IVDD IVDD IVDD IDDSHTDWN VDD Typical 2.90 0.35 0.07 0.03 1.54 Max 4.03 0.50 0.12 0.05 , micro-controller when one of these events occurs: FPD ­ A change in finger state (finger on to finger off and vice , after the user responds to it by reading the respective event status register: FPD ­ reading FPD_STATUS , that can be used as FPD output ­ to display FPD status Pulse Width Modulated (PWM) output ­ to Avago Technologies
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ADBM-A350 BUTST 482-MS ADBM350 ADBM-A350-200 AV02-2905EN
Abstract: ) Pin can be used for FPD output, PWM output or Dome/ Button click input. If configure as input do not , average supply current in Rest2 mode IVDD 0.07 0.12 mA GPIO=SHTDWN=pull low , to trigger the host micro-controller when one of these events occurs: ï'·ï'  FPD â'" A change in , responds to it by reading the respective event status register: ï'·ï'  FPD â'" reading FPD_STATUS , 19.5 ms 250 ms Rest 2 96 ms 9.5 s Rest 3 482 ms 582 s ï'·ï'  FPD output â'" to Avago Technologies
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Abstract: ) Pin can be used for FPD output, PWM output or Dome/ Button click input. If configure as input do not , average supply current in Rest2 mode IVDD 0.07 0.12 mA GPIO=SHTDWN=pull low , to trigger the host micro-controller when one of these events occurs: ï'·ï'  FPD â'" A change in , responds to it by reading the respective event status register: ï'·ï'  FPD â'" reading FPD_STATUS , 19.5 ms 250 ms Rest 2 96 ms 9.5 s Rest 3 482 ms 582 s ï'·ï'  FPD output â'" to Avago Technologies
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Abstract: Temperature range Climatic category IEC 68-2-3, 55/85/56 DIN 40040, 2.73, FPD Max. 0.3% after a 2 year , % 0.07% C > 4700 pF 0.04% 0.07% Dissipation factor tan8 Measured at +20°C, according to E C 384-13 -
OCR Scan
EVOX PFR EVOX pfr5 EVOX PFR CAPACITORS 472J100 103j63l4 222J63 63VDC/40VAC 100VDC 250VDC/160VAC 400VDQ220VAC 630VDC/2S0VAC 472J100L4
Abstract: Pin can be used for FPD output, PWM output or Dome/ Button click input. If configure as input do not , IVDD IVDD IDDSHTDWN VDD Typical 2.90 0.35 0.07 0.03 1.54 Max 4.03 0.50 0.12 0.06 26.7 Units , : FPD ­ A change in finger state (finger on to finger off and vice versa) is detected Soft Click ­ Soft , reading the respective event status register: FPD ­ reading FPD_STATUS register (0x7a) Soft Click ­ , . Mode Rest 1 Rest 2 Rest 3 The GPIO pin is a level-sensitive input/ output that can be used as FPD Avago Technologies
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CRC23 R10-220R
Abstract: ) Pin can be used for FPD output, PWM output or Dome/ Button click input. If configure as input do not , IVDD 0.07 0.12 mA GPIO=SHTDWN=pull low, IO_MISO=NRST=pull high. DC average supply , '  FPD â'" A change in finger state (finger on to finger off and vice versa) is detected ï'·ï'  Soft , reset after the user responds to it by reading the respective event status register: ï'·ï'  FPD â , ï'·ï'  FPD output â'" to display FPD status ï'·ï'  Pulse Width Modulated (PWM) output â'" to control Avago Technologies
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Abstract: ; except as specified.) Symbol IILOSC fOSCin vOSCin fPD Parameter Oscillator Input Low Current Frequency , , LNPLL_flat, and is defined as: LNPLL_flat = L(f) ­ 20·log(N) ­ 10·log(fPD). LPLL_flat is the single side band phase noise in a 1 Hz Bandwidth and fPD is the phase detector frequency of the synthesizer. LPLL_flat , 0.09 0.07 0.07 0.06 0.06 0.05 0.05 0.04 0.04 Imaginary -2.70 -3.04 -2.67 -1.63 -1.22 -0.92 -0.74 -0.63 , 0.07 0.07 0.07 0.06 0.06 0.05 0.05 Powered Down (k) Imaginary -8.14 -6.72 -5.24 -2.94 -2.12 -1.58 Texas Instruments
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LMX2531 SNAS252Q LMX2531LQ1146E LMX2531LQ1226E LMX2531LQ1312E LMX2531LQ1415E
Abstract: Max Units ICC Power Supply Current Power Supply Current ICCPD IIHOSC IILOSC fOSCin vOSCin fPD , noise floor, LNPLL_flat, and is defined as: LNPLL_flat = L(f) ­ 20·log(N) ­ 10·log(fPD). LPLL_flat is the single side band phase noise in a 1 Hz Bandwidth and fPD is the phase detector frequency of the , 130 140 150 Powered Up (k) Real 4.98 3.44 1.42 0.52 0.29 0.18 0.13 0.10 0.09 0.07 0.07 0.06 0.06 , 0.34 0.32 0.30 0.28 Real 6.77 5.73 1.72 0.53 0.26 0.17 0.14 0.10 0.09 0.08 0.07 0.07 0.07 0.06 0.06 National Semiconductor
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311742A application note LMX2531 LMX2531LQ1650 SNAS252P
Abstract: fOSCin vOSCin fPD Power Down Current Oscillator Input High Current Oscillator Input Low Current Frequency , : LNPLL_flat = L(f) ­ 20·log(N) ­ 10·log(fPD). LPLL_flat is the single side band phase noise in a 1 Hz Bandwidth and fPD is the phase detector frequency of the synthesizer. LPLL_flat contributes to the total , 0.09 0.07 0.07 0.06 0.06 0.05 0.05 0.04 0.04 Imaginary -2.70 -3.04 -2.67 -1.63 -1.22 -0.92 -0.74 -0.63 , 0.07 0.07 0.07 0.06 0.06 0.05 0.05 Powered Down (k) Imaginary -8.14 -6.72 -5.24 -2.94 -2.12 -1.58 Texas Instruments
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LMX2531SQ NF 027 NJG0036A LMX2531LQ1500E LMX2531LQ1515E LMX2531LQ1570E LMX2531LQ1650E LMX2531LQ1700E
Abstract: LMX2531LQ2265E/ 2570E LMX2531LQ2820E/ 3010E All Other Options ICCPD IIHOSC IILOSC fOSCin vOSCin fPD Power Down , Normalized PLL noise floor, LNPLL_flat, and is defined as: LNPLL_flat = L(f) ­ 20·log(N) ­ 10·log(fPD). LPLL_flat is the single side band phase noise in a 1 Hz Bandwidth and fPD is the phase detector frequency of , 0.13 0.10 0.09 0.07 0.07 0.06 0.06 0.05 0.05 0.04 0.04 Imaginary -2.70 -3.04 -2.67 -1.63 -1.22 -0.92 , 0.10 0.09 0.08 0.07 0.07 0.07 0.06 0.06 0.05 0.05 Powered Down (k) Imaginary -8.14 -6.72 -5.24 -2.94 Texas Instruments
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SNAS252R ISO/TS16949
Abstract: Range vOSCin Oscillator Sensitivity fPD 100 -100 uA uA Phase Detector Frequency 5 , ·log(fPD). LPLL_flat is the single side band phase noise in a 1 Hz Bandwidth and fPD is the phase detector , -0.56 0.56 0.09 -0.95 0.95 80 0.07 -0.50 0.50 0.08 -0.86 0.87 90 0.07 -0.46 0.46 0.07 -0.80 0.80 100 0.06 -0.41 0.42 0.07 -0.72 0.72 110 0.06 -0.37 0.38 0.07 -0.65 0.65 120 0.05 -0.34 0.34 0.06 -0.59 National Semiconductor
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311500
Abstract: LMX2531LQ2265E/ 2570E LMX2531LQ2820E/ 3010E All Other Options ICCPD IIHOSC IILOSC fOSCin vOSCin fPD Power Down , Normalized PLL noise floor, LNPLL_flat, and is defined as: LNPLL_flat = L(f) ­ 20·log(N) ­ 10·log(fPD). LPLL_flat is the single side band phase noise in a 1 Hz Bandwidth and fPD is the phase detector frequency of , 0.13 0.10 0.09 0.07 0.07 0.06 0.06 0.05 0.05 0.04 0.04 Imaginary -2.70 -3.04 -2.67 -1.63 -1.22 -0.92 , 0.10 0.09 0.08 0.07 0.07 0.07 0.06 0.06 0.05 0.05 Powered Down (k) Imaginary -8.14 -6.72 -5.24 -2.94 Texas Instruments
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312080EB 311415E 312570EC 2820E 311700EB LMX2531LQ1742 LMX2531LQ1778E LMX2531LQ1910E LMX2531LQ2080E LMX2531LQ2265E LMX2531LQ2570E
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