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SN54HC273VTDG1 Texas Instruments Octal D-Type Flip Flops With - Clear, SN54HC273-DIE 0- ri Buy
SN54HC273VTDG2 Texas Instruments Octal D-Type Flip Flops With - Clear, SN54HC273-DIE 0- ri Buy
SN74HCT273ANSR Texas Instruments Octal D-Type Flip-Flops With Clear 20-SO ri Buy

flip flop T (Toggle)

Catalog Datasheet Results Type PDF Document Tags
Abstract: PSoC CreatorTM Component Datasheet ® Toggle Flip Flop 1.0 Features T input toggles Q value Configurable width for array of Toggle Flip Flops General Description The Toggle Flip Flop captures a digital value that can be toggled. When to Use a Toggle Flip Flop Use the Toggle Flip Flop , and output connections for the Toggle Flip Flop. t ­ Input This input determines whether to toggle , Flop is implemented in PLD macrocells using the built-in T Flip Flop mode. Table 1. 1-ArrayWidth Toggle ... Original
datasheet

3 pages,
68.47 Kb

flip flop T Toggle datasheet abstract
datasheet frame
Abstract: , 2012 SR Flip Flop PSoC CreatorTM Component Datasheet ® Component Parameters Drag a Toggle , PSoC CreatorTM Component Datasheet ® SR Flip Flop 1.0 Features Clocked for safe use in synchronous circuits. Configurable width for array of SR Flip Flops. General Description The SR Flip Flop stores a digital value that can be set or reset. When to Use an SR Flip Flop Use the SR Flip Flop to , connections for the SR Flip Flop. s ­ Input This input sets the output (to logic high `1'). The output ... Original
datasheet

3 pages,
107.76 Kb

high frequency flip flop S-R flip flop clock sr flip flop datasheet abstract
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Abstract: override the clock, settmg both the master and the slave portions of the flip flop A low-level clock state , flip-flop are internally offset to give a "raceiess" flip flop (i.e., the master is disabled before the , of the clock waveforms This single-phase Type D flip flop may be used in both counter and shift reg^ , Pulse Out M *cc Gnd 1,14 1,14 1.14 1.14 1,14 1,14 1,14 1,14 1,14 1,14 1 + 1.2 Vdc) Z 3 ^ t , K »lip flop in applications such as single-rail operation Since a true master slave design is ... OCR Scan
datasheet

5 pages,
109.22 Kb

rs FLIPFLOP SCHEMATIC delay reset flip flop MC1034 MC1000/1200 MC1000/1200 abstract
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Abstract: MITSUBISHI LSTTLs M74LS73AP M74LS73AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH RESET DESCRIPTION , conditions were established. Toggle • complement of previous state with I transition of outputs T RD J K Q Q , NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH RESET ABSOLUTE MAXIMUM RATINGS (Ta=-20~+75r, unless otherwise noted , -20- +75 t Tstg Storage temperature range -65 - + 150 r RECOMMENDED OPERATING CONDITIONS (Ta = -20 , M74LS73AP M74LS73AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH RESET Note 4: Measurement circuit Vcc M i The ... OCR Scan
datasheet

4 pages,
216.19 Kb

M74LS73AP 20-PIN M74LS107AP datasheet abstract
datasheet frame
Abstract: state machine is probably the toggle (T) flip flop, which can operate at 416 MHz on the fastest , roadblock is the clock to output time for the T flip flop. Toggle flip flops have value in that fast , results in the upper speed limit being that of the T flip flop toggle rates. Other versions of this , the expression: FMAX = 1/(TSU + TCO) This is a bare flip flop. In the programmable logic world, it , viewpoint on a digital device. Flip flop switching speed is typically limited by the sum of setup time (TSU ... Original
datasheet

9 pages,
65.48 Kb

XAPP379 CoolRunner-II CPLD flip flop T Toggle FLIP FLOP toggle COOLRUNNER-II XAPP375 XAPP376 XAPP377 XAPP378 verilog code for johnson counter COOLRUNNER-II 7 segment t flip flop XAPP379 abstract
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Abstract: preset/clear and scan D-flip flop with preset D-flip flop with preset/scan J-K flip flop J-K flip flop with scan J-K flip flop with clear J-K flip flop with clear/scan J-K flip flop with preset/clear J-K flip flop with preset/clear and scan Toggle flip flop with clear Toggle flip flop with preset D-flip , ) Name Flip Flop FD1x FD1SX FD2x FD2Sx FD3x FD3SX FD4x FD4Sx FJK1X FJKISx FJK2X FJK2SX FJK3X FJK3SX FT2x , , fanout=2) 150 MHz maximum toggle frequency Performance optimization with standard and high drive ... OCR Scan
datasheet

8 pages,
661.5 Kb

SC21C1 siemens Nand gate SC17C1 programmable slew rate control IO JK flip flop IC diagram scxc1 SR flip flop IC pin diagram JK flip flop IC SC11C1 jk flip flop to d flip flop conversion TC110G toshiba tc110g SR flip flop IC datasheet abstract
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Abstract: flop with setf/reset 11 (4) Toggle flip flops 121 TFR Toggle flip flop with reset 8 (3) 122 F312 Toggle flip flop with reset 7 (3) 123 F313 Toggle flip flop with set 7 (3) 124 F314 Toggle flip flop with set/reset 8 (3) 125 TFR1 Toggle flip flop with reset 7 (3) 126 F316 Toggle flip flop with set 7 (3) 127 F317 Toggle flip flop with set/reset 8 (3) 128 F325 Toggle flip flop with reset 7 (4) 129 F326 Toggle flip flop with set 7 (4) 130 F327 Toggle flip flop with sit/reset 8 (4) 131 TFRE ... OCR Scan
datasheet

30 pages,
733.51 Kb

74183 alu 74259 74169 binary counter 74151 adder priority encoder 74147 decoder 3-8 74ls with nor gate TTL 74139 74138 logic circuit 74139 Dual 2 to 4 line decoder 74139 demultiplexer 74118 design excess 3 counter using 74161 74541 buffer datasheet abstract
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Abstract: the zero to < 50 % is obtained by the UC3844 UC3844 and UC3845 UC3845 by the addition of an internal toggle flip flop which blanks the output off every other clock cycle. BLOCK DIAGRAM (toggle flip flop used only , /= T SGS-THOMSON * 7#. R f f ln © ® @ n [ L [ i( O T M a © i UC2842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 UC3842/3/4/5 _ CURRENT MODE PWM CONTROLLER For complete specification refer to ' Unear & Switching Voltage Regulators Appl. M a n u a l( Order Code AMLISVOREST/1) ! OPTIMIZED FOR OFF-LINE AND DC TO DC ... OCR Scan
datasheet

1 pages,
42.09 Kb

uc3844 uc3845 applications uc-3843 dc dc uc3843 UC3845 dc dc applications UC3845 uc3843 U3844 UC3842 UC2842/3/4/5 UC3842/3/4/5 UC2842/3/4/5 abstract
datasheet frame
Abstract: MITSUBISHI LSTTLs M74LS109AP M74LS109AP DUAL J-K POSITIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET , L L H H H î H L Toggle H H î L H 0° Q° H H T H H H L PIN CONFIGURATION (TOP VIEW) DIRECT _ , M74LS109AP M74LS109AP DUAL J-K POSITIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET RECOMMENDED OPERATING CONDITIONS , DUAL J-K POSITIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET TIMING REQUIREMENTS (Vcc= 5 V, Ta = 25r , flip-flop circuits with discrete terminals for clock input T, inputs J and K, and direct set and reset ... OCR Scan
datasheet

4 pages,
244.28 Kb

20-PIN JK flip flop IC Toggle flip flop IC T flip flop pin configuration M74LS109AP RS flip flop IC 74LS109AP 74LS109AP abstract
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Abstract: M ITSUBISHI L S T T L s M74LS76AP M74LS76AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH S E T AND R , R K MITSUBISHI L S T T Ls M 74LS76AP 74LS76AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND , T L s M 74LS76AP 74LS76AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH S E T AND R ESET TIMING , edge-triggered flip -flo p circuits w ith discrete terminals fo r clock input T , inputs J and K and direct set , independently D irect set and reset inputs Q and Q outputs Wide operating temperature range ( T a = -2 0 ~ + 7 ... OCR Scan
datasheet

4 pages,
226.39 Kb

T flip flop pin configuration 74LS76AP M74LS76AP M74LS76AP abstract
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Datasheet Content (non pdf)

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Over 1.1 million files (1986-2014): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer.
 
equation. I CC (opr) = C PD w V CC w f IN + I CC /2 (per FLIP/FLOP) M54/M74HC73 M54/M74HC73 M54/M74HC73 M54/M74HC73 5/11 SWITCHING Datasheet DUAL J-K FLIP FLOP WITH PRESET AND Raw Text Format M54HC73 M54HC73 M54HC73 M54HC73 M74HC73 M74HC73 M74HC73 M74HC73 October 1992 DUAL J-K FLIP FLOP WITH PRESET high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated in silicon gate C 2 MOS technology. It has POWER DISSIPATION I CC = 2 m A (MAX.) AT T A = 25 5C . HIGH NOISE IMMUNITY V NIH = V NIL = 28
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1999.htm
STMicroelectronics 20/10/2000 10.88 Kb HTM 1999.htm
(opr) = C PD w V CC w f IN + I CC /2 (per FLIP/FLOP) M54/M74HC73 M54/M74HC73 M54/M74HC73 M54/M74HC73 5/11 SWITCHING CHARACTERISTICS TEST M74HC73 M74HC73 M74HC73 M74HC73 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Document Number: 1999 Date : Portable Document Format and Raw Text Format M54HC73 M54HC73 M54HC73 M54HC73 M74HC73 M74HC73 M74HC73 M74HC73 October 1992 DUAL J-K FLIP FLOP CC or Ground Current + 50 mA P D Power Dissipation 500 (*) mW T stg Storage Temperature -65 to +150 o LOW POWER DISSIPATION I CC = 2 m A (MAX.) AT T A = 25 5C . HIGH NOISE IMMUNITY V NIH = V NIL = 28 % V
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1999-v2.htm
STMicroelectronics 14/06/1999 8.44 Kb HTM 1999-v2.htm
+ I CC /2 (per FLIP/FLOP) M54/M74HC113 M54/M74HC113 M54/M74HC113 M54/M74HC113 5/11 SWITCHING CHARACTERISTICS TEST WAVEFORM TEST Datasheet DUAL J-K FLIP FLOP WITH PRESET M54HC113 M54HC113 M54HC113 M54HC113 M74HC113 M74HC113 M74HC113 M74HC113 October 1992 DUAL J-K FLIP FLOP WITH PRESET B1R (Plastic Package) ORDER CODES FUNCTION COMPATIBLE WITH 54/74LS113 54/74LS113 54/74LS113 54/74LS113 The M54/74HC113 M54/74HC113 M54/74HC113 M54/74HC113 is a high speed CMOS DUAL J- K FLIP FLOP WITH PRESET . HIGH SPEED f MAX = 71 MHz (TYP.) at V CC = 5 V . LOW POWER DISSIPATION I CC = 2 m A at T
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1892.htm
STMicroelectronics 20/10/2000 11.06 Kb HTM 1892.htm
(opr) = C PD w V CC w f IN + I CC /2 (per FLIP/FLOP) M54/M74HC113 M54/M74HC113 M54/M74HC113 M54/M74HC113 5/11 SWITCHING CHARACTERISTICS TEST M74HC113 M74HC113 M74HC113 M74HC113 DUAL J-K FLIP FLOP WITH PRESET Document Number: 1892 Date Update Document Format and Raw Text Format M54HC113 M54HC113 M54HC113 M54HC113 M74HC113 M74HC113 M74HC113 M74HC113 October 1992 DUAL J-K FLIP FLOP WITH WITH 54/74LS113 54/74LS113 54/74LS113 54/74LS113 The M54/74HC113 M54/74HC113 M54/74HC113 M54/74HC113 is a high speed CMOS DUAL J- K FLIP FLOP WITH PRESET fabricated in DISSIPATION I CC = 2 m A at T A = 25 5C . HIGH NOISE IMMUNITY V NIH = V NIL = 28 % V CC (MIN.) . OUTPUT DRIVE
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1892-v1.htm
STMicroelectronics 02/04/1999 8.67 Kb HTM 1892-v1.htm
equation. I CC (opr) = C PD w V CC w f IN + I CC /2 (per FLIP/FLOP) M54/M74HC113 M54/M74HC113 M54/M74HC113 M54/M74HC113 5 M54HC113 M54HC113 M54HC113 M54HC113 M74HC113 M74HC113 M74HC113 M74HC113 October 1992 DUAL J-K FLIP FLOP WITH PRESET B1R (Plastic Package) ORDER CODES high speed CMOS DUAL J- K FLIP FLOP WITH PRESET fabricated in silicon gate C2MOS technology. It has GND DC V CC or Ground Current + 50 mA P D Power Dissipation 500 (*) mW T stg Storage Datasheet DUAL J-K FLIP
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1892-v3.htm
STMicroelectronics 25/05/2000 10.46 Kb HTM 1892-v3.htm
CC w f IN + I CC /2 (per FLIP/FLOP) M54/M74HC73 M54/M74HC73 M54/M74HC73 M54/M74HC73 5/11 SWITCHING CHARACTERISTICS TEST M54HC73 M54HC73 M54HC73 M54HC73 M74HC73 M74HC73 M74HC73 M74HC73 October 1992 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR B1R (Plastic Package M54/74HC73 M54/74HC73 M54/74HC73 M54/74HC73 is a high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated in silicon gate C 2 Ground Current + 50 mA P D Power Dissipation 500 (*) mW T stg Storage Temperature -65 to +150 Datasheet DUAL J-K FLIP
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1999-v3.htm
STMicroelectronics 25/05/2000 10.27 Kb HTM 1999-v3.htm
(opr) = C PD w V CC w f IN + I CC /2 (per FLIP/FLOP) M54/M74HC73 M54/M74HC73 M54/M74HC73 M54/M74HC73 5/11 SWITCHING CHARACTERISTICS TEST M74HC73 M74HC73 M74HC73 M74HC73 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Document Number: 1999 Date : Portable Document Format and Raw Text Format M54HC73 M54HC73 M54HC73 M54HC73 M74HC73 M74HC73 M74HC73 M74HC73 October 1992 DUAL J-K FLIP FLOP CC or Ground Current + 50 mA P D Power Dissipation 500 (*) mW T stg Storage Temperature -65 to +150 o LOW POWER DISSIPATION I CC = 2 m A (MAX.) AT T A = 25 5C . HIGH NOISE IMMUNITY V NIH = V NIL = 28 % V
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1999-v1.htm
STMicroelectronics 02/04/1999 8.48 Kb HTM 1999-v1.htm
(opr) = C PD w V CC w f IN + I CC /2 (per FLIP/FLOP) M54/M74HC113 M54/M74HC113 M54/M74HC113 M54/M74HC113 5/11 SWITCHING CHARACTERISTICS TEST M74HC113 M74HC113 M74HC113 M74HC113 DUAL J-K FLIP FLOP WITH PRESET Document Number: 1892 Date Update Document Format and Raw Text Format M54HC113 M54HC113 M54HC113 M54HC113 M74HC113 M74HC113 M74HC113 M74HC113 October 1992 DUAL J-K FLIP FLOP WITH WITH 54/74LS113 54/74LS113 54/74LS113 54/74LS113 The M54/74HC113 M54/74HC113 M54/74HC113 M54/74HC113 is a high speed CMOS DUAL J- K FLIP FLOP WITH PRESET fabricated in DISSIPATION I CC = 2 m A at T A = 25 5C . HIGH NOISE IMMUNITY V NIH = V NIL = 28 % V CC (MIN.) . OUTPUT DRIVE
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1892-v2.htm
STMicroelectronics 14/06/1999 8.64 Kb HTM 1892-v2.htm
M54HC107 M54HC107 M54HC107 M54HC107 M74HC107 M74HC107 M74HC107 M74HC107 October 1992 DUAL J-K FLIP FLOP WITH CLEAR B1R (Plastic Package) ORDER CODES high speed CMOS DUAL J- K FLIP FLOP fabricated in silicon gate C 2 MOS tech- nology. It has the Current + 50 mA P D Power Dissipation 500 (*) mW T stg Storage Temperature -65 to +150 o C CC /2 (per FLIP/FLOP) M54/M74HC107 M54/M74HC107 M54/M74HC107 M54/M74HC107 5/11 SWITCHING CHARACTERISTICS TEST TRANSITION TIME OF Datasheet DUAL J-K FLIP
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1888-v3.htm
STMicroelectronics 25/05/2000 10.25 Kb HTM 1888-v3.htm
M74HC107 M74HC107 M74HC107 M74HC107 DUAL J-K FLIP FLOP WITH CLEAR Document Number: 1888 Date Update Document Format and Raw Text Format M54HC107 M54HC107 M54HC107 M54HC107 M74HC107 M74HC107 M74HC107 M74HC107 October 1992 DUAL J-K FLIP FLOP WITH COMPATIBLE WITH 54/74LS107 54/74LS107 54/74LS107 54/74LS107 The M54/74HC107 M54/74HC107 M54/74HC107 M54/74HC107 is a high speed CMOS DUAL J- K FLIP FLOP fabricated in silicon /2 (per FLIP/FLOP) M54/M74HC107 M54/M74HC107 M54/M74HC107 M54/M74HC107 5/11 SWITCHING CHARACTERISTICS TEST TRANSITION TIME OF INPUT DISSIPATION I CC = 2 m A (MAX.) AT T A = 25 5C . HIGH NOISE IMMUNITY V NIH = V NIL = 28 % V CC (MIN.) . OUTPUT
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1888-v2.htm
STMicroelectronics 14/06/1999 8.42 Kb HTM 1888-v2.htm