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HCS109HMSR Intersil Corporation HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC16, DIE-16 pdf Buy
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FLIP-N-CLICK MikroElektronika Arduino Duo compatible on one side and 4 mikroBus on the other 43 from $32.99 (Sep 2016) Allied Electronics Buy
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flip flop T (Toggle)

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: PSoC CreatorTM Component Datasheet ® Toggle Flip Flop 1.0 Features T input toggles Q value Configurable width for array of Toggle Flip Flops General Description The Toggle Flip Flop , and output connections for the Toggle Flip Flop. t ­ Input This input determines whether to toggle , Flop is implemented in PLD macrocells using the built-in T Flip Flop mode. Table 1. 1-ArrayWidth Toggle Flip Flop Truth Table QPREV 0 0 1 1 T 0 1 0 1 Q 0 1 1 0 Page 2 of 3 Document Number: 001-84903 ... Cypress Semiconductor
Original
datasheet

3 pages,
68.47 Kb

TOGGLE FLIP FLOP flip flop T Toggle flip flop T TEXT
datasheet frame
Abstract: L205 D-type latch with reset 4 (2) D-type flip flops 94 DFF D-type flip flop 6 (3) 95 DFR D-type flip flop with reset 8 (3) 96 F112 D-type flip flop with reset 7 (3) 97 F113 D-type flip flop with set 7 (3) 98 DF D-type flip flop with set/reset 9 (3) 99 F114 D-type flip flop with set/reset 8 (3) 100 F115 D-type flip flop with reset 7 (3) 101 F116 D-type flip flop with sit 7 (3) 102 DF1 D-type flip flop with set /reset 8 (3) 103 F121 D-type flip flop 6 (4) 104 F125 D-type flip flop with ... OCR Scan
datasheet

30 pages,
733.51 Kb

74169 binary counter 74373 cmos dual s-r latch TTL 74139 74138 logic circuit Multiplexer 74152 74139 Dual 2 to 4 line decoder decoder 3-8 74ls with nor gate 74118 7493 Decade Counter 74139 demultiplexer two 3 to 8 decoders 74138 design excess 3 counter using 74161 MSM70H000 MSM70H000 74541 buffer MSM70H000 MSM70H000 jk flip flop to d flip flop conversion MSM70H000 MSM70H000 alu 74381 MSM70H000 MSM70H000 priority encoder 74148 MSM70H000 MSM70H000 ttl 74118 MSM70H000 MSM70H000 design a bcd counter using jk flip flop MSM70H000 MSM70H000 74139 for bcd to excess 3 code MSM70H000 MSM70H000 MSM70H000 MSM70H000 MSM70H000 MSM-71H000 MSM72H000 MSM73H000 MSM74H000 MSM79H000 MSM75H000 MSM-76H000 MSM77H000 MSM78H000 TEXT
datasheet frame
Abstract: the expression: FMAX = 1/(TSU + TCO) This is a bare flip flop. In the programmable logic world, it , times. The simplest state machine is probably the toggle (T) flip flop, which can operate at 416 MHz on , met, so the only roadblock is the clock to output time for the T flip flop. Toggle flip flops have , CPLD products and results in the upper speed limit being that of the T flip flop toggle rates. Other , viewpoint on a digital device. Flip flop switching speed is typically limited by the sum of setup time (TSU ... Xilinx
Original
datasheet

9 pages,
65.48 Kb

XAPP379 CoolRunner-II CPLD flip flop T Toggle FLIP FLOP toggle COOLRUNNER-II XAPP375 XAPP377 XAPP378 XAPP376 verilog code for johnson counter COOLRUNNER-II 7 segment t flip flop TEXT
datasheet frame
Abstract: T oggle Flip Flop. T oggles every time the 24-bit counter equals the 24-bit Preset Register , low true 0 1 Carry toggle flip flop (starts out low ) 1 0 Carry - high true 1 1 24 , -4 Pin 17 F unction 0 0 Borrow - low true 1 0 Borrow toggle flip flop (starts out low ) 1 0 , it-5 B it-4 Pin F unction Carry - low true Carry toggle flip flop (starts out low ) Carry - high , -5 B it-4 P in F unction Borrow - low true Borrow toggle flip flop (starts out low ) Borrow - high ... OCR Scan
datasheet

2 pages,
107.1 Kb

LS7166 TEXT
datasheet frame
Abstract: following: Bit-5 Bit-4 Pin 16 Function 0 0 Carry - low true 0 1 Carry toggle flip flop (starts out , Borrow toggle flip flop (starts out low) 1 0 Borrow - high true 1 1 24-bit Comparator/Counter match , -4 Pin Function 0 0 Carry - low true 0 1 Carry toggle flip flop (starts out low) 1 0 Carry - , -4 Pin Function 0 0 Borrow - low true 0 1 Borrow toggle flip flop (starts out low) 1 0 Borrow - , match. Thus there is a 1-clock delay between the input and output of each flip flop. Unless otherwise ... US Digital
Original
datasheet

3 pages,
119.27 Kb

LS7166 TEXT
datasheet frame
Abstract: following: Bit-5 Bit-4 Pin 16 Function 0 0 Carry - low true 0 1 Carry toggle flip flop (starts out , Borrow toggle flip flop (starts out low) 1 0 Borrow - high true 1 1 24-bit Comparator/Counter match , -5 Bit-4 Pin Function 0 0 Carry - low true 0 1 Carry toggle flip flop (starts out low) 1 0 Carry , : Bit-5 Bit-4 Pin Function 0 0 Borrow - low true 0 1 Borrow toggle flip flop (starts out low) 1 , flip flop. Unless otherwise specified, assume the longest prop delay from any input to any output is ... US Digital
Original
datasheet

3 pages,
151.01 Kb

LS7166 TEXT
datasheet frame
Abstract: PSoC CreatorTM Component Datasheet ® SR Flip Flop 1.0 Features Clocked for safe use in synchronous circuits. Configurable width for array of SR Flip Flops. General Description The SR Flip Flop stores a digital value that can be set or reset. When to Use an SR Flip Flop Use the SR Flip Flop to , connections for the SR Flip Flop. s ­ Input This input sets the output (to logic high `1'). The output , , 2012 SR Flip Flop PSoC CreatorTM Component Datasheet ® Component Parameters Drag a Toggle ... Cypress Semiconductor
Original
datasheet

3 pages,
107.76 Kb

high frequency flip flop S-R flip flop clock sr flip flop TEXT
datasheet frame
Abstract: Primitive Cells (Cont.) Name Flip Flop FD1x FD1SX FD2x FD2Sx FD3x FD3SX FD4x FD4Sx FJK1X FJKISx FJK2X , J-K flip flop J-K flip flop with scan J-K flip flop with clear J-K flip flop with clear/scan J-K flip flop with preset/clear J-K flip flop with preset/clear and scan Toggle flip flop with clear Toggle flip , Temperature Symbol V DD Basic Cell Delay vs. Fanout (SCxC1 VDD =5 V, T a =25°C with estimated wiring lengths) Rating -0.3 to +7.0 - 0.3 to V qq + 0.3 - 0.3 to V qq + 0.3 -4 0 to +125 Unit V V V Basic Cell ... OCR Scan
datasheet

8 pages,
661.5 Kb

SC21C1 SC17C1 Toggle flip flop IC LD-3x siemens pg 740 SC75C1 programmable slew rate control IO scxc1 full adder circuit using nor gates SR flip flop IC pin diagram siemens Nand gate bt10s JK flip flop IC SC11C1 jk flip flop to d flip flop conversion TC110G toshiba tc110g SR flip flop IC siemens master drive circuit diagram TEXT
datasheet frame
Abstract: and will override the clock, settmg both the master and the slave portions of the flip flop A , portions of the flip-flop are internally offset to give a "raceiess" flip flop (i.e., the master is , rise and »all times of the clock waveforms This single-phase Type D flip flop may be used in both , + 1.2 Vdc) Z 3 ^ t Output level to be measured after clock transition on pin 6 or 8 through (-TU , advantages over the J K »lip flop in applications such as single-rail operation Since a true master slave ... OCR Scan
datasheet

5 pages,
109.22 Kb

Single Toggle Flip Flop rs FLIPFLOP SCHEMATIC delay reset flip flop MC1034 MCI000/1200 TEXT
datasheet frame
Abstract: toggle flip flop (starts out low) 1 0 Borrow - high true 1 1 24-bit Comparitor/Counter match - high , input and output o f each flip flop. Unless otherwise specified, assume the longest prop delay from , triggered. Bit-2: Compare Toggle Flip Flop. Toggles every time the 24-bit counter equals the 24-bit Preset , -5 Bit-4 Pin 16 Function 0 0 Carry - low true 0 1 Carry toggle flip flop (starts out low) 1 0 , T C 7 1 E n c o d e r to Microprocessor L S/lOft Interface Chip V. ^ T e c h n ic a l D ata ... OCR Scan
datasheet

4 pages,
241.82 Kb

TEXT
datasheet frame

Archived Files

Abstract Saved from Date Saved File Size Type Download
following equation. I CC (opr) = C PD w V CC w f IN + I CC /2 (per FLIP/FLOP) M54/M74HC76 M54/M74HC76 5/11 SWITCHING ST | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR M74HC76 M74HC76 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Document Number: 2002 Date Update: 09 Document Format and Raw Text Format M54HC76 M54HC76 M74HC76 M74HC76 October 1992 DUAL J-K FLIP FLOP WITH FUNCTION COMPATIBLE WITH 54/74LS76 54/74LS76 The M54/74HC76 M54/74HC76 is a high speed CMOS DUAL J-K FLIP FLOP fabricated in
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/2002-v1.htm
STMicroelectronics 02/04/1999 8.61 Kb HTM 2002-v1.htm
V CC w f IN + I CC /2 (per FLIP/FLOP) M54/M74HC113 M54/M74HC113 5/11 SWITCHING CHARACTERISTICS TEST WAVEFORM TEST ST | DUAL J-K FLIP FLOP WITH PRESET M74HC113 M74HC113 DUAL J-K FLIP FLOP WITH PRESET Document Number: 1892 Date Update: 09/04/94 Pages Text Format M54HC113 M54HC113 M74HC113 M74HC113 October 1992 DUAL J-K FLIP FLOP WITH PRESET B1R (Plastic /74LS113 /74LS113 The M54/74HC113 M54/74HC113 is a high speed CMOS DUAL J- K FLIP FLOP WITH PRESET fabricated in silicon gate
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1892-v1.htm
STMicroelectronics 02/04/1999 8.67 Kb HTM 1892-v1.htm
obtained by the following equation. I CC (opr) = C PD w V CC w f IN + I CC /2 (per FLIP/FLOP) M54/M74HC73 M54/M74HC73 5 ST | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Datasheet DUAL J-K FLIP FLOP WITH PRESET AND CLEAR M74HC73 M74HC73 M54HC73 M54HC73 M74HC73 M74HC73 October 1992 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR B1R (Plastic Package) ORDER CODES speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated in silicon gate C 2 MOS technology. It has the same
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1999.htm
STMicroelectronics 20/10/2000 10.88 Kb HTM 1999.htm
can be obtained by the following equation. I CC (opr) = C PD w V CC w f IN + I CC /2 (per FLIP/FLOP ST | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR M74HC73 M74HC73 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Document Number: 1999 Date Update: 09 Document Format and Raw Text Format M54HC73 M54HC73 M74HC73 M74HC73 October 1992 DUAL J-K FLIP FLOP WITH COMPATIBLE WITH 54/74LS73 54/74LS73 The M54/74HC73 M54/74HC73 is a high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated in
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1999-v1.htm
STMicroelectronics 02/04/1999 8.48 Kb HTM 1999-v1.htm
can be obtained by the following equation. I CC (opr) = C PD w V CC w f IN + I CC /2 (per FLIP/FLOP ST | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR M74HC73 M74HC73 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Document Number: 1999 Date Update: 09 Document Format and Raw Text Format M54HC73 M54HC73 M74HC73 M74HC73 October 1992 DUAL J-K FLIP FLOP WITH COMPATIBLE WITH 54/74LS73 54/74LS73 The M54/74HC73 M54/74HC73 is a high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated in
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1999-v2.htm
STMicroelectronics 14/06/1999 8.44 Kb HTM 1999-v2.htm
ST | DUAL J-K FLIP FLOP WITH CLEAR M74HC107 M74HC107 DUAL J-K FLIP FLOP WITH CLEAR Document Number: 1888 Date Update: 09/04/94 Pages Text Format M54HC107 M54HC107 M74HC107 M74HC107 October 1992 DUAL J-K FLIP FLOP WITH CLEAR B1R (Plastic WITH 54/74LS107 54/74LS107 The M54/74HC107 M54/74HC107 is a high speed CMOS DUAL J- K FLIP FLOP fabricated in silicon gate C 2 current can be obtained by the following equation. I CC (opr) = C PD w V CC w f IN + I CC /2 (per FLIP
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1888-v2.htm
STMicroelectronics 14/06/1999 8.42 Kb HTM 1888-v2.htm
following equation. I CC (opr) = C PD w V CC w f IN + I CC /2 (per FLIP/FLOP) M54/M74HC76 M54/M74HC76 5/11 SWITCHING ST | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR M74HC76 M74HC76 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Document Number: 2002 Date Update: 09 Document Format and Raw Text Format M54HC76 M54HC76 M74HC76 M74HC76 October 1992 DUAL J-K FLIP FLOP WITH FUNCTION COMPATIBLE WITH 54/74LS76 54/74LS76 The M54/74HC76 M54/74HC76 is a high speed CMOS DUAL J-K FLIP FLOP fabricated in
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/2002-v2.htm
STMicroelectronics 14/06/1999 8.57 Kb HTM 2002-v2.htm
ST | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR M74HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Document Number: 1891 Date Update: 09 Document Format and Raw Text Format M54HC112 M54HC112 M74HC112 M74HC112 October 1992 DUAL J-K FLIP FLOP GND DC V CC or Ground Current + 50 mA P D Power Dissipation 500 (*) mW T stg Storage Temperature -65 current can be obtained by the following equation. I CC (opr) = C PD w V CC w f IN + I CC /2 (per FLIP
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1891-v1.htm
STMicroelectronics 02/04/1999 8.79 Kb HTM 1891-v1.htm
ST | DUAL J-K FLIP FLOP WITH PRESET Datasheet DUAL J-K FLIP FLOP WITH PRESET M74HC113 M74HC113 Document Format M74HC113 M74HC113 October 1992 DUAL J-K FLIP FLOP WITH PRESET B1R (Plastic Package) ORDER CODES : M54HC113F1R M54HC113F1R /74LS113 /74LS113 The M54/74HC113 M54/74HC113 is a high speed CMOS DUAL J- K FLIP FLOP WITH PRESET fabricated in silicon gate CC or I GND DC V CC or Ground Current + 50 mA P D Power Dissipation 500 (*) mW T stg
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1892-v3.htm
STMicroelectronics 25/05/2000 10.46 Kb HTM 1892-v3.htm
V CC w f IN + I CC /2 (per FLIP/FLOP) M54/M74HC113 M54/M74HC113 5/11 SWITCHING CHARACTERISTICS TEST WAVEFORM TEST ST | DUAL J-K FLIP FLOP WITH PRESET M74HC113 M74HC113 DUAL J-K FLIP FLOP WITH PRESET Document Number: 1892 Date Update: 09/04/94 Pages Text Format M54HC113 M54HC113 M74HC113 M74HC113 October 1992 DUAL J-K FLIP FLOP WITH PRESET B1R (Plastic /74LS113 /74LS113 The M54/74HC113 M54/74HC113 is a high speed CMOS DUAL J- K FLIP FLOP WITH PRESET fabricated in silicon gate
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1892-v2.htm
STMicroelectronics 14/06/1999 8.64 Kb HTM 1892-v2.htm