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CS47L90-CWZR Cirrus Logic PCM Codec visit Digikey
CS42888-CQZ Cirrus Logic PCM Codec, 1-Func, CMOS, PQFP64, LEAD FREE, MS-026, LQFP-64 visit Digikey
CS42888-DQZR Cirrus Logic PCM Codec, 1-Func, CMOS, PQFP64, LEAD FREE, MS-026, LQFP-64 visit Digikey
CS42888-DQZ Cirrus Logic PCM Codec, 1-Func, CMOS, PQFP64, LEAD FREE, MS-026, LQFP-64 visit Digikey
CS42888-CQZR Cirrus Logic PCM Codec, 1-Func, CMOS, PQFP64, LEAD FREE, MS-026, LQFP-64 visit Digikey
WM8580AGEFT/V Cirrus Logic PCM Codec, 1-Func, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, LEAD FREE, MS-026ABC, TQFP-48 visit Digikey

fft fpga code

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Abstract: FFT FPGA Co-Processor Functional Description Figure 5 shows the TI Code Composer Studio software , easily interfaces to a digital signal processor. Designers can adapt the FFT FPGA co-processor reference , . Figure 1 shows the FFT FPGA co-processor reference design block diagram. Figure 1. FFT FPGA , Board Altera Corporation FFT FPGA Co-Processor Functional Description The direct memory access , Preliminary Altera Corporation FFT FPGA Co-Processor Functional Description Atlantic Interface The Altera
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verilog code for FFT 32 point vhdl code for FFT 32 point verilog code 16 bit processor fft tms320c6416 emif verilog code for 64 point fft verilog code for FFT TMS320C6000 TMS320C6416 EP2C35
Abstract: Instruments Code Composer Studio version 2.21 or higher Hardware Requirements To run the FFT FPGA , Description FPGA Co-Processor Functional Description Figure 1 illustrates the FFT FPGA co-processor reference design block diagram. Figure 1. FFT FPGA Co-Processor Block Diagram Texas Instruments , co-processor consumes or produces data. In this FFT FPGA co-processor reference design, the co-processor is , description of the FFT FPGA co-processor reference design signals. Table 4. FFT FPGA Co-Processor Altera
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vhdl code for radix-4 fft vhdl code for 16 point radix 2 FFT TMS320C6416 DSP Starter Kit DSK vhdl source code for fft EMIF sdram full example code Altera fft megacore EP2S60F1020C4 EP2S60 800-EPLD
Abstract: FPGA Co-Processor Functional Description Figure 1 illustrates the FFT FPGA co-processor reference design block diagram. Figure 1. FFT FPGA Co-Processor Block Diagram Texas Instruments TMS320C6416 , consumes or produces data. In this FFT FPGA co-processor reference design, the co-processor is connected , the FFT FPGA co-processor reference design signals. Table 4. FFT FPGA Co-Processor Reference , Design Table 4. FFT FPGA Co-Processor Reference Design Signal Descriptions Signal Name Width Altera
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EP2S180F1020C3 EP2S180 64 point FFT radix-4 VHDL documentation TMS320C6416 DSK TMS320C6416 DSK usb asynchronous fifo vhdl EMIF c program example verilog code for FFT 16 point
Abstract: 's Code Composer Studio tool. The EMIF base address of the FPGA in chip select two memory space is , a complex FFT applied to the input data. Figure 11. Code Composer Studio Output Getting Started , FPGA Peripheral Expansion & FPGA Co-Processing with a TI TMS320C6000 Application Note 352 , (FFT) co-processor and an LED peripheral provide examples of how a system can be developed using , board, which features a TI DM642 digital media processor and an Altera EP1C20 CycloneTM FPGA. For more Altera
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emif vhdl fpga verilog code for stepper motor vhdl code for stepper motor DMEK 642 verilog code to generate sine wave fft butterfly verilog code DMDK642 C6000 AN-352-1
Abstract: Implementing FFT in an FPGA Co-Processor Sheac Yee Lim Andrew Crosland Altera Corporation , to improve overall system performance. For example, an FFT FPGA co-processor implementation that , about a 9.06 s transform time [3]. 3. IMPLEMENTING AN FFT ALGORITHM AS AN FPGA CO-PROCESSOR The , For the purposes of this paper, we have selected an FFT algorithm for implementation as an FPGA , , where nx is the length of the FFT in complex samples. Figure 1. FFT FPGA Co-processor block diagram Altera
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TMS320C6414 TMS320C6415 CORDIC to generate sine wave OFDM DSP Builder TMS320C6414* FFT signal path designer TMS320C64 TMS320C6414/5/6
Abstract: capability for the user to develop his own FPGA code, National does not support such custom FPGA code , the appropriate FPGA code into it, it is possible for the user to download a different FPGA code (the .bit file) into the board. To download another FPGA code into the board, follow these , reference board's operation is only assured for the FPGA code provided by National. Though the board makes it possible for the user to develop and test his own FPGA code, such operation is not supported by National Semiconductor
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ADC08 XC4VLX15 WV4 P6 virtex 5 XC4VLX15-10SF363C led full color screen fpga diode 30v ac dataset 3000RB CSP-9-111C2 CSP-9-111S2
Abstract: capability for the user to develop his own FPGA code, National does not support such custom FPGA code , software. The FPGA logic usage is low, allowing for further code to be written and tested for product , FPGA code into it, it is possible for the user to download a different FPGA code (the .bit file) into the board. To download another FPGA code into the board, follow these instructions: 1. Place the , reference board's operation is only assured for the FPGA code provided by National. Though the board makes Texas Instruments
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Abstract: to develop his own FPGA code, National does not support such custom FPGA code development. 3.2 , to automatically recognize the development board and download the appropriate FPGA code into it, it is possible for the user to download a different FPGA code (the .bit file) into the board. To download another FPGA code into the board, follow the subsequent instructions: 1. Place the desired .bit , 's operation is only assured for the FPGA code provided by National. Though the board makes it possible for National Semiconductor
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Teledyne ssp ADC08D1520 verilog TDI cmos image sensor teledyne adc verilog verilog code for lvds driver 500/10X0/15X0DEV
Abstract: to develop his own FPGA code, National does not support such custom FPGA code development. 3.2 , the appropriate FPGA code into it, it is possible for the user to download a different FPGA code (the .bit file) into the board. To download another FPGA code into the board, follow the subsequent , development board's operation is only assured for the FPGA code provided by National. Though the board makes it possible for the user to develop and test his own FPGA code, such operation is not supported by Texas Instruments
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Abstract: program to configure the FPGA. If using parts that are branded "XCPZ" with a date code other than 1126 , ustomer r Evalu uation Board B Using the e FPGA based C Capture e Board HS SC-ADC C-EVAL LCZ Figure F 1 , ( 1.1-co ompatible) AD96 642 evaluati ion board HSC-ADC-EVAL LCZ FPGA Based Data Capture Bo oard , HSC-ADCEVALCZ evaluation board to set the FPGA I/O voltage to 2.5V. Connect one 6V, 2A switching power supply , prompts for programming the FPGA. The `DONE' LED should illuminate on the HSC-ADC-EVALCZ board indicating Analog Devices
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EPS060250UH-PHP-SZ fft code fpga board hs EPS060250UHPHP-SZ j506 xcpz D9642 AD9642 AN-905 AN-878 AN-877
Abstract: evaluating Maxim's high-speed analog-to-digital converters (ADCs). A field programmable gate array (FPGA , captured by the FPGA and stored in onboard memory. Data transfer and board control are realized through a , control of the hardware and processing of the captured data. Fast Fourier transform (FFT) analysis , FFT windowing functions. The DCEP operates from a single external 5V/4A power supply, provided with the board. o FPGA Configuration Through PC and USB Port Windows is a registered trademark of Maxim Integrated Products
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QSH-060-01-L-D-A QTH-060-01-L-D-A samtec QTH-060-01-L-D MAXIM BAR code label HQCD-060 AN729 HQCD-060-
Abstract: array (FPGA). The FPGA fabric can be used to offload either the GPP or DSP (or both). Hardware , or DSP, accelerating critical sections of either DSP or GPP code in hardware. Moreover, with general purpose routing resources available in the FPGA, hardware acceleration units can run in parallel to , acceleration units running on the FPGA. The creation and use of hardware acceleration units and their , field programmable gate array (FPGA). However, the FPGA fabric can be used to offload the GPP or DSP Altera
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baseband processor simulink sdr on fpga JTRS
Abstract: firmware code onto the FPGA. Flexibility As noted earlier, hardware flexibility/re-programmability in the , code for the FPGA is automatically created at the push of a button. Moreover, based on the throughput , and intellectual property (IP) is proposed. Keywords: WiMAX, FPGA, OFDM, 802.16d, 802.16e, Altera , implemented by performing fast fourier transform (FFT) and inverse FFT on the data signal. Although not , coding/decoding, and front end functions such as FFT/IFFT, beam forming, MIMO, CFR and DPD are very Altera
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abstract for mobile bug LMS adaptive filter simulink model simulink model adaptive beamforming mimo model simulink matlab code for mimo ofdm stc OFDM MRC Matlab code
Abstract: USB interface to the Wavevision 4 software. The FPGA logic usage is low allowing further code to be , with Xilinx Virtex 4 (XC4VLX15) FPGA © Copyright 2006 National Semiconductor Corporation 1 , 7.2 Schematic Drawing ADC081500DEV ­ ADC connected to Virtex4 FPGA . 8 7.3 , . 24 The FFT Plot . 24 FFT Options National Semiconductor
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ADC081500EVAL lvds 4K panel ADC081500 led screen LVDS connector 40 pins wv4 p0 wv4 diode
Abstract: . DS686DB3 CDB4270 5.2 FPGA CODE REVISION ID - ADDRESS 00H 7 REV.7 5.2.1 6 REV.6 5 REV , ) Function: Identifies FPGA code revision number. REV.7 - REV.4 indicate revision whole number, and REV , CS8416 S/PDIF Input Evaluation Board Hardware Setup Clocks /Data FPGA ANALOG OUTPUT , . 5 1.3 FPGA , . 8 2. FPGA OVERVIEW Cirrus Logic
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CS4270 CS8406 HW 2596 SW 2596 10CDB CS8416 evaluation
Abstract: Figure 4: Block diagram of the Radix-2 DIT butterfly used in the FPGA FFT processor. 18-bit fractional , FPGA virtual processor is used for each processing stage of the FPT and FFT. The input , transform method for computing 2-D DFTs. An FPGA architecture is described that is capable of processing , specialized knowledge required to efficiently code the algorithm in comparison to something like the , digital signal processing design engineers. The FPGA maintains the advantages of the high specificity of Xilinx
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TMS320C30 16 point DFT butterfly graph radix-2 DIT FFT C code radix-2 modified booth circuit diagram 4 bit modified booth multipliers radix-2 fft xilinx
Abstract: programming with the FPGA, and implement an internal parallel FFT hardware structure that reduces the FFT , generator. Therefore, this FFT structure is more suitable for processing in an FPGA. The disadvantage of , Fourier transform (FFT) algorithm-based frequency spectrum analysis. The whole system is designed with , collects analog signals, it outputs the signals to the FPGA for processing. The corresponding output is , Nios II processor into the FPGA. Our solution implements a system-on-chip (SOC) solution, which Altera
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verilog code for twiddle factor ROM vhdl code for speech recognition verilog code for speech recognition VHDL audio codec ON DE2 lms algorithm using verilog code lms algorithm using vhdl code EP2C35F672C6
Abstract: function in the FPGA measures the frequency of the incoming ADC clock. This value is used during the FFT , . 19 9.2 The FFT Plot . 19 9.3 FFT Options , . U1 U3-6 U19 FPGA DDR SRAM (200MHz) USB microcontroller LED1 LED6 LED2-5, LED7 LED8 , signals are connected directly to the FPGA Device (U1) on the WaveVision5 Data Capture Board. During data National Semiconductor
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mictor evaluation board layout mictor connector board data dataset DDR right angle 240 connector hmzd connector wv4 marking code
Abstract: or the various serial interfaces as previously described. The LVDS ADC interface code in the FPGA , accessing the FPGA by way of the USB connection. For longer FFT record lengths and lower UART baud rates , . 16 User Interface Single FFT format , evaluation module (EVM) for the ADC. Firmware for an FPGA on the TSW1200EVM has an interface to various LVDS , controls the TSW1200 hardware and displays the FFT and important statistics related to the performance of Texas Instruments
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SLAU212A
Abstract: `out-of-thebox' without having to develop FPGA code. This image can be loaded from the FLASH file system and , w RADAR Features w 2 Channel 1.5GSPS, 8-bit ADC w Xilinx® Virtex®-5 SX95T FPGA (user , performance Xilinx Virtex-5 FPGA to a dual channel high-speed analog input front end providing both , programmable FPGA, data I/O sub-systems and multiple banks of fast memory provides a powerful platform for , Xilinx Virtex-5 SXT FPGA is used to control the analog to digital converter and provides the off-board Curtiss-Wright Controls Embedded Computing
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AD1520 AD1500 1B73EPA HUmiseal 1B31 1B31 VIRTEX-5 DDR2 controller MKT-DS-AD1520-06089
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