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Part | Manufacturer | Description | Samples | Ordering |

DK-LM3S9B96-FPGA | Texas Instruments | Stellaris FPGA Expansion Board | |||

PMP5712.3 | Texas Instruments | FPGA/ DDR2 Supply | |||

PMP5712.1 | Texas Instruments | FPGA/ DDR2 Supply |

Catalog Datasheet Results | Type | Document Tags |

Abstract: program to configure the FPGA. If using parts that are branded "XCPZ" with a date code other than 1126 , ustomer r Evalu uation Board B Using the e FPGA based C Capture e Board HS SC-ADC C-EVAL LCZ Figure F 1 , ( 1.1-co ompatible) AD96 642 evaluati ion board HSC-ADC-EVAL LCZ FPGA Based Data Capture Bo oard Documen , HSC-ADCEVALCZ evaluation board to set the FPGA I/O voltage to 2.5V. Connect one 6V, 2A switching power supply , prompts for programming the FPGA. The `DONE' LED should illuminate on the HSC-ADC-EVALCZ board indicating ... | Original |
4 pages, |
xcpz fft fpga code board hs fft code fpga D9642 AD9642 AN-905 AN-878 AN-877 D9642 abstract |

Abstract: FFT FPGA Co-Processor Functional Description Figure 5 shows the TI Code Composer Studio software , easily interfaces to a digital signal processor. Designers can adapt the FFT FPGA co-processor reference , Figure 1 shows the FFT FPGA co-processor reference design block diagram. Figure 1. FFT FPGA , Board Altera Corporation FFT FPGA Co-Processor Functional Description The direct memory access , Preliminary Altera Corporation FFT FPGA Co-Processor Functional Description Atlantic Interface The ... | Original |
25 pages, |
emif vhdl fpga Altera fft megacore verilog code for sine wave using FPGA TI6416 matlab code for radix-4 fft vhdl source code for fft matlab code for FFT 32 point verilog for 8 point fft TMS320C6416 DSK verilog for 16 point fft cyclone ii fft verilog code for FFT TMS320C6000 TMS320C6416 TMS320C6000 abstract |

Abstract: design targeting efficient use of Stratix® II and Stratix III FPGA resources Turbo encoder/decoder , 1 y De-puncture · Supports all 188 code blocks defined in LTE standard from 40 to 6,144 , Stratix III FPGA resources N Decoder 2 De-interleaver Altera supplies the reference design as , Fourier transform (FFT)/inverse FFT (IFFT) reference design Altera supplies the reference design as , FFT L,N Reference I/O Processor CP Insertion 1536 FFT/IFFT Input Re-sequencer ... | Original |
2 pages, |
vhdl code for lte channel coding 3gpp lte OFDMA Matlab code verilog for 8 point fft Radix-3 FFT vhdl code for FFT radix vhdl code for FFT 8 point vhdl code for lte turbo decoder vhdl code lte vhdl code for FFT matlab code for mimo wireless MIMO Matlab code datasheet abstract |

Abstract: Instruments Code Composer Studio version 2.21 or higher Hardware Requirements To run the FFT FPGA , Functional Description FPGA Co-Processor Functional Description Figure 1 illustrates the FFT FPGA co-processor reference design block diagram. Figure 1. FFT FPGA Co-Processor Block Diagram Texas , Interface FFT MegaCore Function Receive FIFO Buffer TI TMS320C6416 TMS320C6416 DSK Stratix II FPGA Stratix , rate at which the co-processor consumes or produces data. In this FFT FPGA co-processor reference ... | Original |
21 pages, |
TMS320C6416 TMS320C6416 DSK tms320c6416 emif vhdl code for FFT 16 point vhdl code for FFT mixed radix 8 point Altera fft megacore verilog code fft verilog code for 64 point fft emif vhdl fpga TMS320C6416 DSK usb EMIF sdram full example code vhdl source code for fft TMS320C6000 TMS320C6416 TMS320C6000 abstract |

Abstract: FPGA Co-Processor Functional Description Figure 1 illustrates the FFT FPGA co-processor reference design block diagram. Figure 1. FFT FPGA Co-Processor Block Diagram Texas Instruments TMS320C6416 TMS320C6416 , consumes or produces data. In this FFT FPGA co-processor reference design, the co-processor is connected , FPGA co-processor reference design signals. Table 4. FFT FPGA Co-Processor Reference Design Signal , Table 4. FFT FPGA Co-Processor Reference Design Signal Descriptions Signal Name Width Direction ... | Original |
21 pages, |
EP2S180 DSK6416 AN-395 523C Atlantic Interface fft code fpga 16 point FFT radix-4 VHDL documentation fpga stratix II ep2s180 verilog code for FFT 16 point vhdl source code for fft verilog code for FFT TMS320C6416 DSK usb asynchronous fifo vhdl TMS320C6000 TMS320C6416 TMS320C6000 abstract |

Abstract: Implementing FFT in an FPGA Co-Processor Sheac Yee Lim Andrew Crosland Altera Corporation , to improve overall system performance. For example, an FFT FPGA co-processor implementation that , about a 9.06 s transform time [3]. 3. IMPLEMENTING AN FFT ALGORITHM AS AN FPGA CO-PROCESSOR The , the purposes of this paper, we have selected an FFT algorithm for implementation as an FPGA , , where nx is the length of the FFT in complex samples. Figure 1. FFT FPGA Co-processor block diagram ... | Original |
6 pages, |
1S25 Atlantic Interface FFT 1024 point fft fpga code TMS320C6000 TMS320C6414 TMS320C6414* FFT TMS320C6415 TMS320C6416 C6416 CORDIC to generate sine wave OFDM DSP Builder tms320c6416 emif datasheet abstract |

Abstract: Figure 4: Block diagram of the Radix-2 DIT butterfly used in the FPGA FFT processor. 18-bit fractional , FPGA virtual processor is used for each processing stage of the FPT and FFT. The input , transform method for computing 2-D DFTs. An FPGA architecture is described that is capable of processing , specialized knowledge required to efficiently code the algorithm in comparison to something like the , digital signal processing design engineers. The FPGA maintains the advantages of the high specificity of ... | Original |
6 pages, |
TMS320C30 booth multiplier DECIMATION IN FREQUENCY DSP design pipelined fft processor Modified Booth Multipliers 4 bit Booth Multiplier 16 point DIF FFT using radix 4 fft 16 point Fast Fourier Transform radix-2 BUTTERFLY DSP FPGA DIF FFT using radix 4 fft radix-2 fft xilinx 4 bit modified booth multipliers datasheet abstract |

Abstract: supported by TI's Code Composer Studio tool. The EMIF base address of the FPGA in chip select two memory , to reduce dynamic power consumption in the FPGA. The FFT co-processor in this reference design is a , output of Code Composer Studio with a complex FFT applied to the input data. Figure 11. Code Composer , supported by Code Composer Studio. f For information on how to load a new FPGA image, see section 4.8 , FPGA Peripheral Expansion & FPGA Co-Processing with a TI TMS320C6000 TMS320C6000 Application Note 352 ... | Original |
26 pages, |
TMS320C6000 verilog code for 64 point fft vhdl code for radix-4 fft vhdl code for FFT 32 point verilog code for sine wave using FPGA vhdl code to generate sine wave VHDL code of DCT by MAC l2 cache verilog code verilog code for FFT 32 point fpga based stepper motor controller verilog code for FFT TMS320C6000 abstract |

Abstract: Software - FPGA Synthesis Architectural Synthesis from Behavioral Code to Implementation in a Xilinx FPGA The Frontier Design A|RT Designer product efficiently maps a software design into a hardware description language implementation suitable for FPGA synthesis. by Doug Johnson, Business , written in C code) onto an optimized hardware architecture (FPGA). A|RT Designer is ideal for creating a , the C code and transforms it into synthesizable VHDL and Verilog HDL that is suitable for driving FPGA ... | Original |
3 pages, |
fft butterfly verilog code fgpa verilog code for FFT 2 point fft butterfly verilog code vhdl source code for fft ALU Verilog processor ALU vhdl code, not verilog verilog code for implementation of rom verilog code for ALU implementation datasheet abstract |

Abstract: (OFDMA) and multicarrier Code Division Multiple Access (MC-CDMA), are considered key to achieving target , fast Fourier transform (FFT/IFFT), beamforming, MIMO, crest factor reduction (CFR), and digital , MCU controls the system, while the FPGA and digital signal processor handle the data-flow processing. , typical digital signal processor/FPGA partitioning for baseband physical layer (PHY) functions in an OFDMA-based system such as WiMAX or LTE. Figure 1. DSP/FPGA Partitioning for OFDMA Systems Downlink ... | Original |
6 pages, |
WiMAX baseband lte if filter HARQ MIMO HARQ *MIMO OFDM OFDM DSP Builder OFDM FPGA CPRI Multi Rate channel equalization MIMO ifft transmit LTE baseband array antenna Mimo Channel Estimation for FPGA IS-95 IS-95 abstract |

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No abstract text available www.datasheetarchive.com/download/72614211-94705ZC/acfftds.zip (Acfftds.pdf) |
EM Microelectronics | 17/09/2002 | 414.27 Kb | ZIP | acfftds.zip |

description of Xilinx FPGA technology. The Fastest FFT in the West This paper discusses that the incorporation of a large FFT in a single FPGA, while noteworthy, may evoke a "so what" response. Its speed will time of a 256 point FFT. The speed in the FPGA design is set by the computation time of the radix 2 > Other FPGA Applications List Summaries XAPP Application for Model Technology - ModelSim 110 KB Summary 7/98 FPGA www.datasheetarchive.com/files/xilinx/docs/wcd00008/wcd0086a-v2.htm |
Xilinx | 04/06/1999 | 24.79 Kb | HTM | wcd0086a-v2.htm |

description of Xilinx FPGA technology. The Fastest FFT in the West This paper discusses that the incorporation of a large FFT in a single FPGA, while noteworthy, may evoke a "so what" response. Its speed will time of a 256 point FFT. The speed in the FPGA design is set by the computation time of the radix 2 > Other FPGA Applications List Summaries XAPP Application for Model Technology - ModelSim 110 KB Summary 7/98 FPGA www.datasheetarchive.com/files/xilinx/docs/wcd00002/wcd00208-v1.htm |
Xilinx | 16/02/1999 | 24.84 Kb | HTM | wcd00208-v1.htm |

ASICs and very large FPGA designs. We use an HDL approach to design and have extensive experience to prototype in FPGA and easily retarget to ASIC. Our broad knowledge of FPGAs allows to write HDL models that will leverage the best performance from a given FPGA architecture. Additionally we Data cipher FFT RAM controllers Microprocessor Interfacing Contact : Postal Code: Phone: Fax: E-mail www.datasheetarchive.com/files/xilinx/docs/rp00024/rp02446.htm |
Xilinx | 06/03/2000 | 8.12 Kb | HTM | rp02446.htm |

technology is followed by a description of Xilinx FPGA technology. The Fastest FFT in the West This paper discusses that the incorporation of a large FFT in a single FPGA, while noteworthy, may , established in 1995, is the execution time of a 256-point FFT. The speed in the FPGA design is set by the Summary 7/98 FPGA Xilinx/Synplicity High Density Methodology 140 KB Summary 7/98 FPGA 16-Tap, 8-Bit FIR www.datasheetarchive.com/files/xilinx/docs/wcd00001/wcd00196.htm |
Xilinx | 17/07/1998 | 23.27 Kb | HTM | wcd00196.htm |

description of Xilinx FPGA technology. The Fastest FFT in the West (70 kb) This paper discusses that the incorporation of a large FFT in a single FPGA, while noteworthy, may evoke a "so what" , is the execution time of a 256-point FFT. The speed in the FPGA design is set by the computation Other FPGA Applications List XC3164A-2 XC3164A-2 XC3164A-2 XC3164A-2 FPGA 171 kb Summary 1/95 XC3000 XC3000 XC3000 XC3000 VIEW logic Verilog www.datasheetarchive.com/files/xilinx/weblinx/apps/fpga.htm |
Xilinx | 05/02/1997 | 18.2 Kb | HTM | fpga.htm |

DSP Design DFT IP Cores FPGA : standard compliant verified by FPGA realiable and robust VHDL synthesisable code test environment constrains files 6k-8k without code memory now 8k-10k without code memory - www.datasheetarchive.com/files/em-microelectronics/asicentrum/en_01_01_01_03.html |
EM Microelectronics | 17/09/2002 | 57.8 Kb | HTML | en_01_01_01_03.html |

> Other FPGA Applications List Summaries XAPP Application Notes Xilinx FPGAs 60 KB Summary 9/98 XC4000 XC4000 XC4000 XC4000 FPGA Interpolators Using Polynomial Filters 80 KB Summary 9/98 XC4000 XC4000 XC4000 XC4000 High-Performance FPGA Filters Processing 140 KB Summary 4/99 FPGA FPGA Implementation of Adaptive Temporal Kalman Filter for Real Time Video Filtering 60 KB Summary 3/99 FPGA www.datasheetarchive.com/files/xilinx/docs/rp00003/rp0031b.htm |
Xilinx | 06/03/2000 | 36.71 Kb | HTM | rp0031b.htm |

design house specializing in cost-effective FPGA solutions. The company is located in Egmating DAB, DVBT, MPEG, FFT, FIR/HDF-Filters Measurement systems m C/ m P interfaces I 2 million gate FPGA designs. Contact Partner Array Electronics Klaus Schwan : State: Country: Postal Code: Phone www.datasheetarchive.com/files/xilinx/docs/wcd0000e/wcd00e1b-v2.htm |
Xilinx | 04/06/1999 | 7.58 Kb | HTM | wcd00e1b-v2.htm |

design house specializing in cost-effective FPGA solutions. The company is located in Egmating DAB, DVBT, MPEG, FFT, FIR/HDF-Filters Measurement systems m C/ m P interfaces I 2 million gate FPGA designs. Contact Partner Array Electronics Klaus Schwan : State: Country: Postal Code: Phone www.datasheetarchive.com/files/xilinx/docs/rp00027/rp02707.htm |
Xilinx | 29/02/2000 | 7.52 Kb | HTM | rp02707.htm |