RF/128 T5557 T555701-DDW T555702-DDW T5554 RF/16 RF/32 RF/40 RF/50 RF/64 RF/100 - Datasheet Archive

 

· · · · · · · · Contactless power supply Contactless read/write data

 

Features · · · · · · · · Contactless power supply Contactless read/write data transmission Radio frequency fRF from 100 to 150 kHz e5550 binary compatible or extended mode 75 pF on-chip resonant capacitor (mask option) 7 x 32-bit EEPROM data memory including 32-bit password memory Separate 64-bit memory for traceability data 32 bit configuration register in EEPROM to setup: Data rate: - RF/2 to RF/128 RF/128, binary selectable or - fixed e5550 data rates Modulation / Coding - FSK, PSK, Manchester, Biphase, NRZ Other options: - Password mode - Max block feature - Answer-On-Request (AOR) mode - Inverse data output - Direct access mode - Sequence terminator(s) - Write protection (through lock-bit per block) - Fast write method (X5 kbps vs. X2 kbps) - OTP functionality - POR delay up to 67 ms Multifunctional 330-bit Read/Write RFIdentification IC T5557 T5557 Description The T5557 T5557 is a contactless R/W-IDentification IC (IDIC) for applications in the 125kHz frequency range. A single coil, connected to the chip, serves as the IC's power supply and bidirectional communication interface. Antenna and chip together form a transponder or tag. The on-chip 330-bit EEPROM (10 blocks 33 bits each) can be read and written blockwise from a base station. Block 0 is reserved for setting the operation modes of the T5557 T5557 tag. Block 7 may contain a password to prevent unauthorized writing. Data is transmitted from the IDIC (uplink) using load (backscatter) modulation. This is achieved by damping the RF field with a resistive load between the two terminals Coil 1/ Coil 2. The IC receives and decodes 100% amplitude modulated (OOK) pulsewidth encoded bit streams from the base station. System Block Diagram Figure 1. RFID system using T5557 T5557 tag Base station Data * Controller Power Coil interface Transponder Memory T5557 T5557 * Mask option Rev. A7, 11-Dec-01 1 (24) Ordering Information Extended Type Number T555701-DDW T555701-DDW Dice on wafer 300 µm thickness T555702-DDW T555702-DDW T5557 T5557 Building Blocks Package Remarks Dice on wafer 300 µm thickness, 75 pF (± 3%) Figure 2. Block diagram POR Modulator Coil 1 Coil 2 Write decoder Memory (330 bit EEPROM) Controller Data-rate generator * Analog front end Mode register Input register Test logic HV generator * Mask option Analog Front End (AFE) The AFE includes all circuits which are directly connected to the coil. It generates the IC's power supply and handles the bidirectional data communication with the reader unit. It consists of the following blocks: · Rectifier to generate a DC supply voltage from the AC coil voltage · Clock extractor · Switchable load between Coil 1 / Coil 2 for data transmission from tag to the base station or reader (uplink) · Field gap detector for data transmission from the base station to the tag (downlink mode) · ESD protection circuitry Data-Rate Generator 2 (24) The data rate is binary programmable to operate at any data rate between rf/2 and rf/128 or equal to any of the fixed e5550/e5551 and T5554 T5554 bitrates (RF/8, RF/16 RF/16, RF/32 RF/32, RF/40 RF/40, RF/50 RF/50, RF/64 RF/64, RF/100 RF/100 and RF/128 RF/128). T5557 T5557 Rev. A7, 11-Dec-01 T5557 T5557 Write Decoder This function decodes the write gaps and verifies the validity of the data stream according to the Atmel e555x write method. Charge Pump This on-chip circuit generates the high voltage required for programming of the EEPROM. DC Supply Power is externally supplied to the IDIC via the two coil connections. The IC rectifies and regulates this RF source and uses it to generate its supply voltage. Power-On Reset (POR) This circuit delays the IDIC functionality until an acceptable voltage threshold has been reached. Clock Extraction The clock extraction circuit uses the external RF signal as its internal clock source. Control-Logic Module The control logic has the following functions: · Load-mode register with mode data from EEPROM block 0 after power-on and also during reading · Control memory access (read, write) · Handle write data transmission and write error modes · The first two bits of the downlink data stream are the opcode, e.g. standard write, direct access or reset. · In password mode, the 32 bits received after the opcode are compared with the password stored in block 7. Mode (Configuration) Register This register stores the mode data from the EEPROM configuration block. It is continually refreshed at the start of every block read. 3 (24) Rev. A7, 11-Dec-01 Figure 3. Block 0 configuration mapping - e5550 compatible mode 5 6 7 8 0 0 0 0 0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 0 0 0 0 Lock Bit Master Key 0 Data Note 1), 2) PSK- Modulation CF Rate 0 0 0 0 1 0 1 RF/4 0 1 0 1 0 RF/8 0 1 1 1 1 RFU RF/50 RF/50 1 0 0 0 0 0 0 0 Direct 1 0 1 0 0 0 0 1 PSK1 RF/100 RF/100 1 1 0 0 0 0 1 0 1 0 0 1 1 PSK3 0 0 1 0 0 FSK1 0 0 1 0 1 FSK2 0 0 1 1 0 FSK1a 0 0 1 1 1 FSK2a 0 1 0 0 0 Manchester 1 0 0 0 0 Biphase ('50) 1 1 0 0 0 0 PSK2 0 BLOCK RF/2 RF/40 RF/40 Locked 0 RF/64 RF/64 1 0 RF/32 RF/32 Unlocked 0 RF/16 RF/16 0 RF/8 0 MAX- POR delay 3 4 1 PWD 2 1 ST-Sequence Terminator 1 0 AOR L Reserved RF/128 RF/128 1 1 1) If Master Key = 6 then test mode write commands are ignored 2) If Master Key 6 or 9 then extended function mode is disabled Modulator The modulator consists of data encoders for the following basic types of modulation: Table 1. Types of e5550-compatible modulation modes Mode Direct Data Output FSK 1a 1) FSK 2a 1) `0' = f1 = rf/8; `1'= f2 = rf/5 `0' = f1 = rf/8; `1'= f2 = rf/10 FSK 1 1) `0' = f1 = rf/5; `1'= f2 = rf/8 FSK 2 1) `0' = f1 = rf/10; `1'= f2 = rf/8 PSK1 2) Phase change when input changes PSK2 2) Phase change on bit clock if input high PSK3 2) Phase change on rising edge of input Manchester `0' = falling edge, `1'= rising edge Biphase `1' creates an additional mid­bit change NRZ `1'= damping on, `0'= damping off Notes: 4 (24) 1) A common multiple of bitrate and FSK frequencies is recommended. 2) In PSK mode the selected data rate has to be an integer multiple of the PSK sub-carrier frequency. T5557 T5557 Rev. A7, 11-Dec-01 T5557 T5557 Memory The memory is a 330-bit EEPROM, which is arranged in 10 blocks of 33 bits each. All 33 bits of a block - including the lock bit - are programmed simultaneously. Block 0 of page 0 contains the mode/configuration data, which is not transmitted during normal read operation. Block 7 of page 0 may be used as a write protection password. Bit 0 of every block is the lock bit for that block. Once locked, the block (including the lock bit itself) is not re-programmable through the RF field again. Blocks 1 and 2 of page 1 are accessed with the parameters defined in the configuration register, if the opcode '11' is used. Figure 4. Memory map Page 1 0 1 32 Traceability data Block 2 1 Traceability data Block 1 L User data or password Block 7 L User data Block 6 L User data Block 5 L User data Block 4 L User data Block 3 L User data Block 2 L User data Block 1 L Page 0 1 Configuration data Block 0 Not transmitted 32 bits Traceability Data Structure Blocks 1 and 2 of page 1 contain the traceability data and are programmed by Atmel during production test. The most significant byte of block 1 is fixed to the allocation class (ACL) as defined in ISO/IEC 15963-1. The second byte is reserved to the manufacturer's ID. The following 8 bits are used as IC reference byte (ICR - bits 47 to 40). The lower 40 bits of the data encode the traceability information of Atmel and conform to an unique numbering system. These 40 data bits are divided in two sub-groups, a 5-digit lot ID number, the wafer number (5 bit) concatenated with the sequential die number per wafer. 5 (24) Rev. A7, 11-Dec-01 Figure 5. T5557 T5557 traceability data structure Traceability 12 31 Block 2 20 20 . 19 LotID Block 1 . 15 23 . ICR 16 2 . 1 0 die on wafer # MFC 24 14 wafer # ACL 31 . 15 . MSN LotID 8 7 . 0 8 ACL MFC ICR MSN LotID DPW Allocation class as defined in ISO/IEC 15963-1 = E0h Manufacturer code of Atmel Corporation as defined in ISO/IEC 7816-6 = 15h C reference of tag or silicon manufacturer. Default: Atmel = 00h, customer specific setting on request Manufacturer serial number consists of 5 digit lot number, e.g.'38765' 20 bit encoded as sequential die per wafer number (with top 5 bit = wafer#) Operating the T5557 T5557 Initialization and POR Delay Power-On-Reset circuit (POR) remains active until an adequate voltage threshold has been reached. This in turn triggers the default start-up delay sequence. During this configuration period of about 192 field clocks the T5557 T5557 is initialized with the configuration data stored in EEPROM block 0. During initialization of the configuration block, modulation is switched on. If the POR-delay bit is reset, no additional delay is observed after the configuration period. Tag modulation in regular-read mode will be observed about 3 ms after entering the RF field. If the POR-delay bit is set the T5557 T5557 remains quiet in a permanent damping state until 8190 internal field clocks have elapsed. TINIT = (192 + 8190 delay)fc (67 ms @ 125 kHz) Any field gap occurring during this initialization phase will restart the complete sequence. After this initialization time the T5557 T5557 enters regular-read mode and modulation starts automatically using the parameters defined in the configuration register. Uplink Mode Under normal operation, the data stored within the EEPROM is cycled and the Coil 1, Coil 2 terminals are load modulated. This resistive load modulation can be detected at the reader module. Data Encoding Everytime the T5557 T5557 enters regular- or block-read mode, the first bit transmitted is a logical '0'. The data stream starts with block 1, bit 1, continues through MAXBLK, bit 32, and cycles continuously if in regular-read mode . Note: 6 (24) This behaviour is different from the original e555x and helps in decoding of PSK modulated data. T5557 T5557 Rev. A7, 11-Dec-01 T5557 T5557 Direct Access Command With the direct access command only the addressed block is repetitively read, this mode is called block-read mode. Direct access is entered by transmitting the access opcode (`10'), a single `0' bit and the requested 3 bit block address, if the tag is in plain/ normal mode. In password mode (PWD bit set), the direct access to a single block needs the valid 32bit password to be transmitted after the access opcode ('10') whereas a '0' bit and the 3-bit block address follow afterwards. In case the transmitted password does not match with the contents of block 7, the T5557 T5557 tag returns to the regular-read mode immediately. MaxBlock = No of Readable Blocks Data from the memory is serially transmitted, starting with block 1, bit 1, up to the last block (e.g. 7), bit 32. The last block which will be read is defined by the mode parameter field MAXBLK in EEPROM block 0. When the MAXBLK address has been read, data transmission restarts with block 1, bit 1. The user may limit the cyclic datastream in regular-read mode by setting the MAXBLK between 0 and 7 (representing each of the 8 data blocks). If set to 7, blocks 1 through 7 can be read. If set to 1, only block 1 is transmitted continously. If set to 0, the contents of the configuration block (normally not transmitted) can be read. In the case of MAXBLK = 0 or 1 regular-read mode is not distinguishable from block-read mode. Figure 6. Example of MAXBLK features MAXBLK = 5 0 Block 1 Block 4 Block 5 Block 1 Block 2 Block 2 Block 1 Block 2 Block 1 Block 0 Block 0 Block 0 Block 0 Loading block 0 MAXBLK = 2 0 Block 1 Loading block 0 MAXBLK = 0 e5550 Sequence Terminator Block 0 0 Loading block 0 The sequence terminator ST is a special damping pattern which follows the last block and may be used to synchronize the reader. This e5550-compatible sequence terminator consists of 4 bit periods with underlaying data values of '1'. During the second and fourth bit period modulation is switched off (Manchester encoding - switched on). Biphase modulated data blocks need fixed leading and trailing bits in combination with the sequence terminator to be identified reliabely. The sequence terminator may be individually enabled by setting of mode bit 29 (ST = '1') in the e5550-compatibility mode (X-mode = '0'). In the regular-read mode the sequence terminator is inserted at the start of each MAXBLK-limited read data stream. In block-read mode - after any block-write or direct-access command - or if MAXBLK was set to '0' or '1', the sequence terminator is inserted before the transmission of the selected block. 7 (24) Rev. A7, 11-Dec-01 Figure 7. Read data stream with sequence terminator No terminator Block 1 Block 2 MAXBLK Regular-read mode Sequence terminator Block 2 Sequence terminator Block 1 ST = on Block 1 Block 2 MAXBLK Block 1 Block 2 Figure 8. e5550-compatible sequence terminator waveforms Bit period Sequence Data '1' Data '1' Data '1' Data '1' Last bit First Bit Modulation off (on) Modulation off (on) Waveforms per different modulation type V Coil bit '1' or '0' PP Manchester FSK Sequence terminator not suitable for Biphase or PSK modulation Downlink Mode Data is written to the tag by interrupting the RF field with short field gaps (on-off keying) in accordance with the e5550 write method. The time between two gaps encodes the '0/1' information to be transmitted. The duration of the gaps is usually 50 to 150 ms. The time between two gaps is nominally 24 field clocks for a "0" and 54 field clocks for a "1". When there is no gap for more than 64 field clocks after a previous gap, the T5557 T5557 exits the downlink mode; it starts with command execution if the correct number of bits were received. If there is a gap failure - the T5557 T5557 does not continue, instead it will enter regular-read mode. Start Gap The initial gap is referred to as the start gap. This triggers the downlink mode. During the downlink mode, the receive damping is permanently enabled to ease gap detection. The start gap may need to be longer than subsequent gaps in order to be detected reliably. A start gap will be accepted at any time after the mode register has been loaded ( 3 ms). A single gap will not change the previously selected page (by former opcode '10' or '11'). Figure 9. Start of writing Read mode Write mode d1 S gap 8 (24) d0 W gap T5557 T5557 Rev. A7, 11-Dec-01 T5557 T5557 Writing Data The T5557 T5557 always expects to receive a dual bit as the first two bits of a reader command sequence. There are three valid opcodes: - The opcodes "10" and "11" precede all block write and direct access operations for page 0 and page 1. - The RESET opcode "00" initiates a POR cycle. - The opcode "01" precedes all test mode write operations. Any test mode access is ignored after master key (bits 1.4) in block 0 has been set to "6". Any further modifications of the master key may be prohibited by setting the lock bit of block 0 or the OTP bit. Writing has to follow these rules: - Standard writing needs the opcode, the lock bit, the 32 data bits and the 3 bit address (38 bits total). - Protected write (PWD bit set) requires a valid 32-bit password between opcode and data, address bits. - For the AOR wake-up command an opcode and a valid password are necessary to activate a specific tag. Note:The data bits are read in the same order as written. If the transmitted command sequence is invalid, the T5557 T5557 enters regular-read mode with the previously selected page (by former opcode '10' or '11'). Table 2. Write data decoding schemes Parameters Remark Symbol Min. Max. Unit Sgap 10 50 FC Normal write mode Wgap 8 50 FC '0' data d0 16 31 FC '1' data d1 48 63 FC Start gap Write gap Write data in normal mode Figure 10. Complete writing sequence Read mode Op-code Block 0 loading Start gap Read mode Write mode Block data Block address Programming Lock bit POR 9 (24) Rev. A7, 11-Dec-01 Figure 11. T5557 T5557 command formats OP Standard write L Protected write 1p 1 Password 32 AOR (wake-up command) 10 1 Password 32 Direct access (PWD = 1) 10 1 Password 32 Direct access (PWD = 0) 1p 0 Page 0/1 regular read 1p Reset command Password 1p 1 Data 00 2 Addr 32 2 Addr L 1 0 2 Addr 0 Data 32 2 Addr 0 0 0 * p = page selector When password mode is active (PWD = 1), the first 32 bits after the opcode are regarded as the password. They are compared bit-by-bit with the contents of block 7, starting at bit 1. If the comparison fails, the T5557 T5557 will not program the memory, instead it will restart in regular-read mode once the command transmission is finished. Note: In password mode, MAXBLK should be set to a value below 7 to prevent the password from being transmitted by the T5557 T5557. Every transmission of the direct-access command (two opcode bits, 32 bits password, '0' bit plus 3 address bits = 38 bits) needs about 18 ms. Testing all possible combinations (about 4.3 billion) takes about two years. Answer-On-Request (AOR) Mode When the AOR bit is set, the T5557 T5557 does not start modulation in the regular-read mode after loading configuration block 0. The tag waits for a valid AOR data stream ("wake-up command") from the basestation before modulation is enabled. The wake-up command consists of the opcode ('10`) followed by a valid password. This selected tag will remain active until the RF field is turned off or a new command with a different password is transmitted. Table 3. T5557 T5557 - Modes of operation PWD AOR Behavior of Tag after Reset Command or POR De-activate Function 1 1 Answer-on-request (AOR) mode: · Modulation starts after wake-up with a matching PWD · Programming needs valid PWD Command with non-matching password deactivates the selected tag 1 0 Password mode: · Modulation in regular-read mode starts after reset · Programming and direct access needs valid PWD 0 - Plain/Normal mode: · Modulation in regular-read mode starts after reset · Programming and direct access without password 10 (24) T5557 T5557 Rev. A7, 11-Dec-01 T5557 T5557 Figure 12. Answer-on-request (AOR) mode Modulation V Coil 1- Coil 2 POR Loading block 0 No modulation because AOR = 1 AOR wake-up command (with valid PWD) Figure 13. Coil voltage after programming of a memory block V Coil 1- Coil 2 5.6 ms Write data to tag Programming and data verification Read programmed memory block (Block-read mode) POR/ or single gap Read block 1.MAXBLK (Regular-read mode) 11 (24) Rev. A7, 11-Dec-01 Figure 14. Anticollision procedure using AOR mode BASE station TAG init tags with AOR = '1' , PWD = '1' Field OFF => ON wait for t w POWER ON RESET read configuration > 2.5ms enter AOR mode wait for OPCODE + PWD => "wake-up command" "Select a single tag" send OPCODE + PWD => "wake-up command" Receive damping ON NO PWD correct ? YES decode data send block 1.MAXBLK NO all tags read ? YES EXIT 12 (24) T5557 T5557 Rev. A7, 11-Dec-01 T5557 T5557 Programming When all necessary information has been received by the T5557 T5557, programming may proceed. There is a clock delay between the end of the writing sequence and the start of programming. Typical programming time is 5.6 ms. This cycle includes a data verification read to grant secure and correct programming. After programming was executed successfully, the T5557 T5557 enters block-read mode transmitting the block just programmed (see figure 13). Note: This behaviour is different from the e555x-family predecesssors. Error Handling Several error conditions can be detected to ensure that only valid bits are programmed into the EEPROM. There are two error types, which lead to two different actions. Errors During Writing The following detectable errors could occur during writing data into the T5557 T5557: · Wrong number of field clocks between two gaps (i.e. not a valid "1" or "0" pulse stream). · Password mode is activated and the password does not match the contents of block 7. · The number of bits received in the command sequence is incorrect. Valid bit counts accepted by the T5557 T5557 are: - Password write 70 bits (PWD = 1) - Normal write 38 bits (PWD = 0) - AOR wake up 34 bits (PWD = 1) - Direct access 38 bits (PWD = 1) - Direct access 6 bits (PWD = 0) - Reset command 2 bits - Page 0/1 regular read 2 bits If any of these erroneous conditions were detected, the T5557 T5557 enters regular-read mode, starting with block 1 of page 0. Errors Before/ During Programming If the command sequence was received successfully, the following error could still prevent programming: · The lock bit of the addressed block is set already. · In case of a locked block, programming mode will not be entered. The T5557 T5557 reverts to uplink mode, continuously transmitting the currently addressed block in block-read mode. If the command sequence is validated and the addressed block is not write protected, the new data will be programmed into the EEPROM memory. The new state of the block write protection bit (lock bit) will be programmed at the same time accordingly. Each programming cycle consists of 4 consecutive steps: erase block, erase verification (data = '0'), programming, write verification (corresponding data bits ='1'). · If a data verification error is detected after an executed data block programming, the tag will stop modulation (modulation defeat) until a new command is transmitted. 13 (24) Rev. A7, 11-Dec-01 Figure 15. T5557 T5557 functional diagram Power -on reset * p = page selector AOR = 1 Setup modes AOR mode AOR = 0 Regular - read mode addr = 1 . maxblk Start Block - read mode gap Gap addr = current command mode gap Direct access OP (1p)* Command decode Modulation defeat single gap or invalid command OP(11.) Page 1 OP (1p)* Page 0 OP(10.) OP(00) Reset OP(01) Write OP(1p)* Test to Page 0 Write fail data = old fail data = old fail data = old ok data = new Number of bits Password check Lock bit check Data verification failed T5557 T5557 in Extended Mode (X-Mode) Program In general, the block 0 setting of the master key (bits 1 to 4) to the value "6" or "9" together with the X-mode bit will enable the extended mode functions. · Master key = "9": Test mode access and extended mode are both enabled. · Master key = "6": Any test mode access will be denied but the extended mode is still enabled. Any other master key setting will prevent the activation of the T5557 T5557 extended mode options, even when the X-mode bit is set. Binary Bit-Rate Generator In extended mode the data rate is binary programmable to operate at any data rate between rf/2 and rf/128 as given in the formula below. Data data rate = RF/(2n+2) 14 (24) T5557 T5557 Rev. A7, 11-Dec-01 T5557 T5557 OTP Functionality If the OTP bit is set to "1" all memory blocks are write protected and behave as if all lock bits are set to 1. If the master key is set to "6" additionally, the T5557 T5557 mode of operation is locked forever (= OTP functionality). If the master key is set to "9", the test-mode access allows the re-configuration of the tag again. Figure 16. Block 0 - configuration map in extended mode (x-mode) 6 7 8 1 0 0 0 0 0 1 0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 n5 n4 n3 n2 n1 n0 Data Rate Modulation PSK- 0 0 0 0 1 1 0 RF/8 Unlocked PSK2 0 0 0 1 0 1 1 Res. 1 Locked PSK3 0 0 0 1 1 FSK1 0 0 1 0 0 FSK2 0 0 1 0 1 Manchester 0 1 0 0 0 Biphase ('50) 1 0 0 0 0 Biphase ('57) 1 1 0 0 MAX- 0 0 0 RF/2 Direct 0 0 0 0 0 0 1 BLOCK RF/4 RF/(2n+2) POR-Delay PSK1 0 CF Inverse Data Note 1), 2) Fast write Lock Bit Master Key 9 10 11 12 13 14 15 16 PWD 5 ST-Sequence start marker 3 4 OTP 2 AOR 1 X-Mode L 1) If Master Key = 6 and bit 15 set, then test mode writes are ignored and extended mode is active 2) If Master Key = 9 and bit 15 set, then extended mode is enabled Table 4. T5557 T5557 types of modulation in extended mode Mode Inverse Data Output Encoding FSK 1 1) 1) Direct Data Output Encoding `0' = f2 = rf/5; `1' = f1 = rf/8 `0' = f1 = rf/8; `1'= f2 = rf/5 `0' = f2 = rf/10; `1' = f1 = rf/8 `0' = f1 = rf/8; `1'= f2 = rf/10 PSK1 2) Phase change when input changes Phase change when input changes PSK2 2) Phase change on bit clock if input low Phase change on bit clock if input high PSK3 2) Phase change on falling edge of input Phase change on rising edge of input Manchester `1' = falling edge, `0'= rising edge on mid­bit `0' = falling edge, `1'= rising edge on mid­bit Biphase 1 ('50) `1' creates an additional mid­bit change `0' creates an additional mid­bit change Biphase 2 ('57) `0' creates an additional mid­bit change `1' creates an additional mid­bit change NRZ `0'= damping on, `1'= damping off `1'= damping on, `0'= damping off FSK 2 Notes: 1) A common multiple of bitrate and FSK frequencies is recommended 2) In PSK mode the selected data rate has to be an integer multiple of the PSK sub-carrier frequency 15 (24) Rev. A7, 11-Dec-01 Table 5. Fast write data decoding schemes Parameters Remark Symbol Min. Max. Unit Sgap 10 50 FC Normal write mode Wngap 8 50 FC Fast write mode Wfgap 8 50 FC Write data in normal mode '0' data d0 16 31 FC '1' data d1 48 63 FC Write data in fast mode '0' data d0 8 15 FC '1' data d1 24 31 FC Start gap Write gap Sequence Start Marker Figure 17. T5557 T5557 sequence start marker in extended mode Sequence Start Marker Block-read mode 10 Block n Regular-read mode 10 Block 1 01 Block n Block 2 10 Block n MAXBLK 01 01 Block 1 Block n Block 2 10 Block n MAXBLK 01 10 The T5557 T5557 sequence start marker is a special damping patterns, which may be used to synchronize the reader. The sequence start marker consists of two bits ('01' or '10') which are inserted as header before the first block to be transmitted. At the start of a new block sequence, the value of the two bits is inverted. Inverse Data The T5557 T5557 supports in its extended mode (X-mode) an inverse data output option. If inverse data is enabled the modulator as shown in figure 18 works inverse (see table 4). This function is supported for all basic types of modulations. Figure 18. Data encoder for inverse data output PSK1 PSK2 PSK3 Intern out data D Sync Data clock CLK XOR R Direct/NRZ Data output Mux FSK1 FSK2 Manchester Biphase Inverse data output Fast Write 16 (24) Modulator In the optional fast write mode the time between two gaps is nominally 12 field clocks for a "0" and 28 field clocks for a "1". When there is no gap for more than 32 field clocks after a previous gap, the T5557 T5557 will exit the downlink mode. Please refer to table 5 and figure 8. T5557 T5557 Rev. A7, 11-Dec-01 Rev. A7, 11-Dec-01 RF-field Inverted modulator signal Biphase coded 1 2 1 8 8 FC 8 9 8 FC Data rate = 16 field Clocks (FC) 1 2 9 8 FC 16 1 16 1 8 9 0 8 0 9 16 1 16 1 8 0 8 0 16 1 16 1 8 1 8 9 1 9 16 1 2 1 2 16 8 9 1 8 9 1 16 1 16 1 9 8 9 0 8 0 16 16 Figure 19. Example of Manchester coding with data rate RF/16 RF/16 Data stream RF-field Inverted modulator signal Manchester coded Data stream 8 FC 1 Data rate = 16 Field Clocks (FC) T5557 T5557 Figure 20. Example of Biphase coding with data rate RF/16 RF/16 17 (24) 18 (24) RF-field subcarrier RF/2 Inverted modulator signal Data stream RF-field f 0= RF/8, f 1= RF/5 Inverted modulator signal Data stream 1 2 1 5 8 FC 8 9 1 8 FC Data rate = 16 Field Clocks (FC) 1 Data rate= 40 Field Clocks (FC) 16 1 1 8 8 0 0 16 1 1 8 8 0 0 16 1 1 5 8 1 1 16 1 1 5 8 1 1 16 1 1 8 8 0 0 Figure 21. Example: FSK 1 coding with data rate RF/40 RF/40, subcarrier f0 = RF/8, f1 = RF/5 Figure 22. Example of PSK1 coding with data rate RF/16 RF/16 T5557 T5557 Rev. A7, 11-Dec-01 Rev. A7, 11-Dec-01 RF-field Inverted modulator signal sub carrier RF/2 1 2 1 2 8 FC 8 9 1 8 FC Data rate = 16 Field Clocks (FC) 8 9 8 FC 16 1 16 1 8 0 8 0 16 1 16 1 8 0 8 0 16 1 16 1 8 1 8 1 16 1 16 1 1 8 8 1 16 1 16 1 8 8 0 0 Figure 23. Example of PSK2 coding with data rate RF/16 RF/16 Data stream RF-field Inverted modulator signal subcarrier RF/2 Datas stream 8 FC 1 Data rate = 16 Field Clocks (FC) T5557 T5557 Figure 24. Example of PSK3 coding with data rate RF/16 RF/16 19 (24) Absolute Maximum Ratings Parameter Symbol Value Unit Maximum DC current into Coil 1/Coil 2 Icoil 20 mA Maximum AC current into Coil 1/Coil 2 f = 125 kHz Icoil p 20 mA Ptot 100 mW Electrostatic discharge maximum to MIL-Standard 883 C method 3015 Vmax 2 kV Operating ambient temperature range Tamb -40 to +85 °C Storage temperature range (data retention reduced) Tstg -40 to +150 °C Power dissipation (dice) (free-air condition, time of application: 1 s) Electrical Characteristics Tamb = +25°C; fcoil = 125 kHz; unless otherwise specified T: directly or indirectly tested during production; Q: guaranteed based on initial product qualification data No. 1 2.1 2.2 2.3 Parameters Supply current (without current consumed by the ext. LC tank circuit) 5 Typ. Max. Unit fRF 100 125 150 kHz 1.5 3 µA T Read - full temp. range 2 4 µA Q Programming full temperature range 25 40 µA Q 3.6 4.0 V Q 3) Tamb = 25 °C (fig. 24) IDD Vcoil pp 3.2 Type* Read mode and write command 2) 6 Vclamp V Q Program EEPROM 2) Coil voltage (AC supply) 8 Vclamp V Q 3 ms Q 23 V T 4.8 V T 600 µA T -6 mV/°C Q ms T Cycles Q Startup time Vcoil pp = 6 V tstartup Clamp voltage 10 mA current into Coil 1/2 Vclamp Vcoilpp = 6 V on test circuit generator and modulation ON4) 6.1 6.2 Min. POR threshold (50 mV hysteresis) 3.3 4 Symbol RF frequency range 3.1 3.2 Test Conditions Modulation parameters 17 V mod pp I mod pp Thermal stability 6.3 2.5 4.2 400 Vmod/ Tamb 7 Programming time From last command gap to re-enter read mode (64 + 648 internal clocks) Tprog 5 8 Endurance Erase all / Write all 1) ncycle 100,00 0 5.7 6 9.1 Top = 55 °C 1) tretention 10 9.2 Top = 150 °C 1) tretention 96 hrs T Top = 250 °C 1) tretention 24 hrs Q Data retention 9.3 20 (24) 20 50 Years T5557 T5557 Rev. A7, 11-Dec-01 T5557 T5557 Notes: 1) Since EEPROM performance is influenced by assembly processes, Atmel confirms the parameters for DOW (tested dice on uncutted wafer) delivery only. 2) Current into Coil 1/Coil 2 is limited to 10 mA. The damping circuitry has the same structure as the e5550. The damping characteristics are defined by the internally limited supply voltage (= min AC coil voltage) 3) IDD measurement setup R = 100 k; VCLK = Vcoil = 5 V: EEPROM programmed to 00 . 000 (erase all); chip in modulation defeat. IDD = (VOUTmax - VCLK) / R 4) Vmod measurement setup: R = 2.3 k; VCLK = 3 V; setup with modulation enabled (figure 24). 5) Extrapolated from single cell measurements and 150°C data retention tests. Figure 25. Measurement setup for IDD and Vmod R BAT68 BAT68 V OUTmax Coil 1 750 + 750 Coil 2 Substrat BAT68 BAT68 21 (24) Rev. A7, 11-Dec-01 Chip Dimensions (in µm) Figure 26. 870 87,5 70 970 910 840 87,5 125 125 435 22 (24) T5557 T5557 Rev. A7, 11-Dec-01 T5557 T5557 Ozone Depleting Substances Policy Statement It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC 88/540/EEC and 91/690/EEC 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. 23 (24) Rev. A7, 11-Dec-01 A tmel Sales Offices France 3, Avenue du Centre 78054 St.-Quentin-en-Yvelines Cedex Tel: +33 1 30 60 70 00 Fax: +33 1 30 60 71 11 Germany Erfurter Strasse 31 85386 Eching Tel: +49 89 319 70 0 Fax: +49 89 319 46 21 Kruppstrasse 6 45128 Essen Tel: +49 201 247 30 0 Fax: +49 201 247 30 47 Theresienstrasse 2 74072 Heilbronn Tel: +49 7131 67 36 36 Fax: +49 7131 67 31 63 Italy Via Grosio, 10/8 20151 Milano Tel: +39 02 38 03 71 Fax: +39 02 38 03 72 34 Sweden Kavallerivaegen 24, Rissne 17402 Sundbyberg Tel: +46 8 587 48 800 Fax: +46 8 587 48 850 United Kingdom Easthampstead Road Bracknell Berkshire RG12 1LX Tel: +44 1344 707 300 Fax: +44 1344 427 371 USA Western 2325 Orchard Parkway San Jose, California 95131 Tel: +1 408 441 0311 Fax: +1 408 436 4200 USA Eastern 1465 Route 31, Fifth floor Annandale New Jersey 08801 Tel: +1 908 848 5208 Fax: +1 908 848 5232 Spain Principe de Vergara, 112 28002 Madrid Tel: +34 91 564 51 81 Fax: +34 91 562 75 14 Hong Kong Room #1219, Chinachem Golden Plaza 77 Mody Road, Tsimhatsui East East Kowloon, Hong Kong Tel: +852 23 789 789 Fax: +852 23 755 733 Korea 25-4, Yoido-Dong, Suite 605, Singsong Bldg. Youngdeungpo-Ku 150-010 Seoul Tel: +822 785 1136 Fax: +822 785 1137 Rep. of Singapore Keppel Building #03-00 25 Tampines Street 92, Singapore 528877 Tel: +65 260 8223 Fax: +65 787 9819 Taiwan, R.O.C. 8F-2, 266 Sec.1 Wen Hwa 2 Rd. Lin Kou Hsiang, 244 Taipei Hsien Tel: +886 2 2609 5581 Fax: +886 2 2600 2735 Japan Tonetsushinkawa Bldg. 1-24-8 Shinkawa Chuo Ku Tokyo 104-0033 Tel: +81 3 3523 3551 Fax: +81 3 3523 7581 Web Site http://www.atmel-wm.com © Atmel Germany GmbH 2001. Atmel Germany GmbH makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel Germany GmbH's Terms and Conditions. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel Germany GmbH are granted by the Company in connection with the sale of Atmel Germany GmbH products, expressly or by implication. Atmel Germany GmbH's products are not authorized for use as critical components in life support devices or systems. Data sheets can also be retrieved fron the Internet: http://www.atmel-wm.com Rev. A7, 11-Dec-01