RF/16 RF/32 RF/40 RF/50 RF/64 RF/80 RF/100 RF/128 4508C ATA5530 RF/10 FILE0000 - Datasheet Archive

 

· · · · · · · Low-power, Low-voltage CMOS Rectifier, Voltage Limiter, Clock

 

Features · · · · · · · Low-power, Low-voltage CMOS Rectifier, Voltage Limiter, Clock Extraction On-chip (No Battery) Small Size Factory Laser Programmable ROM Operating Temperature Range ­40°C to +125°C Radio Frequency (RF): 100 kHz to 450 kHz Transmission options ­ Code Length: 128, 96, 64, 32 bits ­ Bitrate [bit/s]: RF/8, RF/16 RF/16, RF/32 RF/32, RF/40 RF/40, RF/50 RF/50, RF/64 RF/64, RF/80 RF/80, RF/100 RF/100, RF/128 RF/128 ­ Modulation: FSK, PSK, BIPH, Manchester, BIPH-FSK · FDX-B Compatible Coding Possible (ISO 11784/ ISO 11785) 1. Description The e5530 is part of a closed coupled identification system. It receives power from an RF transmitter which is coupled inductively to the IDIC®. The frequency is typically 100 kHz to 450 kHz. Receiving RF, the IDIC responds with a data stream by damping the incoming RF via an internal load. This damping-in-turn can be detected by the interrogator. The identifying data are stored in a 128-bit PROM on the e5530, realized as an array of laser-programmable fuses. The logic block diagram for the e5530 is shown in Figure 1-2 on page 2. The data are output bit-serially as a code of length 128, 96, 64 or 32 bits. The chips are factory-programmed with a unique code. Figure 1-1. 128-bit Read-only IDIC® for RF Identification e5530 Application RF transmitter and interrogator RF IDIC e5530 ID Rev. 4508C 4508C­RFID­08/05 Figure 1-2. Block Diagram Analog front end Mod Coil Clk Data R7 R6 R5 R4 R3 R2 R1 R0 128-bit PROM C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 Clock extractor Modulator FSK PSK BIPH Manchester Row decoder Load Coil VDD 2 VSS Bitrate A6 A5 A4 A3 Rectifier A2 A1 A0 Column decoder Counter e5530 4508C 4508C­RFID­08/05 e5530 2. Chip Dimensions Figure 2-1. Chip Size 0.175 mm e5530 1.17 mm 0.447 mm COIL1 COIL2 Pad: 150µ (Metal: 99% Al, 1% Si) Padwindow: 138µ x 138µ 1.62 mm Thickness: 15 mils 3. Pin Configuration Figure 3-1. Pinning SO8 COIL2 1 8 2 COIL1 7 ATA5530 ATA5530 3 4 Note: 6 5 Pins 2 to 7 have to be open. They are not specified for applications. Table 3-1. Pin Description Name Pad Window Function COIL1 2 138 × 138 µm 1st coil pad COIL2 138 × 138 µm2 2nd coil pad 3 4508C 4508C­RFID­08/05 4. Functional Description 4.1 Read Operation After power up, once the e5530 has detected the incoming RF field, the IC continuously transmits the identification code as long as the RF signal is applied. The transition from the last bit to bit 1 of the next sequence occurs without interruption. Data is transmitted by damping the incoming RF signal by an internal load. These load changes are detected by the reader station. Different kinds of modulation and bitrates are optionally available. 4.2 Rectifier For internal power supply, an on-chip bridge rectifier is used which consists of two diodes and two n-channel transistors. A Zener diode, which protects the circuit against overvoltage on the coil inputs, and a smoothing capacitor for the internal supply are also provided. 4.3 Damping Load Incoming RF will be damped by the power consumption of the IC itself and by an internal load, which is controlled by the modulator. The loads are p-channel transistors connected between VDD and the coil inputs. The IDIC includes mask options for the load circuit: single-side, double-side and alternate-side modulation. There are four modulation methods available which can be selected by fuses. The corresponding timing diagram is shown in Figure 4-1 on page 5. 4.4 FSK Modulation Logical data "1" and "0" are represented as two different frequencies of damping. The frequency for "1" is RF divided by 10, a "0" divides RF by 8. 4.5 PSK Modulation The external coil is damped with a carrier frequency of RF/2. A logical "1" causes (at the end of the bit period) a 180° phase shift on the carrier frequency, while a logical "0" causes no phase shift. 4.6 Biphase Modulation Logical "1" produces a signal which is the same as the internal bitclock. A logical "0" produces no signal change in the middle of the bit period. 4.7 Manchester Modulation A logical "1" causes a rising edge in the middle of a bit period (i.e., switch damping off), while a logical "0" causes a falling edge (i.e., switch damping on). A combination of Biphase- and FSK-modulation is also optionally available. The available combinations between the modulation types and the bitrates are shown in Table 4-1 on page 5 "Transmission Options". 4 e5530 4508C 4508C­RFID­08/05 e5530 Table 4-1. Transmission Options Modulation Carrier Frequency (CF) Bitrate [bit/s] FSK RF/8, RF/10 RF/10 RF/32 RF/32, RF/40 RF/40, RF/50 RF/50, RF/64 RF/64, RF/80 RF/80, RF/100 RF/100, RF/128 RF/128 PSK RF/2 CF/4, 8, 16, 32 Biphase Manchester Figure 4-1. RF/8, RF/16 RF/16, RF/32 RF/32, RF/64 RF/64, RF/100 RF/100, RF/128 RF/128 RF/8, RF/16 RF/16, RF/32 RF/32, RF/64 RF/64, RF/100 RF/100, RF/128 RF/128 Timing Diagram for Modulation Options BitClk Data 1 0 1 1 0 0 1 FSK PSK Man Biph 4.8 Reading Distances The e5530 is able to operate from very weak fields. Nevertheless, there are some general rules which influence the achievable reading distance. · Best results are accomplished when the transponder points towards the reader coil. · The transponder should not be embedded in metal, which will reduce the applicable magnetic field and thus the reading distance. · The strength of the generated magnetic field and the sensitivity of the demodulator are the most important factors for a good reading distance. Figure 4-2. Example for a 64-bit Code E6 Header 00 00 00 10 2D 72 5D 56-bit ID code 5 4508C 4508C­RFID­08/05 The identification code is transmitted continuously. After the RF field is applied, the e5530H-232 starts with the first bit (MSB) of the header byte "E6hex" ("1110 0110"), followed by a unique 56-bit serial number. No checksum is included in this sample code. Pulsing the RF field may reduce the synchronization task as the first byte transmitted is known already (i.e., E6hex). This is even feasible, if the first bit may be lost due to reader synchronization problems. 4.9 Customer ID Code Selection In general the customer may choose any ID code suitable to his application. To avoid code duplication, Atmel will define a fixed header ­ i.e, the first 8 bits of the code ­ for each customer. 4.10 Modes of Operation ­ Options For any new product variant, the customer has to select the following operation options which are configured in the laser ROM as well: · Bitrate, which is defined as field clocks per bit (e.g., RF/40 RF/40 = 125 kHz/40 = 3.125 kBit/s) (see table Table 4-1 on page 5 "Transmission Options") · Modulation method (see Figure 4-1 on page 5) · Code length: 32, 64, 96 or 128 bits For programming the ID code into the laser ROM, one of the following data has to be supplied: · ID code algorithm which is implemented in Atmel's code management software (Atmel will generate the codes as requested) · Customer generated ID codes on floppy disk or per email/ftp. The format has to comply to the following rules: ­ The ID code file is a plain ASCII text file. ­ The code files should be compressed. Please make self extracting files. ­ The code files are used in alphabetical order of their file names (including letters and numbers). Used - i.e. programmed - code files are discarded. ­ Each line of the code file must contain one ID code for one IC. ­ The code is in hexadecimal format. The code may contain spaces for better readability. ­ The code line is exactly as long as the selected code length (e.g. 64 bits 16 hex numbers). ­ The line must end with a carriage return. ­ The first 8 bits are fixed, this is the unique customer header which is defined by Atmel. ­ Each hexadecimal code entry must be preceded by a decimal serial number. Serial number and code must be separated by a space. ­ The serial number has to be unique and is up-counting to avoid double programming. ­ The series numbers of two consecutive files (file name!) has to count also for proper linking. 6 e5530 4508C 4508C­RFID­08/05 e5530 Figure 4-3. Example of Two Code Files with Header = E6 and 64-bit Code Length FILE0000 FILE0000.TXT File name 00001 E65F34E25801904F E65F34E25801904F 00002 E634E25801904FAA E634E25801904FAA 00003 E6910AG7000010FE E6910AG7000010FE . . 12345 E610ABE4F9014821 E610ABE4F9014821 Code file Last code Carriage return 8-bit header Space necessary Series number FILE0001 FILE0001.TXT Next code 12346 E6A04EB73087FCC0 E6A04EB73087FCC0 12347 E60178DC00F03460 E60178DC00F03460 . 5. Absolute Maximum Ratings Parameters Symbol Value Unit Maximum current into Coil1 and Coil2 Icoil 10 mA Maximum power dissipation (dice) Ptot 100 mW(1) Maximum ambient air temperature with voltage applied Tamb ­40 to +125 °C Storage temperature Tstg ­65 to +200 °C Note: 1. Free-air condition. Time of application: 1s Stresses above those listed under `Absolute Maximum Ratings' may cause permanent damage to the device. Functional operation of the device at these conditions is not implied. 6. Electrical Characteristics Tamb = 25°C, reference terminal is VDD, operating voltage VDD ­ VSS = 3V DC, unless otherwise specified No. Parameters Test Conditions Condition for logic test Symbol Min. Max. Unit VSS ­1.5 ­5.0 V 125 °C 450 kHz 1 Operating voltage 2 Operating temperature Tamb ­40 3 Input frequency (RF) fCLK Typ. 100 4 Operating current fCLK = 125 kHz, VSS = ­2V ICC 5 Clamp voltage I = 4 mA VCL (1) Note: 3 6.7 mA 10 V 1. Typical parameters represent the statistical mean values 7 4508C 4508C­RFID­08/05 Figure 6-1. Measurement Setup for IDD IDD VDD COIL1 ~ 2V = COIL2 VSS Vpp Coil at 1.5V Figure 6-2. Simplified Damping Circuit 100 ~ 2V COIL1 Mod COIL2 100 ~ 2V 7. Application Example Figure 7-1. Typical Application Circuit IAC From oscillator 125 kHz 740 µH 4.05 mH 390 pF Energy Input capacitance 5 pF static, 4 pF dynamic COIL1 (pin 8) e5530 (SO8) Data To read amplifier COIL2 (pin 1) 2.2 nF 8 e5530 4508C 4508C­RFID­08/05 e5530 8. Ordering Information Extended Type Number Package e5530H-232-DOW e5530H-232-DIT ATA5530H-232-TAQY ATA5530H-232-TAQY(2) DOW DIT SO8 Notes: Configuration Checksum Header Manchester e5530H-zzz-DOW(1) DOW DIT e5530H-zzz-DIT(1) ATA5530H-zzz-TAQY(1),(2) SO8 Modulation Data Rate RF/32 RF/32 64-bit No checksum E6 ID Code SPQ (Minimum Volume) Minimum Order Volume fixed and unique code 10 kpcs 10 kpcs 1120 10 kpcs 10 kpcs 1120 > 600 kpcs p.a. > 600 kpcs p.a. > 400 kpcs p.a. Defined by customer 1. - Definition of customized part number basing on orders for first year volume (300 kpcs) - Definition of header, ID code, checksum etc. according to customers data base - 5.000 US$ initial cost for customer specific laser-fusing - Lead time 3 month - Low volume customized applications may be covered by TK5551-PP TK5551-PP programming. With identical features of TK5530H-zzz-PP possible 2. SO8 in tape and reel, lead-free 8.1 Order Code The full order code for the e5530 is e5530H-zzz-pkg or e5530G-zzz-pkg, where zzz is a customer specific number defined by Atmel. pkg (package) defines the delivery form: - DOW factory programmed, tested unsawn, backlapped (15 mils) wafers - DIT cutted chips in wafflepack (Dice In Tray) - TAQY SO8-packaged parts (taped and reeled, lead-free) Samples: Atmel supplies e5530 samples, which are set to Manchester modulation at RF/32 RF/32 with a 64-bit ID code (order code: ATA5530H-232-TAQY ATA5530H-232-TAQY (SO8 in tape and reel, lead-free) 9 4508C 4508C­RFID­08/05 9. Package Information Package SO8 Dimensions in mm 5.2 4.8 5.00 4.85 3.7 1.4 0.25 0.10 0.4 1.27 0.2 3.8 6.15 5.85 3.81 8 5 technical drawings according to DIN specifications 1 4 10. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4508C-RFID-08/05 4508C-RFID-08/05 10 History · · · · Put datasheet in a new template First page: Pb-free logo added First Page 3: Figure 3-1 changed Page 9: Ordering Information changed e5530 4508C 4508C­RFID­08/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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