500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
DUALOUTPUT-ISOFLYBACK-REF Texas Instruments Dual Output Isolated Flyback Design: 5V @ 0.2A, 12V @ 2.1A w/2 addl out 3.3V @ 0.5A, 5V @ 0.5A visit Texas Instruments
ISL68127IRAZ-T Intersil Corporation Digital Dual Output, 7-Phase Configurable, PWM Controller with PMBus; QFN48; Temp Range: -40° to 85°C visit Intersil
ISL68127IRAZ-T7A Intersil Corporation Digital Dual Output, 7-Phase Configurable, PWM Controller with PMBus; QFN48; Temp Range: -40° to 85°C visit Intersil
ISL69125IRAZ Intersil Corporation Digital Dual Output, 4-Phase Configurable, VR13 PWM Controller; TQFN40; Temp Range: -40° to 85°C visit Intersil
ISL69133IRAZ-T Intersil Corporation Digital, Dual Output, 4-Phase Configurable, VR13/IMVP8 PWM Controller; TQFN40; Temp Range: -40° to 85°C visit Intersil
ISL69138IRAZ-T7A Intersil Corporation Digital, Dual Output, 7-Phase Configurable, VR13/IMVP8 PWM Controller; QFN48; Temp Range: -40° to 85°C visit Intersil

dual 7-segment-display pin configuration

Catalog Datasheet MFG & Type PDF Document Tags

pin diagram of LED dot matrix display

Abstract: 14 pin dot matrix LED display diagram - Dimensions & Configuration Dot Matrix Dimensions Pin Configuration Dot Matrix Diagram , 8 Matrix - Dimensions & Configuration Dot Matrix Dimensions Pin Configuration Dot Matrix , Dimensions Pin Configuration Dot Matrix Diagram Common Anode 570311x Common Cathode 570321x , Dimensions Pin Configuration Dot Matrix Diagram Common Anode 570312x Common Cathode 570322x , Dimensions Pin Configuration Dot Matrix Diagram Common Anode 580311x Common Cathode 580321x
Continental Device India
Original

IMAPCAR

Abstract: uPD48288236 IMAPCAR2-300-USB board 4.1.9 SW5 System configuration: IMAPCAR2 Input pin configuration SW , Undefined Undefined Undefined SW5 4.1.10 SW6 System configuration: IMAPCAR2 Input pin configuration , Undefined Undefined SW6 4.1.11 SW7 System configuration: IMAPCAR2 Input pin configuration SW , IMAPCAR2 LVSDD Configuration. Please do not change the factory setting 1 3 Jumper pin 1-2 2-3 , configuration Please do not change the factory setting A B C 1 4 1 2 3 4 IMAPCAR2 Pin Name
NEC
Original
EPMC-PU-0115-1 IMAPCAR uPD48288236 QTH-060-05-L-D-A 8830E-026-170S-F QTH-060-05 UPD70F3134AYGJ-UEN-A 47KPUP

xc3s500e fg320

Abstract: intel strataflash j3d Generator (BitGen) Options. During configuration a Low logic level on the HSWAP pin activates pull-up , Digital Clock Manager (DCM) Clock Network Configuration Powering Spartan-3E FPGAs Production Stepping , Timing - DCM Timing - Block RAM Timing - Multiplier Timing - Configuration and JTAG Timing Module 4: Pinout Descriptions DS312-4 (v3.7) April 18, 2008 · · · · Pin Descriptions Package , logic cell. New features improve system performance and reduce the cost of configuration. These Spartan
Xilinx
Original
XC3S500E xc3s500e fg320 intel strataflash j3d SPARTAN 3E STARTER BOARD transistor tt 2222 eeprom programmer schematic winbond pin configuration 500K variable resistor DS312 DS312-1 DS312-3 DS312-2 XC3S100E CP132

16650 uart

Abstract: 16550AF pin Female D type (via flylead with PC bracket.) PCI Dual LPT & RS232 Software Configuration , Printer Port Configuration. On the PCI Dual LPT & RS232 Card, the parallel printer port is the lower 25-pin , Specifications. Chapter 3 - PCI DUAL LPT & RS232 Software Configuration Guide. The Layout Of This Manual , DUAL LPT & RS232 Software Configuration Guide, shows you how to configure your operating system to , DUAL LPT & RS232 Card. 10 Parallel Printer Port Configuration
-
Original
16650 uart 16550AF LPT 25 pin LPT port male D-type device control through RS232 application rs232 card isa slot scheme RS422 RS485

xc3s500e fg320

Abstract: XC3S500E FGG320 . New features improve system performance and reduce the cost of configuration. These Spartan , global clocks and eight clocks for each half of device, plus abundant low-skew routing Configuration , Specification R Introduction and Ordering Information Configuration Spartan-3E FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources. The FPGA's configuration data
Xilinx
Original
XC3S500E FGG320 XC3S250E TQG144 XC3S100E TQG144 CP132 "pin-compatible" XC3S100E TQ144 xc3s1600e fg320 XC3S250E FG400 FG484 VQ100 TQ144 PQ208

xc3s500e fg320

Abstract: XC3S500E FGG320 Dedicated Multipliers Digital Clock Manager (DCM) Clock Network Configuration Powering Spartan-3E FPGAs , Configuration and JTAG Timing Module 4: Pinout Descriptions DS312-4 (v1.1) March 21, 2005 72 pages · · · · Pin Descriptions Package Overview Pinout Tables Footprint Diagrams IMPORTANT NOTE: The , cell. New features improve system performance and reduce the cost of configuration. These Spartan , global clocks and eight clocks for each half of device, plus abundant low-skew routing Configuration
Xilinx
Original
AT45DBX DS3121 M25PXX XCF32P FOOT PRINT AT45DBXX X2Y3

cmos 4093

Abstract: IDT72V201 pin. In this configuration, when WENA1 (WENB1) is LOW, data can be loaded into the input register of , ,048 x 9 and DUAL 4,096 x 9 OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION - When FIFO A (B , Bidirectional Configuration 15 72V801/72V811/72V821/72V831/72V841 3.3 Volt DUAL CMOS SyncFIFOTM DUAL 256 , 72V801/72V811/72V821/72V831/72V841 3.3 Volt DUAL CMOS SyncFIFOTM DUAL 256 x 9, DUAL 512 x 9, DUAL 1,024 x 9, DUAL 2,048 x 9 and DUAL 4,096 x 9 COMMERCIAL TEMPERATURE RANGES PRELIMINARY 3.3
Integrated Device Technology
Original
IDT72V801 IDT72V811 IDT72V821 IDT72V831 IDT72V841 IDT72V201 cmos 4093 IDT72V211 IDT72V221 IDT72V231 IDT72V241

AN2232L-02

Abstract: FT232 ASYNCHRONOUS 245 FIFO Configuration . 21 Dual Port , 22 Dual Port RS485 Configuration , the configuration of the FT2232H. The following table details the function of each pin dependent on , Pin No. 16 17 18 19 21 22 23 Channel B Pin No. 38 39 40 41 43 44 45 Name Type RS232 Configuration , WR# signals. Channel A Pin No. Channel B Pin No. Name Type FT245 Configuration Description 24,23
FTDI
Original
AN2232L-02 FT232 ASYNCHRONOUS 245 FIFO XILINX ft2232 usb jtag Xilinx jtag cable Schematic level shifter 5V to 3.3V ft2232h spi RS232/RS422/RS485 AN2232L-1

cmos 4093

Abstract: pin configuration 4093 asynchronous of one another for dual clock operation. An output enable pin (OEA, OEB) is provided on the read , QB5 QB4 QB3 QB2 QB1 FFA EFA OEA RENA2 RCLKA RENA1 PIN CONFIGURATION 4093 drw 02 , and DUAL 4,096 x 9 COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTIONS The IDT72V801/72V811/72V821 , DUAL 4,096 x 9 OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION - When FIFO A (B) is in a , 14). In this configuration, the Write Enable 2/Load WENA2/LDA (WENB2/LDB) pin is set LOW at Reset
Integrated Device Technology
Original
pin configuration 4093 IDT72V801/72V811/72V821/72V831/72V841 IDT72V201/72V211/72V221/72V231/ 72V241 IDT72V801/72V811/72V821/72V83 IDT72V801/72V811/72V821/ 72V831/72V841

how to use the FT2232H device in FT245 Style

Abstract: FT2232HL Configuration . 22 Dual Port , 23 Dual Port RS485 Configuration , DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC Version 2.21 Clearance No.: FTDI#77 3 Device Pin , configuration of the FT2232H. The following table details the function of each pin dependent on the , PWREN# PWRSAV # Pin functions (depends on configuration) 245 FIFO SYNC D0 D1 D2 D3 D4 D5 D6 D7 RXF
FTDI
Original
how to use the FT2232H device in FT245 Style FT2232HL FT2232HQ how to use the FT2232H device in FT245 Style Sync FT2232D

mcu FT232

Abstract: FT2232H control for RS485 serial applications using TXDEN pin. Operational configuration mode and USB , 4.3.1 Dual Port RS232 Configuration . 21 4.3.2 Dual Port RS422 Configuration . 22 4.3.3 Dual Port RS485 Configuration , function of each pin dependent on the configuration of the interface. Each of the functions are described
FTDI
Original
mcu FT232 flash card reader schematic AN108 AN114 AN135 FTDI FT245 USB FIFO device
Abstract: 4.3.1 Dual Port RS232 Configuration . 21 4.3.2 Dual Port RS422 Configuration . 22 4.3.3 Dual Port RS485 Configuration , function of each pin dependent on the configuration of the interface. Each of the functions are described , "¦ (approx) pull up resistor to VCCIO. FT2232H Pin Pin functions (depends on configuration) ASYNC FTDI
Original

FT2232HL

Abstract: FT2232H . Auto-transmit enable control for RS485 serial applications using TXDEN pin. Operational configuration mode and , 4.3.1 Dual Port RS232 Configuration . 21 4.3.2 Dual Port RS422 Configuration . 22 4.3.3 Dual Port RS485 Configuration , function of each pin dependent on the configuration of the interface. Each of the functions are described
FTDI
Original
XILINX ft2232 93C66 93C56 93C46 ft245 ft232 spi example FT222H FTCI2C AN2232-02

XC3S400 TQ144

Abstract: xc3s400 pinout form differential I/Os. IO, IO_Lxxy_# DUAL Dual-purpose pin used in some configuration modes , offers significantly more detail about each pin, especially for the dual- or special-function pins used , pin is not used during configuration, this pin behaves as an I/O-type pin. There are 12 dual-purpose , /DOUT, IO_Lxxy_#/INIT_B CONFIG Dedicated configuration pin. Not available as a user-I/O pin , the differential standards. DUAL: Dual-purpose configuration pins IO_Lxxy_#/DIN/D0, IO_Lxxy_#/D1
Xilinx
Original
DS099-4 XC3S400 TQ144 xc3s400 pinout XC3S200 PQ208 SPARTAN-3 XC3S400 PQ208 XC3S200 PQ208 pin diagram XC3S400 PQ208 FG676 FG900 FG320 FG1156 XC3S2000

FT2232HL

Abstract: FT245 control for RS485 serial applications using TXDEN pin. Operational configuration mode and USB , 4.3.1 Dual Port RS232 Configuration . 21 4.3.2 Dual Port RS422 Configuration . 22 4.3.3 Dual Port RS485 Configuration , pin. The function of many pins is determined by the configuration of the FT2232H. The following table
FTDI
Original
FT232 software uart 8048 Multiprotocol ftcs canbus application of LC oscillator

FT2232HL

Abstract: FT2232H control for RS485 serial applications using TXDEN pin. Operational configuration mode and USB , 4.3.1 Dual Port RS232 Configuration . 21 4.3.2 Dual Port RS422 Configuration . 22 4.3.3 Dual Port RS485 Configuration , pin. The function of many pins is determined by the configuration of the FT2232H. The following table
FTDI
Original
93c46 spi mp3 player schematic diagram AD117
Abstract: applications using TXDEN pin. Operational configuration mode and USB Description strings configurable in , 4.3.1 Dual Port RS232 Configuration . 21 4.3.2 Dual Port RS422 Configuration . 22 4.3.3 Dual Port RS485 Configuration , pin. The function of many pins is determined by the configuration of the FT2232H. The following table FTDI
Original

xc3s500e vq100

Abstract: m1l43 Configuration and JTAG Timing Module 2: Functional Description DS312 (4.0) October 29, 2012 · Input/Output , Configuration Powering Spartan®-3E FPGAs Production Stepping Module 4: Pinout Descriptions DS312 (4.0) October 29, 2012 · · · · Pin Descriptions Package Overview Pinout Tables Footprint Diagrams © Copyright , features improve system performance and reduce the cost of configuration. These Spartan-3E FPGA , per each half of device, plus abundant low-skew routing Configuration interface to industry-standard
Xilinx
Original
xc3s500e vq100 m1l43 XC3S250E TQ144 STARTER KIT BOARD XC3S500EVQ100 Xilinx Parallel Cable IV spartan-3 XC3S500E-VQ100

xc3s500e fg320

Abstract: XC3S500E FGG320 configuration a Low logic level on the HSWAP pin activates pull-up resistors on all I/O and Input-only pins not , RAM Dedicated Multipliers Digital Clock Manager (DCM) Clock Network Configuration Powering , Configuration and JTAG Timing Module 4: Pinout Descriptions DS312-4 (v3.8) August 26, 2009 · · · · Pin Descriptions Package Overview Pinout Tables Footprint Diagrams © 2005­2009 Xilinx, Inc , features improve system performance and reduce the cost of configuration. These Spartan-3E FPGA
Xilinx
Original
xc3s500e VQG100 NUMONYX xilinx bpi intel j3d XC3S250E vqg100 XC3S250E design guide atmel package marking at29 XC3S1600E VQG100
Abstract: asynchronous of one another for dual clock operation. An output enable pin (OEA, OEB) is provided on the read , ,096 x 9 COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATION TQFP (PN64-1, order code: PF) TOP , 512 x 9, DUAL 1,024 x 9, DUAL 2,048 x 9 and DUAL 4,096 x 9 COMMERCIAL TEMPERATURE RANGES PIN , ) is the only enable control pin. In this configuration, when WENA1 (WENB1 ) is LOW, data can be , TEMPERATURE RANGES this configuration, the Write Enable 2/Load WENA2/LDA (WENB2/LDB) pin is set LOW at -
OCR Scan
IDT72 V801/72V811 DT72V801/72V811/72V821/ 72V801
Showing first 20 results.