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DUALOUTPUT-ISOFLYBACK-REF Texas Instruments Dual Output Isolated Flyback Design: 5V @ 0.2A, 12V @ 2.1A w/2 addl out 3.3V @ 0.5A, 5V @ 0.5A ri Buy
TVP5021DUAL Texas Instruments NTSC/PAL Digital Video Decoder 80-HTQFP ri Buy
HIP1013CB-T Intersil Corporation DUAL SWITCHING CONTROLLER, PDSO14 ri Buy

dual 7-segment-display pin configuration

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Abstract: - Dimensions & Configuration Dot Matrix Dimensions Pin Configuration Dot Matrix Diagram , 8 Matrix - Dimensions & Configuration Dot Matrix Dimensions Pin Configuration Dot Matrix , Dimensions Pin Configuration Dot Matrix Diagram Common Anode 570311x Common Cathode 570321x , Dimensions Pin Configuration Dot Matrix Diagram Common Anode 570312x Common Cathode 570322x , Dimensions Pin Configuration Dot Matrix Diagram Common Anode 580311x Common Cathode 580321x ... Continental Device India
Original
datasheet

19 pages,
2876.11 Kb

570311K 8 x 8 DOT MATRIX DISPLAY diagram of LED dot matrix 8 x 8 led dot matrix 2 x 16 led dot matrix pitch 2.5 mm matrix 7 x 5 white 8 x 8 DOT MATRIX DISPLAY dual colour led dot matrix 5*7 led dot matrix display 5 x 7 DOT MATRIX DIAGRAM 5 x 7 dot matrix display common cathode 5*7 led dot matrix 14 pin DOT MATRIX diagram of LED matrix display 5 x 8 led dot matrix c code DOT LED MATRIX 14 pin dot matrix LED display diagram pin diagram of LED dot matrix display TEXT
datasheet frame
Abstract: IMAPCAR2-300-USB IMAPCAR2-300-USB board 4.1.9 SW5 System configuration: IMAPCAR2 Input pin configuration SW , Undefined Undefined Undefined SW5 4.1.10 SW6 System configuration: IMAPCAR2 Input pin configuration , Undefined Undefined SW6 4.1.11 SW7 System configuration: IMAPCAR2 Input pin configuration SW , IMAPCAR2 LVSDD Configuration. Please do not change the factory setting 1 3 Jumper pin 1-2 2-3 , configuration Please do not change the factory setting A B C 1 4 1 2 3 4 IMAPCAR2 Pin Name ... NEC
Original
datasheet

45 pages,
992.69 Kb

L16 8pin LED10 LLDRAM CN10 XC3S700AFGG400 QTH-060-05-L-D EPMC car2 UPD70F3134AY EPMC-PU-0115-1 TOP11 IMAPCAR2 nec V20 microcontroller QSH-060-01-L-D-A IMAPCAR2-300-USB EPMC-PU-0115-1 8830E-026-170S-F IMAPCAR2-300-USB EPMC-PU-0115-1 QTH-060-05 IMAPCAR2-300-USB EPMC-PU-0115-1 UPD70F3134AYGJ-UEN-A IMAPCAR2-300-USB EPMC-PU-0115-1 IMAPCAR IMAPCAR2-300-USB EPMC-PU-0115-1 uPD48288236 IMAPCAR2-300-USB EPMC-PU-0115-1 QTH-060-05-L-D-A IMAPCAR2-300-USB EPMC-PU-0115-1 IMAPCAR2-300-USB IMAPCAR2-300-USB EPMC-PU-0115-1 TEXT
datasheet frame
Abstract: Generator (BitGen) Options. During configuration a Low logic level on the HSWAP pin activates pull-up , Digital Clock Manager (DCM) Clock Network Configuration Powering Spartan-3E FPGAs Production Stepping , Timing - DCM Timing - Block RAM Timing - Multiplier Timing - Configuration and JTAG Timing Module 4: Pinout Descriptions DS312-4 DS312-4 (v3.7) April 18, 2008 · · · · Pin Descriptions Package , logic cell. New features improve system performance and reduce the cost of configuration. These Spartan ... Xilinx
Original
datasheet

234 pages,
3238.07 Kb

16x4 sram CAT16-LV4F12 M25PXX AMIC date code marking spartan-3 starter UG331 spi flash programmer schematic schematic diagram UPS inverter phase XC3S500E FGG320 XC3S250E TQ144 STARTER KIT BOARD spartan 3a AT49 jtag cable Schematic AT45DB XC3S500E eeprom programmer schematic winbond SPARTAN 3E STARTER BOARD transistor tt 2222 xc3s500e fg320 TEXT
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Abstract: pin Female D type (via flylead with PC bracket.) PCI Dual LPT & RS232 RS232 Software Configuration , Printer Port Configuration. On the PCI Dual LPT & RS232 RS232 Card, the parallel printer port is the lower 25-pin , Specifications. Chapter 3 - PCI DUAL LPT & RS232 RS232 Software Configuration Guide. The Layout Of This Manual , DUAL LPT & RS232 RS232 Software Configuration Guide, shows you how to configure your operating system to , DUAL LPT & RS232 RS232 Card. 10 Parallel Printer Port Configuration ... Original
datasheet

24 pages,
2582.84 Kb

set top box RS232 Driver 16950 16c550 to isa slot scheme cable rs232 to idc 10 pin rs232 printer buffer interface 16450 UART ta7aa lpt port RS232 serial to parallel RS232 communication port 16650 16750 UART rs232 card isa slot scheme rs485 serial card datasheet rs232 protocol LPT port male D-type LPT 25 pin 16550AF 16650 uart TEXT
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Abstract: . New features improve system performance and reduce the cost of configuration. These Spartan , global clocks and eight clocks for each half of device, plus abundant low-skew routing Configuration , Specification R Introduction and Ordering Information Configuration Spartan-3E FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources. The FPGA's configuration data ... Xilinx
Original
datasheet

192 pages,
1710.38 Kb

400-BALL DS312-1 XC3S250ETM XC3S250E vqg100 PQ208AGQ0525 xc3s1600e fg320 XC3S100E TQ144 XC3S100E TQG144 CP132 "pin-compatible" XC3S250E TQG144 XC3S500E FGG320 xc3s500e fg320 TEXT
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Abstract: Dedicated Multipliers Digital Clock Manager (DCM) Clock Network Configuration Powering Spartan-3E FPGAs , Configuration and JTAG Timing Module 4: Pinout Descriptions DS312-4 DS312-4 (v1.1) March 21, 2005 72 pages · · · · Pin Descriptions Package Overview Pinout Tables Footprint Diagrams IMPORTANT NOTE: The , cell. New features improve system performance and reduce the cost of configuration. These Spartan , global clocks and eight clocks for each half of device, plus abundant low-skew routing Configuration ... Xilinx
Original
datasheet

193 pages,
1670.8 Kb

grid tie inverters circuit diagrams DS312-2 DS312-1 PQ208AGQ0525 XC3S100E TQ144 XC3S100E TQG144 D1234 X2Y3 spi flash m25pxx DS3121 XCF32P FOOT PRINT M25PXX XC3S250E TQG144 XC3S500E FGG320 xc3s500e fg320 TEXT
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Abstract: pin. In this configuration, when WENA1 (WENB1) is LOW, data can be loaded into the input register of , ,048 x 9 and DUAL 4,096 x 9 OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION - When FIFO A (B , Bidirectional Configuration 15 72V801/72V811/72V821/72V831/72V841 72V801/72V811/72V821/72V831/72V841 3.3 Volt DUAL CMOS SyncFIFOTM DUAL 256 , 72V801/72V811/72V821/72V831/72V841 72V801/72V811/72V821/72V831/72V841 3.3 Volt DUAL CMOS SyncFIFOTM DUAL 256 x 9, DUAL 512 x 9, DUAL 1,024 x 9, DUAL 2,048 x 9 and DUAL 4,096 x 9 COMMERCIAL TEMPERATURE RANGES PRELIMINARY 3.3 ... Integrated Device Technology
Original
datasheet

16 pages,
229.53 Kb

IDT72V841 IDT72V201 IDT72V211 IDT72V221 IDT72V231 IDT72V241 IDT72V801 IDT72V811 IDT72V821 IDT72V831 cmos 4093 72V801/72V811/72V821/72V831/72V841 TEXT
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Abstract: Configuration . 21 Dual Port , 22 Dual Port RS485 RS485 Configuration , the configuration of the FT2232H FT2232H. The following table details the function of each pin dependent on , Pin No. 16 17 18 19 21 22 23 Channel B Pin No. 38 39 40 41 43 44 45 Name Type RS232 RS232 Configuration , WR# signals. Channel A Pin No. Channel B Pin No. Name Type FT245 FT245 Configuration Description 24,23 ... FTDI
Original
datasheet

65 pages,
1373.58 Kb

Xilinx jtag cable Schematic level shifter 5V to 3.3V FT2232HQ ft2232h spi FT2232 FT2232H XILINX ft2232 usb jtag FT232 ASYNCHRONOUS 245 FIFO RS232/RS422/RS485 RS232 RS485 64-LD TEXT
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Abstract: asynchronous of one another for dual clock operation. An output enable pin (OEA, OEB) is provided on the read , QB5 QB4 QB3 QB2 QB1 FFA EFA OEA RENA2 RCLKA RENA1 PIN CONFIGURATION 4093 drw 02 , and DUAL 4,096 x 9 COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTIONS The IDT72V801/72V811/72V821 IDT72V801/72V811/72V821 , DUAL 4,096 x 9 OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION - When FIFO A (B) is in a , 14). In this configuration, the Write Enable 2/Load WENA2/LDA (WENB2/LDB) pin is set LOW at Reset ... Integrated Device Technology
Original
datasheet

16 pages,
241.47 Kb

pin configuration 4093 IDT72V201 IDT72V211 IDT72V221 IDT72V231 IDT72V241 IDT72V801 IDT72V811 IDT72V821 IDT72V831 IDT72V841 cmos 4093 TEXT
datasheet frame
Abstract: Configuration . 22 Dual Port , 23 Dual Port RS485 RS485 Configuration , DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC Version 2.21 Clearance No.: FTDI#77 3 Device Pin , configuration of the FT2232H FT2232H. The following table details the function of each pin dependent on the , PWREN# PWRSAV # Pin functions (depends on configuration) 245 FIFO SYNC D0 D1 D2 D3 D4 D5 D6 D7 RXF ... FTDI
Original
datasheet

67 pages,
1637.73 Kb

level shifter 5V to 3.3V FT232 ASYNCHRONOUS 245 FIFO FT2232H FT2232HQ FT2232HL RS232/RS422/RS485 RS232 RS485 64-LD TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
No abstract text available
/download/88270223-265198ZC/mdc_10.doc
Intel 26/02/1999 1389 Kb DOC mdc_10.doc
Designing with the Symmetrical Dual Processing Configuration , refer to "Managing and Designing with the Symmetrical Dual Processing Configuration" on page 11-225 . Managing and Designing with the Symmetrical Dual Processing Configuration module using the APICEN pin. The startup IPI must be sent via the local APICs. Once the Dual processor Microprocessor Initialization and Configuration
/datasheets/files/intel/design/intarch/techinfo/pentium/initconf.htm
Intel 03/02/1999 168.61 Kb HTM initconf.htm
Designing with the Symmetrical Dual Processing Configuration , refer to "Managing and Designing with the Symmetrical Dual Processing Configuration" on page 11-225 . Managing and Designing with the Symmetrical Dual Processing Configuration module using the APICEN pin. The startup IPI must be sent via the local APICs. Once the Dual processor Microprocessor Initialization and Configuration
/datasheets/files/intel/products one/design/intarch/techinfo/pentium/initconf.htm
Intel 04/05/1999 168.61 Kb HTM initconf.htm
configuration (unipolar, dual half bridge or full bridge; see Data and Address decoding). Every input channel (full bridge, dual half bridge, unipo- lar motor). A0 A1 1 0 This configuration is used to Inverted diagonal chopper X 1 1 1 Tristate left and right c) Dual Half Bridge Configuration D0 D1 D2 D3 ) L6280 L6280 16/26 DUAL HALF BRIDGE CONFIGURATION (CH1 and CH2) In dual half bridge configuration the in side the blank boxes in the following block diagrams. In dual half bridge configuration, the
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1387-v1.htm
STMicroelectronics 25/05/2000 38.5 Kb HTM 1387-v1.htm
, D0 to D3 choose the type of configuration (unipolar, dual half bridge or full bridge; see Data and to D3 are used to specify the configuration of the channel (full bridge, dual half bridge, unipo- lar Tristate left and right c) Dual Half Bridge Configuration D0 D1 D2 D3 X 0 0 0 Tristate left and right X 0 0 X000 configuration) L6280 L6280 16/26 DUAL HALF BRIDGE CONFIGURATION (CH1 and CH2) In dual half bridge substi- tuted in side the blank boxes in the following block diagrams. In dual half bridge configuration
/datasheets/files/stmicroelectronics/books/ascii/docs/1387.htm
STMicroelectronics 25/05/2000 40.02 Kb HTM 1387.htm
CHARACTERISTICS 2. PIN ASSIGNMENT AND FUNCTIONS 2.1 Pin Assignment 2.2 Pin Names and Functions 3. OPERATION 3.1 CPU 3.1.1 Reset 3.2 Memory Map 3.3 Dual 3.3.3 Internal Clock Pin Output Function 3.3.4 Standby Controller 3.4 Interrupts Control Registers 3.9.2 Configuration 3.9.3 Operational Description 3.10 Serial Bus Interface (SBI) 3.10.1 Configuration 3.10.2 Serial Bus Interface (SBI
/datasheets/files/toshiba/micon2/900l_3/doc/cs20f.htm
Toshiba 11/02/1999 5.51 Kb HTM cs20f.htm
, D0 to D3 choose the type of configuration (unipolar, dual half bridge or full bridge; see Data and to D3 are used to specify the configuration of the channel (full bridge, dual half bridge, unipo- lar Tristate left and right c) Dual Half Bridge Configuration D0 D1 D2 D3 X 0 0 0 Tristate left and right X 0 0 X000 configuration) L6280 L6280 16/26 DUAL HALF BRIDGE CONFIGURATION (CH1 and CH2) In dual half bridge substi- tuted in side the blank boxes in the following block diagrams. In dual half bridge configuration
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1387-v2.htm
STMicroelectronics 14/06/1999 36.65 Kb HTM 1387-v2.htm
Supply Precision Op Amp  The RH1078M RH1078M is a micropower dual op amp in the standard 8-pin configuration LM124/LM148/OP-11/5156 LM124/LM148/OP-11/5156 pin configuration. Low offset voltage (300uV max), low drift (≤2.5uV/°C), low characteristics than the LM111 LM111. Although pin compatible with the LM111 LM111, it offers four times lower bias current RH1013M RH1013M   Dual Precision Operational Amplifier  The RH1013M RH1013M is the first precision dual operational amplifier which directly upgrades designs in the industry standard 8-pin DIP LM158/MC1558/OP-221 LM158/MC1558/OP-221 pin
/datasheets/files/linear/c1010/c1503/c1503-defaultcolumnstypical-v1.html
Linear 09/02/2007 24.87 Kb HTML c1503-defaultcolumnstypical-v1.html
, 749 dual processors 225 CPUTYP 268 CPUTYP pin 7 , 79 CR0 control register , segments 1043 ADSC# 252 ADSC# pin 6 , 78 ADS# 251 ADS# pin 6 , 44 , 78 , 118 pin 6 , 44 , 78 , 118 Air temperature 17 , 91 Airflow 134 Alignment of words AP pin 6 , 44 , 78 , 118 APCHK pin 6 , 44 , 78 , 118 APCHK# 255 , 342 APIC 76 , 117 , 168 , 204 , 207 bus 209 configuration modes 209 Bypass mode 210 Masked mode
/datasheets/files/intel/design/intarch/techinfo/pentium/hbookix.htm
Intel 02/02/1999 165.94 Kb HTM hbookix.htm
OUTLINE AND DEVICE CHARACTERISTICS 2. PIN ASSIGNMENT AND FUNCTIONS 2.1 Pin Assignment 2.2 Pin Names and Functions 3. OPERATION 3.1 CPU 3.1.1 Reset 3.1.2 AM8/16 AM8/16 pin 3.2 Memory Map 3.3 Dual Clock, Standby Function Clock Pin Output Function 3.3.4 Standby Controller 3.4 Interrupts 3.5.8 Port 7 3.6 Bus Width / Wait Controller, AM8/16 AM8/16 pin 3.6.1 AM8/16 AM8/16 pin
/datasheets/files/toshiba/micon2/900l_1_2/doc/cs44.htm
Toshiba 11/02/1999 4.95 Kb HTM cs44.htm