DS70139A ISO/TS-16949 DS70046 DS70030 CN17/RF4 CN18/RF5 U2RX/CN17/RF4 - Datasheet Archive

 

dsPIC30F3012, dsPIC30F3013 Data Sheet High-Performance Digital Signal Controllers 2004 Microchip Technology Inc. Advance

 

dsPIC30F2011, dsPIC30F2012, dsPIC30F3012, dsPIC30F3013 Data Sheet High-Performance Digital Signal Controllers 2004 Microchip Technology Inc. Advance Information DS70139A DS70139A Note the following details of the code protection feature on Microchip devices: · Microchip products meet the specification contained in their particular Microchip Data Sheet. · Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. · There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. · Microchip is willing to work with the customer who is concerned about the integrity of their code. · Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949 ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70139A-page ii Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 dsPIC30F2011/2012/3012/3013 High Performance Digital Signal Controllers Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046 DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer's Reference Manual (DS70030 DS70030). · 16-bit Compare/PWM output functions: · 3-wire SPITM modules (supports four Frame modes) · I2CTM module supports Multi-Master/Slave mode and 7-bit/10-bit addressing · Up to two addressable UART modules with FIFO buffers High Performance Modified RISC CPU: Analog Features: · · · · · · · · · · · 12-bit Analog-to-Digital Converter (A/D) with: - 100 Ksps conversion rate - Up to 10 input channels - Conversion available during Sleep and Idle · Programmable Low Voltage Detection (PLVD) · Programmable Brown-out Detection and Reset generation Modified Harvard architecture C compiler optimized instruction set architecture Flexible addressing modes 84 base instructions 24-bit wide instructions, 16-bit wide data path Up to 24 Kbytes on-chip Flash program space Up to 2 Kbytes of on-chip data RAM Up to 1 Kbytes of non-volatile data EEPROM 16 x 16-bit working register array Up to 30 MIPs operation: - DC to 40 MHz external clock input - 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x) · Up to 21 interrupt sources: - 8 user selectable priority levels - 3 external interrupt sources - 4 processor trap sources DSP Features: · Dual data fetch · Modulo and Bit-reversed modes · Two 40-bit wide accumulators with optional saturation logic · 17-bit x 17-bit single cycle hardware fractional/ integer multiplier · All DSP instructins are single cycle - Multiply-Accumulate (MAC) operation · Single cycle ±16 shift Peripheral Features: · High current sink/source I/O pins: 25 mA/25 mA · Three 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules · 16-bit Capture input functions 2004 Microchip Technology Inc. Special Microcontroller Features: · Enhanced Flash program memory: - 10,000 erase/write cycle (min.) for industrial temperature range, 100K (typical) · Data EEPROM memory: - 100,000 erase/write cycle (min.) for industrial temperature range, 1M (typical) · Self-reprogrammable under software control · Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) · Flexible Watchdog Timer (WDT) with on-chip low power RC oscillator for reliable operation · Fail-Safe Clock Monitor operation: - Detects clock failure and switches to on-chip low power RC oscillator · Programmable code protection · In-Circuit Serial ProgrammingTM (ICSPTM) · Selectable Power Management modes: - Sleep, Idle and Alternate Clock modes CMOS Technology: · · · · Low power, high speed Flash technology Wide operating voltage range (2.5V to 5.5V) Industrial and Extended temperature ranges Low power consumption Advance Information DS70139A-page 1 dsPIC30F2011/2012/3012/3013 dsPIC30F2011/2012/3012/3013 Sensor Family Input Cap Output Comp/Std PWM A/D 12-bit 100 Ksps I2CTM Timer 16-bit SPITM EEPROM Bytes UART Program Memory dsPIC30F2011 18 12K 4K 1024 ­ 3 2 2 8 ch 1 1 1 dsPIC30F3012 18 24K 8K 2048 1024 3 2 2 8 ch 1 1 1 Bytes Device Instructions SRAM Bytes Pins dsPIC30F2012 28 12K 4K 1024 ­ 3 2 2 10 ch 1 1 1 dsPIC30F3013 28 24K 8K 2048 1024 3 2 2 10 ch 2 1 1 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 AVDD AVSS AN6/SCK1/INT0/OCFA/RB6 EMUD2/AN7/OC2/IC2/RB7 VDD VSS PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4 EMUC2/OC1/IC1/INT1/RD0 dsPIC30F2012 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS AN6/OCFA/RB6 EMUD2/AN7/RB7 AN8/OC1/RB8 AN9/OC2/RB9 CN17/RF4 CN17/RF4 CN18/RF5 CN18/RF5 VDD VSS PGC/EMUC/U1RX/SDI1/SDA/RF2 PGD/EMUD/U1TX/SDO1/SCL/RF3 SCK1/INT0/RF6 EMUC2/IC1/INT1/RD8 dsPIC30F3013 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS AN6/OCFA/RB6 EMUD2/AN7/RB7 AN8/OC1/RB8 AN9/OC2/RB9 U2RX/CN17/RF4 U2RX/CN17/RF4 U2TX/CN18/RF5 U2TX/CN18/RF5 VDD VSS PGC/EMUC/U1RX/SDI1/SDA/RF2 PGD/EMUD/U1TX/SDO1/SCL/RF3 SCK1/INT0/RF6 EMUC2/IC1/INT1/RD8 Pin Diagrams 18-Pin PDIP and SOIC dsPIC30F2011 dsPIC30F3012 MCLR AN0/VREF+/CN2/RB0 AN1/VREF-/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 OSC1/CLKI OSC2/CLKO/RC15 OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 28-Pin PDIP and SOIC MCLR EMUD3/AN0/VREF+/CN2/RB0 EMUC3/AN1/VREF-/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5 VSS OSC1/CLKI OSC2/CLKO/RC15 OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 VDD IC2/INT2/RD9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-Pin SPDIP and SOIC MCLR EMUD3/AN0/VREF+/CN2/RB0 EMUC3/AN1/VREF-/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5 VSS OSC1/CLKI OSC2/CLKO/RC15 OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 VDD IC2/INT2/RD9 Note: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 For descriptions of individual pins, see Section 1.0. DS70139A-page 2 Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Pin Diagrams 44 43 42 41 40 39 38 37 36 35 34 PGD/EMUD/U1TX/SDO1/SCL/RF3 SCK1/INT0/RF6 EMUC2/IC1/INT1/RD8 NC NC NC NC IC2/INT2/RD9 VDD EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 44-Pin QFN 1 2 3 4 5 6 7 8 9 10 11 dsPIC30F3013 33 32 31 30 29 28 27 26 25 24 23 OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKI VSS VSS NC NC AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 NC AN2/SS1/LVDIN/CN4/RB2 EMUD2/AN7/RB7 NC AN6/OCFA/RB6 NC AVSS AVDD MCLR EMUD3/AN0/VREF+/CN2/RB0 EMUC3/AN1/VREF-/CN3/RB1 NC NC 12 13 14 15 16 17 18 19 20 21 22 PGC/EMUC/U1RX/SDI1/SDA/RF2 VSS NC VDD NC NC U2TX/CN18/RF5 U2TX/CN18/RF5 NC U2RX/CN17/RF4 U2RX/CN17/RF4 AN9/OC2/RB9 AN8/OC1/RB8 Note: For descriptions of individual pins, see Section 1.0. 2004 Microchip Technology Inc. Advance Information DS70139A-page 3 dsPIC30F2011/2012/3012/3013 Table of Contents 1.0 Device Overview . 5 2.0 CPU Architecture Overview. 13 3.0 Memory Organization . 23 4.0 Address Generator Units . 37 5.0 Flash Program Memory . 43 6.0 Data EEPROM Memory . 49 7.0 I/O Ports . 53 8.0 Interrupts . 59 9.0 Timer1 Module . 67 10.0 Timer2/3 Module . 71 11.0 Input Capture Module. 77 12.0 Output Compare Module . 81 13.0 SPI Module. 85 14.0 I2C Module . 89 15.0 Universal Asynchronous Receiver Transmitter (UART) Module . 97 16.0 12-bit Analog-to-Digital Converter (A/D) Module . 105 17.0 System Integration . 113 18.0 Instruction Set Summary . 127 19.0 Development Support. 135 20.0 Electrical Characteristics . 141 21.0 Packaging Information. 181 Index . 187 On-Line Support. 193 Systems Information and Upgrade Hot Line . 193 Reader Response . 194 Product Identification System. 195 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A DS30000A is version A of document DS30000 DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: · Microchip's Worldwide Web site; http://www.microchip.com · Your local Microchip sales office (see last page) · The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS70139A-page 4 Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 1.0 DEVICE OVERVIEW Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046 DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer's Reference Manual (DS70030 DS70030). This data sheet contains information specific to the dsPIC30F2011, dsPIC30F2012, dsPIC30F3012 and dsPIC30f3013 Digital Signal Controllers. These devices contain extensive Digital Signal Processor (DSP) functionality within a high performance 16-bit microcontroller (MCU) architecture. The following block diagrams depict the architecture for these devices: · · · · Figure 1-1 illustrates the dsPIC30F2011 Figure 1-2 illustrates the dsPIC30F2012 Figure 1-3 illustrates the dsPIC30F3012 Figure 1-4 illustrates the dsPIC30F3013 Following the block diagrams, Table 1-1 relates the I/O functions to pinout information. 2004 Microchip Technology Inc. Advance Information DS70139A-page 5 dsPIC30F2011/2012/3012/3013 FIGURE 1-1: dsPIC30F2011 BLOCK DIAGRAM Y Data Bus X Data Bus 16 Interrupt Controller PSV & Table Data Access 24 Control Block 8 Data Latch Y Data RAM (512 bytes) Address Latch 16 24 Address Latch 16 16 AN0/VREF+/CN2/RB0 AN1/VREF-/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 AN6/SCK1/INT0/OCFA/RB6 EMUD2/AN7/OC2/IC2/RB7 X RAGU X WAGU Y AGU PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic Data Latch X Data RAM (512 bytes) Address Latch 16 16 24 Program Memory (12 Kbytes) 16 16 16 Data Latch Effective Address PORTB 16 ROM Latch 16 24 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15 OSC2/CLKO/RC15 IR 16 16 16 x 16 W Reg Array Decode PORTC Instruction Decode & Control 16 16 Power-up Timer OSC1/CLKI Timing Generation DSP Engine VDD, VSS AVDD, AVSS Watchdog Timer Low Voltage Detect ALU 16 16 PORTD Input Capture Module Output Compare Module I2CTM Timers 12-bit ADC DS70139A-page 6 EMUC2/OC1/IC1/INT1/RD0 Oscillator Start-up Timer POR/BOR Reset MCLR Divide Unit SPI1 UART1 Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 FIGURE 1-2: dsPIC30F2012 BLOCK DIAGRAM Y Data Bus X Data Bus 16 Interrupt Controller PSV & Table Data Access 24 Control Block 8 16 16 Data Latch Y Data RAM (512 bytes) Address Latch 16 24 Address Latch 16 16 EMUD3/AN0/VREF+/CN2/RB0 EMUC3/AN1/VREF-/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5 AN6/OCFA/RB6 EMUD2/AN7/RB7 AN8/OC1/RB8 AN9/OC2/RB9 X RAGU X WAGU Y AGU PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic Data Latch X Data RAM (512 bytes) Address Latch 16 16 24 Program Memory (12 Kbytes) 16 Data Latch Effective Address 16 PORTB ROM Latch 16 24 IR 16 x 16 W Reg Array Decode Instruction Decode & Control Timing Generation DSP Engine VDD, VSS AVDD, AVSS Divide Unit EMUC2/IC1/INT1/RD8 IC2/INT2/RD9 Oscillator Start-up Timer ALU POR/BOR Reset MCLR PORTC 16 16 Power-up Timer OSC1/CLKI EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15 OSC2/CLKO/RC15 16 16 Watchdog Timer Low Voltage Detect PORTD 16 16 Input Capture Module Output Compare Module I2CTM Timers 12-bit ADC SPI1 UART1 PGC/EMUC/U1RX/SDI1/SDA/RF2 PGD/EMUD/U1TX/SDO1/SCL/RF3 CN17/RF4 CN17/RF4 CN18/RF5 CN18/RF5 SCK1/INT0/RF6 PORTF 2004 Microchip Technology Inc. Advance Information DS70139A-page 7 dsPIC30F2011/2012/3012/3013 FIGURE 1-3: dsPIC30F3012 BLOCK DIAGRAM Y Data Bus X Data Bus 16 Interrupt Controller PSV & Table Data Access 24 Control Block 8 Data Latch Y Data RAM (1 Kbytes) Address Latch 16 24 Address Latch Data EEPROM (1 Kbytes) 16 16 AN0/VREF+/CN2/RB0 AN1/VREF-/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 AN6/SCK1/INT0/OCFA/RB6 EMUD2/AN7PC2/IC2/RB7 X RAGU X WAGU Y AGU PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic Data Latch X Data RAM (1 Kbytes) Address Latch 16 16 24 Program Memory (24 Kbytes) 16 16 16 Effective Address PORTB 16 Data Latch ROM Latch 16 24 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15 OSC2/CLKO/RC15 IR 16 16 16 x 16 W Reg Array Decode PORTC Instruction Decode & Control 16 16 Power-up Timer OSC1/CLKI Timing Generation DSP Engine VDD, VSS AVDD, AVSS Watchdog Timer Low Voltage Detect ALU 16 16 PORTD Input Capture Module Output Compare Module I2CTM Timers 12-bit ADC DS70139A-page 8 EMUC2/OC1/IC1/INT1/RD0 Oscillator Start-up Timer POR/BOR Reset MCLR Divide Unit SPI1 UART1 Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 FIGURE 1-4: dsPIC30F3013 BLOCK DIAGRAM Y Data Bus X Data Bus PSV & Table Data Access 24 Control Block 8 16 16 16 Interrupt Controller 16 24 Address Latch 16 16 EMUD3/AN0/VREF+/CN2/RB0 EMUC3/AN1/VREF-/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5 AN6/OCFA/RB6 EMUD2/AN7/RB7 AN8/OC1/RB8 AN9/OC2/RB9 X RAGU X WAGU Y AGU PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic Data Latch X Data RAM (1 Kbytes) Address Latch 16 16 24 Program Memory (24 Kbytes) 16 Data Latch Y Data RAM (1 Kbytes) Address Latch Data EEPROM (1 Kbytes) Data Latch Effective Address 16 PORTB ROM Latch 16 24 IR 16 16 x 16 W Reg Array Decode Instruction Decode & Control Timing Generation DSP Engine VDD, VSS AVDD, AVSS Divide Unit EMUC2/IC1/INT1/RD8 IC2/INT2/RD9 Oscillator Start-up Timer ALU POR/BOR Reset MCLR PORTC 16 16 Power-up Timer OSC1/CLKI EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15 OSC2/CLKO/RC15 16 Watchdog Timer Low Voltage Detect 16 PORTD 16 Input Capture Module Output Compare Module I2C Timers 12-bit ADC SPI1 UART1, UART2 PGC/EMUC/U1RX/SDI1/SDA/RF2 PGD/EMUD/U1TX/SDO1/SCL/RF3 U2RX/CN17/RF4 U2RX/CN17/RF4 UT2X/CN18/RF5 UT2X/CN18/RF5 SCK1/INT0/RF6 PORTF 2004 Microchip Technology Inc. Advance Information DS70139A-page 9 dsPIC30F2011/2012/3012/3013 Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module's functional requirements may force an override of the data direction of the port pin. TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Type Buffer Type AN0-AN9 I Analog AVDD P P AVSS P P CLKI I ST/CMOS CLKO O - CN0-CN7 I ST Input change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. EMUD EMUC EMUD1 EMUC1 EMUD2 EMUC2 EMUD3 EMUC3 I/O I/O I/O I/O I/O I/O I/O I/O ST ST ST ST ST ST ST ST ICD Primary Communication Channel data input/output pin. ICD Primary Communication Channel clock input/output pin. ICD Secondary Communication Channel data input/output pin. ICD Secondary Communication Channel clock input/output pin. ICD Tertiary Communication Channel data input/output pin. ICD Tertiary Communication Channel clock input/output pin. ICD Quaternary Communication Channel data input/output pin. ICD Quaternary Communication Channel clock input/output pin. IC1-IC2 I ST Capture inputs 1 through 2. INT0 INT1 INT2 I I I ST ST ST External interrupt 0. External interrupt 1. External interrupt 2. LVDIN I Analog MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active low Reset to the device. OC1-OC2 OCFA O I - ST Compare outputs 1 through 2. Compare Fault A input. OSC1 I ST/CMOS OSC2 I/O - Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. PGD PGC I/O I ST ST In-Circuit Serial Programming data input/output pin. In-Circuit Serial Programming clock input pin. RB0-RB9 I/O ST PORTB is a bidirectional I/O port. RC13-RC15 RC13-RC15 I/O ST PORTC is a bidirectional I/O port. RD0, RD8-RD9 I/O ST PORTD is a bidirectional I/O port. Pin Name Description Analog input channels. Positive supply for analog module. Ground reference for analog module. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. Low Voltage Detect Reference Voltage input pin. RF2-RF5 I/O ST PORTF is a bidirectional I/O port. SCK1 SDI1 SDO1 SS1 I/O I O I ST ST - ST Synchronous serial clock input/output for SPI1. SPI1 Data In. SPI1 Data Out. SPI1 Slave Synchronization. Legend: CMOS = CMOS compatible input or output Analog= ST = Schmitt Trigger input with CMOS levelsO= I = Input P = DS70139A-page 10 Analog input Output Power Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type SCL SDA I/O I/O ST ST SOSCO SOSCI O I - ST/CMOS T1CK T2CK I I ST ST Timer1 external clock input. Timer2 external clock input. U1RX U1TX U1ARX U1ATX U2RX U2TX I O I O I O ST - ST - ST - UART1 Receive. UART1 Transmit. UART1 Alternate Receive. UART1 Alternate Transmit. UART2 Receive. UART2 Transmit. VDD P - Positive supply for logic and I/O pins. VSS P - Ground reference for logic and I/O pins. VREF+ I Analog Analog Voltage Reference (High) input. I Analog Analog Voltage Reference (Low) input. Pin Name VREF- Legend: Description Synchronous serial clock input/output for I2C. Synchronous serial data input/output for I2C. 32 kHz low power oscillator crystal output. 32 kHz low power oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. CMOS = CMOS compatible input or output Analog= ST = Schmitt Trigger input with CMOS levelsO= I = Input P = 2004 Microchip Technology Inc. Analog input Output Power Advance Information DS70139A-page 11 dsPIC30F2011/2012/3012/3013 NOTES: DS70139A-page 12 Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.0 CPU ARCHITECTURE OVERVIEW Two ways to access data in program memory are: Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046 DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer's Reference Manual (DS70030 DS70030). This section is an overview of the CPU architecture of the dsPIC30F. The core has a 24-bit instruction word. The Program Counter (PC) is 23-bits wide with the Least Significant (LS) bit always clear (see Section 3.1). The Most Significant (MS) bit is ignored during normal program execution, except for certain specialized instructions. Thus, the PC can address up to 4M instruction words of user program space. An instruction pre-fetch mechanism helps maintain throughput. Program loop constructs, free from loop count management overhead, are supported using the DO and REPEAT instructions, both of which are interruptible at any point. 2.1 Core Overview The working register array consists of 16 x 16-bit registers, each of which can act as data, address or offset registers. One working register (W15) operates as a software stack pointer for interrupts and calls. The data space is 64 Kbytes (32K words) and is split into two blocks, referred to as X and Y data memory. Each block has its own independent Address Generation Unit (AGU). Most instructions operate solely through the X memory, AGU, which provides the appearance of a single unified data space. The Multiply-Accumulate (MAC) class of dual source DSP instructions operate through both the X and Y AGUs, splitting the data address space into two parts (see Section 3.2). The X and Y data space boundary is device specific and cannot be altered by the user. Each data word consists of 2 bytes, and most instructions can address data either as words or bytes. 2004 Microchip Technology Inc. · The upper 32 Kbytes of data space memory can be mapped into the lower half (user space) of program space at any 16K program word boundary, defined by the 8-bit Program Space Visibility Page (PSVPAG) register. Thus any instruction can access program space as if it were data space, with a limitation that the access requires an additional cycle. Only the lower 16 bits of each instruction word can be accessed using this method. · Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions. Table read and write instructions can be used to access all 24 bits of an instruction word. Overhead-free circular buffers (modulo addressing) are supported in both X and Y address spaces. This is primarily intended to remove the loop overhead for DSP algorithms. The X AGU also supports bit-reversed addressing on destination effective addresses to greatly simplify input or output data reordering for radix-2 FFT algorithms. Refer to Section 4.0 for details on modulo and bit-reversed addressing. The core supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct, Register Indirect, Register Offset and Literal Offset Addressing modes. Instructions are associated with predefined Addressing modes, depending upon their functional requirements. For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, 3-operand instructions are supported, allowing C = A+B operations to be executed in a single cycle. A DSP engine has been included to significantly enhance the core arithmetic capability and throughput. It features a high speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. Data in the accumulator or any working register can be shifted up to 15 bits right, or 16 bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. The MAC class of instructions can concurrently fetch two data operands from memory while multiplying two W registers. To enable this concurrent fetching of data operands, the data space has been split for these instructions and linear for all others. This has been achieved in a transparent and flexible manner, by dedicating certain working registers to each address space for the MAC class of instructions. Advance Information DS70139A-page 13 dsPIC30F2011/2012/3012/3013 The core does not support a multi-stage instruction pipeline. However, a single stage instruction pre-fetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions. The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors. The exceptions consist of up to 8 traps (of which 4 are reserved) and 54 interrupts. Each interrupt is prioritized based on a user assigned priority between 1 and 7 (1 being the lowest priority and 7 being the highest), in conjunction with a predetermined `natural order'. Traps have fixed priorities ranging from 8 to 15. 2.2 Programmer's Model The programmer's model is shown in Figure 2-1 and consists of 16 x 16-bit working registers (W0 through W15), 2 x 40-bit accumulators (AccA and AccB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT) and Program Counter (PC). The working registers can act as data, address or offset registers. All registers are memory mapped. W0 acts as the W register for file register addressing. Some of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The shadow register is used as a temporary holding register and can transfer its contents to or from its host register upon the occurrence of an event. None of the shadow registers are accessible directly. The following rules apply for transfer of registers into and out of shadows. · PUSH.S and POP.S W0, W1, W2, W3, SR (DC, N, OV, Z and C bits only) are transferred. · DO instruction DOSTART, DOEND, DCOUNT shadows are pushed on loop start, and popped on loop end. 2.2.1 SOFTWARE STACK POINTER/ FRAME POINTER The dsPIC® devices contain a software stack. W15 is the dedicated software Stack Pointer (SP), and will be automatically modified by exception processing and subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all other W registers. This simplifies the reading, writing and manipulation of the stack pointer (e.g., creating stack frames). Note: In order to protect against misaligned stack accesses, W15 is always clear. W15 is initialized to 0x0800 during a Reset. The user may reprogram the SP during initialization to any location within data space. W14 has been dedicated as a stack frame pointer as defined by the LNK and ULNK instructions. However, W14 can be referenced by any instruction in the same manner as all other W registers. 2.2.2 STATUS REGISTER The dsPIC core has a 16-bit STATUS register (SR), the LS Byte of which is referred to as the SR Low byte (SRL) and the MS Byte as the SR High byte (SRH). See Figure 2-1 for SR layout. SRL contains all the MCU ALU operation status flags (including the Z bit), as well as the CPU Interrupt Priority Level status bits, IPL and the Repeat Active status bit, RA. During exception processing, SRL is concatenated with the MS Byte of the PC to form a complete word value which is then stacked. The upper byte of the STATUS register contains the DSP Adder/Subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit. 2.2.3 PROGRAM COUNTER The program counter is 23-bits wide; bit 0 is always clear. Therefore, the PC can address up to 4M instruction words. When a byte operation is performed on a working register, only the Least Significant Byte of the target register is affected. However, a benefit of memory mapped working registers is that both the Least and Most Significant Bytes can be manipulated through byte wide data memory space accesses. DS70139A-page 14 Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 FIGURE 2-1: PROGRAMMER'S MODEL D15 D0 W0/WREG PUSH.S Shadow W1 DO Shadow W2 W3 Legend W4 DSP Operand Registers W5 W6 W7 Working Registers W8 W9 DSP Address Registers W10 W11 W12/DSP W12/DSP Offset W13/DSP W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer Stack Pointer Limit Register SPLIM AD39 AD15 AD31 AD0 AccA DSP Accumulators AccB PC22 PC0 Program Counter 0 0 7 TABPAG TBLPAG 7 Data Table Page Address 0 PSVPAG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 DCOUNT DO Loop Counter 22 0 DOSTART DO Loop Start Address DOEND DO Loop End Address 22 15 0 Core Configuration Register CORCON OA OB SA SB OAB SAB DA SRH 2004 Microchip Technology Inc. DC IPL2 IPL1 IPL0 RA N OV Z C Status Register SRL Advance Information DS70139A-page 15 dsPIC30F2011/2012/3012/3013 2.3 Divide Support The dsPIC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 1. 2. 3. 4. 5. DIVF - 16/16 signed fractional divide DIV.sd - 32/16 signed divide DIV.ud - 32/16 unsigned divide DIV.sw - 16/16 signed divide DIV.uw - 16/16 unsigned divide The divide instructions must be executed within a REPEAT loop. Any other form of execution (e.g., a series of discrete divide instructions) will not function correctly because the instruction flow depends on RCOUNT. The divide instruction does not automatically set up the RCOUNT value and it must, therefore, be explicitly and correctly specified in the REPEAT instruction as shown in Table 2-1 (REPEAT will execute the target instruction {operand value+1} times). The REPEAT loop count must be setup for 18 iterations of the DIV/ DIVF instruction. Thus, a complete divide operation requires 19 cycles. The 16/16 divides are similar to the 32/16 (same number of iterations), but the dividend is either zero-extended or sign-extended during the first iteration. TABLE 2-1: The divide flow is interruptible. However, the user needs to save the context as appropriate. DIVIDE INSTRUCTIONS Instruction DIVF Note: Function Signed fractional divide: Wm/Wn W0; Rem W1 DIV.sd Signed divide: (Wm+1:Wm)/Wn W0; Rem W1 DIV.sw or DIV.s Signed divide: Wm/Wn W0; Rem W1 DIV.ud Unsigned divide: (Wm+1:Wm)/Wn W0; Rem W1 DIV.uw or DIV.u Unsigned divide: Wm/Wn W0; Rem W1 DS70139A-page 16 Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.4 DSP Engine The DSP engine consists of a high speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/ subtracter (with two target accumulators, round and saturation logic). The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations, which require no additional data. These instructions are ADD, SUB and NEG. The dsPIC30F is a single-cycle instruction flow architecture, threfore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources may be used concurrently by the same instruction (e.g., ED, EDAC). TABLE 2-2: The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below: 1. 2. 3. 4. 5. 6. Fractional or integer DSP multiply (IF). Signed or unsigned DSP multiply (US). Conventional or convergent rounding (RND). Automatic saturation on/off for AccA (SATA). Automatic saturation on/off for AccB (SATB). Automatic saturation on/off for writes to data memory (SATDW). Accumulator Saturation mode selection (ACCSAT). 7. Note: For CORCON layout, see Table 3-3. A block diagram of the DSP engine is shown in Figure 2-2. DSP INSTRUCTION SUMMARY Instruction CLR ED Algebraic Operation A=0 ACC WB? Yes A = (x ­ y)2 No 2 No EDAC A = A + (x ­ y) MAC A = A + (x * y) MAC A = A + x2 No No change in A Yes A=x*y No A=­x*y No A=A­x*y Yes MOVSAC MPY MPY.N MSC 2004 Microchip Technology Inc. Advance Information Yes DS70139A-page 17 dsPIC30F2011/2012/3012/3013 FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 S a 40 Round t 16 u Logic r a t e 40-bit Accumulator A 40-bit Accumulator B Carry/Borrow Out Carry/Borrow In Saturate Adder Negate 40 40 40 Barrel Shifter X Data Bus 16 40 Y Data Bus Sign-Extend 32 16 Zero Backfill 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array DS70139A-page 18 Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.4.1 MULTIPLIER 2.4.2.1 The 17 x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17 x 17-bit multiplier/scaler is a 33-bit value which is sign-extended to 40 bits. Integer data is inherently represented as a signed two's complement value, where the MSB is defined as a sign bit. Generally speaking, the range of an N-bit two's complement integer is -2N-1 to 2N-1 ­ 1. For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including `0'. For a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,645 (0x7FFF FFFF). When the multiplier is configured for fractional multiplication, the data is represented as a two's complement fraction, where the MSB is defined as a sign bit and the radix point is implied to lie just after the sign bit (QX format). The range of an N-bit two's complement fraction with this implied radix point is -1.0 to (1 ­ 21-N). For a 16-bit fraction, the Q15 data range is -1.0 (0x8000) to 0.999969482 (0x7FFF) including `0' and has a precision of 3.01518x10-5. In Fractional mode, the 16x16 multiply operation generates a 1.31 product which has a precision of 4.65661 x 10-10. The same multiplier is used to support the MCU multiply instructions which include integer 16-bit signed, unsigned and mixed sign multiplies. The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true, or complement data into the other input. In the case of addition, the carry/borrow input is active high and the other input is true data (not complemented), whereas in the case of subtraction, the carry/borrow input is active low and the other input is complemented. The adder/subtracter generates overflow status bits SA/SB and OA/OB, which are latched and reflected in the STATUS register: · Overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed. · Overflow into guard bits 32 through 39: this is a recoverable overflow. This bit is set whenever all the guard bits bits are not identical to each other. The adder has an additional saturation block which controls accumulator data saturation, if selected. It uses the result of the adder, the overflow status bits described above, and the SATA/B (CORCON) and ACCSAT (CORCON) mode control bits to determine when and to what value to saturate. Six Status register bits have been provided to support saturation and overflow; they are: 1. 2. 3. The MUL instruction may be directed to use byte or word sized operands. Byte operands will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the W array. 2.4.2 DATA ACCUMULATORS AND ADDER/SUBTRACTER The data accumulator consists of a 40-bit adder/ subtracter with automatic sign extension logic. It can select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation. 2004 Microchip Technology Inc. Adder/Subtracter, Overflow and Saturation 4. 5. 6. OA: AccA overflowed into guard bits OB: AccB overflowed into guard bits SA: AccA saturated (bit 31 overflow and saturation) or AccA overflowed into guard bits and saturated (bit 39 overflow and saturation) SB: AccB saturated (bit 31 overflow and saturation) or AccB overflowed into guard bits and saturated (bit 39 overflow and saturation) OAB: Logical OR of OA and OB SAB: Logical OR of SA and SB The OA and OB bits are modified each time data passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding overflow trap flag enable bit (OVATEN, OVBTEN) in the INTCON1 register (refer to Section 8.0) is set. This allows the user to take immediate action, for example, to correct system gain. Advance Information DS70139A-page 19 dsPIC30F2011/2012/3012/3013 The SA and SB bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate an arithmetic warning trap when saturation is disabled. The overflow and saturation status bits can optionally be viewed in the STATUS register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). This allows programmers to check one bit in the STATUS register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. This would be useful for complex number arithmetic which typically uses both the accumulators. The device supports three saturation and overflow modes: 1. 2. 3. Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF), or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. This is referred to as `super saturation' and provides protection against erroneous data, or unexpected algorithm problems (e.g., gain calculations). Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF), or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. When this Saturation mode is in effect, the guard bits are not used (so the OA, OB or OAB bits are never set). Bit 39 Catastrophic Overflow: The bit 39 overflow status bit from the adder is used to set the SA or SB bit which remain set until cleared by the user. No saturation operation is performed and the accumulator is allowed to overflow (destroying its sign). If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. DS70139A-page 20 2.4.2.2 Accumulator `Write Back' The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction into data space memory. The write is performed across the X bus into combined X and Y address space. The following Addressing modes are supported: 1. 2. W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction. [W13]+=2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write). 2.4.2.3 Round Logic The round logic is a combinational block which performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16bit, 1.15 data value which is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the LS Word is simply discarded. Conventional rounding takes bit 15 of the accumulator, zero-extends it and adds it to the ACCxH word (bits 16 through 31 of the accumulator). If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented. If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding operations, the value will tend to be biased slightly positive. Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. If this is the case, the LS bit (bit 16 of the accumulator) of ACCxH is examined. If it is `1', ACCxH is incremented. If it is `0', ACCxH is not modified. Assuming that bit 16 is effectively random in nature, this scheme will remove any rounding bias that may accumulate. The SAC and SAC.R instructions store either a truncated (SAC) or rounded (SAC.R) version of the contents of the target accumulator to data memory via the X bus (subject to data saturation, see Section 2.4.2.4). Note that for the MAC class of instructions, the accumulator write back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.4.2.4 Data Space Write Saturation 2.4.3 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space may also be saturated but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory. The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either of the two DSP accumulators, or the X bus (to support multi-bit shifts of register or memory data). If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly, For input data greater than 0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The MS bit of the source (bit 39) is used to determine the sign of the operand being tested. The barrel shifter is 40-bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 to 31 for right shifts, and bit positions 0 to 16 for left shifts. The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value will shift the operand right. A negative value will shift the operand left. A value of `0' will not modify the operand. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. 2004 Microchip Technology Inc. Advance Information DS70139A-page 21 dsPIC30F2011/2012/3012/3013 NOTES: DS70139A-page 22 Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 3.0 MEMORY ORGANIZATION Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046 DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer's Reference Manual (DS70030 DS70030). 3.1 Program Address Space The program address space is 4M instruction words. The program space memory map for the dsPI30F2011/ 2012 is shown in Figure 3-1. The program space memory map for the dsPI30F3012/3013 is shown in Figure 3-2. 2004 Microchip Technology Inc. Program memory is addressable by a 24-bit value from either the 23-bit PC, table instruction Effective Address (EA), or data space EA, when program space is mapped into data space as defined by Table 3-1. Note that the program space address is incremented by two between successive program words in order to provide compatibility with data space addressing. User program space access is restricted to the lower 4M instruction word address range (0x000000 to 0x7FFFFE) for all accesses other than TBLRD/TBLWT, which use TBLPAG to determine user or configuration space access. In Table 3-1, Program Space Address Construction, bit 23 allows access to the Device ID, the User ID and the configuration bits. Otherwise, bit 23 is always clear. Advance Information DS70139A-page 23 dsPIC30F2011/2012/3012/3013 FIGURE 3-1: dsPIC30F2011/2012 PROGRAM SPACE MEMORY MAP Reset - GOTO Instruction Reset - Target Address FIGURE 3-2: dsPIC30F3012/3013 PROGRAM SPACE MEMORY MAP Reset - GOTO Instruction Reset - Target Address 000000 000002 000004 Interrupt Vector Table Interrupt Vector Table Vector Tables Reserved Vector Tables 00007E 00007E 000080 000084 Reserved 0000FE 0000FE 000100 001FFE 001FFE 002000 User Flash Program Memory (8K instructions) Reserved (Read `0's) Reserved (Read `0's) Data EEPROM (1 Kbyte) 7FFFFE 800000 F7FFFE F80000 F80000 F8000E F8000E F80010 F80010 Configuration Memory Space Configuration Memory Space 8005BE 8005BE 8005C0 8005C0 Reserved Reserved DEVID (2) DS70139A-page 24 003FFE 003FFE 004000 7FFBFE 7FFC00 7FFC00 Reserved 8005FE 8005FE 800600 Device Configuration Registers 000084 0000FE 0000FE 000100 7FFFFE 800000 Reserved UNITID (32 instr.) 00007E 00007E 000080 Alternate Vector Table User Memory Space User Memory Space Alternate Vector Table User Flash Program Memory (4K instructions) 000000 000002 000004 UNITID (32 instr.) 8005BE 8005BE 8005C0 8005C0 8005FE 8005FE 800600 Reserved Device Configuration Registers F7FFFE F80000 F80000 F8000E F8000E F80010 F80010 Reserved FEFFFE FF0000 FF0000 FFFFFE Advance Information DEVID (2) FEFFFE FF0000 FF0000 FFFFFE 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Program Space Address Access Space Access Type Instruction Access User TBLRD/TBLWT User (TBLPAG = 0) TBLPAG Data EA TBLRD/TBLWT Configuration (TBLPAG = 1) TBLPAG Data EA Program Space Visibility User FIGURE 3-3: PC 0 0 PSVPAG 0 Data EA DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION 23 bits Using Program Counter Program Counter 0 Select Using Program Space Visibility 0 0 1 EA PSVPAG Reg 8 bits 15 bits EA Using Table Instruction 1/0 User/ Configuration Space Select Note: TBLPAG Reg 8 bits 16 bits 24-bit EA Byte Select Program space visibility cannot be used to access bits of a word in program memory. 2004 Microchip Technology Inc. Advance Information DS70139A-page 25 dsPIC30F2011/2012/3012/3013 3.1.1 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS A set of table instructions are provided to move byte or word sized data to and from program space. 1. This architecture fetches 24-bit wide program memory. Consequently, instructions are always aligned. However, as the architecture is modified Harvard, data can also be present in program space. There are two methods by which program space can be accessed: via special table instructions, or through the remapping of a 16K word program space page into the upper half of data space (see Section 3.1.2). The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the LS Word of any address within program space, without going through data space. The TBLRDH and TBLWTH instructions are the only method whereby the upper 8 bits of a program space word can be accessed as data. 2. 3. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit word wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the LS Data Word, and TBLRDH and TBLWTH access the space which contains the MS Data Byte. 4. TBLRDL: Table Read Low Word: Read the LS Word of the program address; P maps to D. Byte: Read one of the LS Bytes of the program address; P maps to the destination byte when byte select = 0; P maps to the destination byte when byte select = 1. TBLWTL: Table Write Low (refer to Section 5.0 for details on Flash Programming) TBLRDH: Table Read High Word: Read the MS Word of the program address; P maps to D; D will always be = 0. Byte: Read one of the MS Bytes of the program address; P maps to the destination byte when byte select = 0; The destination byte will always be = 0 when byte select = 1. TBLWTH: Table Write High (refer to Section 5.0 for details on Flash Programming) Figure 3-3 shows how the EA is created for table operations and data space accesses (PSV = 1). Here, P refers to a program space word, whereas D refers to a data space word. FIGURE 3-4: PROGRAM DATA TABLE ACCESS (LS WORD) PC Address 0x000000 0x000002 0x000004 0x000006 Program Memory `Phantom' Byte (read as `0') DS70139A-page 26 23 8 16 0 00000000 00000000 00000000 00000000 TBLRDL.B (Wn = 0) TBLRDL.W TBLRDL.B (Wn = 1) Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 FIGURE 3-5: PROGRAM DATA TABLE ACCESS (MS BYTE) TBLRDH.W PC Address 0x000000 0x000002 0x000004 0x000006 23 16 8 0 00000000 00000000 00000000 00000000 TBLRDH.B (Wn = 0) Program Memory `Phantom' Byte (read as `0') 3.1.2 TBLRDH.B (Wn = 1) DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page. This provides transparent access of stored constant data from X data space without the need to use special instructions (i.e., TBLRDL/H, TBLWTL/H instructions). Program space access through the data space occurs if the MS bit of the data space EA is set and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON). The functions of CORCON are discussed in Section 2.4, DSP Engine. Data accesses to this area add an additional cycle to the instruction being executed, since two program memory fetches are required. Note that the upper half of addressable data space is always part of the X data space. Therefore, when a DSP operation uses program space mapping to access this memory region, Y data space should typically contain state (variable) data for DSP operations, whereas X data space should typically contain coefficient (constant) data. Although each data space address, 0x8000 and higher, maps directly into a corresponding program memory address (see Figure 3-6), only the lower 16 bits of the 24-bit program word are used to contain the data. The upper 8 bits should be programmed to force an illegal instruction to maintain machine robustness. Refer to the Programmer's Reference Manual (DS70030 DS70030) for details on instruction encoding. 2004 Microchip Technology Inc. Note that by incrementing the PC by 2 for each program memory word, the LS 15 bits of data space addresses directly map to the LS 15 bits in the corresponding program space addresses. The remaining bits are provided by the Program Space Visibility Page register, PSVPAG, as shown in Figure 3-6. Note: PSV access is temporarily disabled during table reads/writes. For instructions that use PSV which are executed outside a REPEAT loop: · The following instructions will require one instruction cycle in addition to the specified execution time: - MAC class of instructions with data operand pre-fetch - MOV instructions - MOV.D instructions · All other instructions will require two instruction cycles in addition to the specified execution time of the instruction. For instructions that use PSV which are executed inside a REPEAT loop: · The following instances will require two instruction cycles in addition to the specified execution time of the instruction: - Execution in the first iteration - Execution in the last iteration - Execution prior to exiting the loop due to an interrupt - Execution upon re-entering the loop after an interrupt is serviced · Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle. Advance Information DS70139A-page 27 dsPIC30F2011/2012/3012/3013 FIGURE 3-6: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Data Space Program Space 0x0000 EA = 0 PSVPAG(1) 0x00 8 15 Data 16 Space 15 EA EA = 1 0x000000 0x8000 15 Address Concatenation 23 23 15 0 0x001200 Upper Half of Data Space is Mapped into Program Space 0x001FFF 0xFFFF Data Read BSET MOV MOV MOV Note: CORCON,#2 ; Set PSV bit #0x0, W0 ; Set PSVPAG register W0, PSVPAG 0x9200, W0 ; Access program memory location ; using a data space access PSVPAG is an 8-bit register, containing bits of the program space address. DS70139A-page 28 Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 3.2 Data Address Space The core has two data spaces. The data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. 3.2.1 DATA SPACE MEMORY MAP The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses. FIGURE 3-7: When executing any instruction other than one of the MAC class of instructions, the X block consists of the 64Kbyte data address space (including all Y addresses). When executing one of the MAC class of instructions, the X block consists of the 64-Kbyte data address space excluding the Y address block (for data reads only). In other words, all other instructions regard the entire data memory as one composite address space. The MAC class instructions extract the Y address space from data space and address it using EAs sourced from W10 and W11. The remaining X data space is addressed using W8 and W9. Both address spaces are concurrently accessed only with the MAC class instructions. The data space memory map for the dsPIC30F2011 and dsPIC30F2012 is shown in Figure 3-7. The data space memory map for the dsPIC30F3012 and dsPIC30F3013 is shown in Figure 3-8. dsPIC30F2011/2012 DATA SPACE MEMORY MAP MS Byte Address MSB 2 Kbyte SFR Space 1 Kbyte SRAM Space LS Byte Address 16 bits LSB 0x0000 0x0001 SFR Space 0x07FF 0x0801 0x09FF 0x0A01 0x07FE 0x0800 X Data RAM (X) Y Data RAM (Y) 0x09FE 0x0A00 0x0BFF 0x0C01 0x0BFE 0x0C00 0x1FFF 0x1FFE 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFE 0xFFFF 2004 Microchip Technology Inc. 8 Kbyte Near Data Space Advance Information DS70139A-page 29 dsPIC30F2011/2012/3012/3013 FIGURE 3-8: dsPIC30F3012/3013 DATA SPACE MEMORY MAP MS Byte Address MSB 2 Kbyte SFR Space 2 Kbyte SRAM Space LS Byte Address 16 bits LSB 0x0000 0x0001 SFR Space 0x07FE 0x0800 0x07FF 0x0801 0x0BFF 0x0C01 X Data RAM (X) 8 Kbyte Near Data Space 0x0BFE 0x0C00 Y Data RAM (Y) 0x0FFF 0x1001 0x0FFE 0x1000 0x1FFF 0x1FFE 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70139A-page 30 0xFFFE Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE SFR SPACE X SPACE FIGURE 3-9: Y SPACE UNUSED X SPACE (Y SPACE) X SPACE UNUSED UNUSED Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W 2004 Microchip Technology Inc. MAC Class Ops (Read) Indirect EA using W8, W9 Advance Information Indirect EA using W10, W11 DS70139A-page 31 dsPIC30F2011/2012/3012/3013 3.2.2 DATA SPACES 3.2.3 The X data space is used by all instructions and supports all Addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space. It is also the X address space data path for the dual operand read instructions (MAC class). The X write data bus is the only write path to data space for all instructions. The X data space also supports modulo addressing for all instructions, subject to Addressing mode restrictions. Bit-reversed addressing is only supported for writes to X data space. The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths. No writes occur across the Y bus. This class of instructions dedicates two W register pointers, W10 and W11, to always address Y data space, independent of X data space, whereas W8 and W9 always address X data space. Note that during accumulator write back, the data address space is considered a combination of X and Y data spaces, so the write occurs across the X bus. Consequently, the write can be to any address in the entire data space. The Y data space can only be used for the data prefetch operation associated with the MAC class of instructions. It also supports modulo addressing for automated circular buffers. Of course, all other instructions can access the Y data address space through the X data path as part of the composite linear space. The boundary between the X and Y data spaces is defined as shown in Figure 3-8 and is not user programmable. Should an EA point to data outside its own assigned address space, or to a location outside physical memory, an all zero word/byte will be returned. For example, although Y address space is visible by all non-MAC instructions using any Addressing mode, an attempt by a MAC instruction to fetch data from that space using W8 or W9 (X space pointers) will return 0x0000. TABLE 3-2: EFFECT OF INVALID MEMORY ACCESSES Attempted Operation Data Returned DATA SPACE WIDTH The core data width is 16 bits. All internal registers are organized as 16-bit wide words. Data space memory is organized in byte addressable, 16-bit wide blocks. 3.2.4 DATA ALIGNMENT To help maintain backward compatibility with PICmicro® devices and improve data space memory usage efficiency, the dsPIC30F instruction set supports both word and byte operations. Data is aligned in data memory and registers as words, but all data space EAs resolve to bytes. Data byte reads will read the complete word which contains the byte, using the LS bit of any EA to determine which byte to select. The selected byte is placed onto the LS Byte of the X data path (no byte accesses are possible from the Y data path as the MAC class of instruction can only fetch words). That is, data memory and registers are organized as two parallel byte wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address. As a consequence of this byte accessibility, all effective address calculations (including those generated by the DSP operations which are restricted to word sized data) are internally scaled to step through word aligned memory. For example, the core would recognize that Post-Modified Register Indirect Addressing mode [Ws+] will result in a value of Ws+1 for byte operations and Ws+2 for word operations. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. Should a misaligned read or write be attempted, an address error trap will be generated. If the error occurred on a read, the instruction underway is completed, whereas if it occurred on a write, the instruction will be executed but the write will not occur. In either case, a trap will then be executed, allowing the system and/or user to examine the machine state prior to execution of the address fault. FIGURE 3-10: 15 DATA ALIGNMENT MS Byte 87 LS Byte 0 0x0000 W8 or W9 used to access Y data space in a MAC instruction 0x0000 W10 or W11 used to access X data space in a MAC instruction 0001 Byte1 Byte 0 0000 0003 Byte3 Byte 2 0002 0005 EA = an unimplemented address Byte5 Byte 4 0004 0x0000 All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes or 32K words. DS70139A-page 32 Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 All byte loads into any W register are loaded into the LS Byte. The MSB is not modified. A sign-extend (SE) instruction is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions, including the DSP instructions, operate only on words. 3.2.5 NEAR DATA SPACE An 8-Kbyte `near' data space is reserved in X address memory space between 0x0000 and 0x1FFF, which is directly addressable via a 13-bit absolute address field within all memory direct instructions. The remaining X address space and all of the Y address space is addressable indirectly. Additionally, the whole of X data space is addressable using MOV instructions, which support memory direct addressing with a 16-bit address field. 3.2.6 SOFTWARE STACK The dsPIC devices contain a software stack. W15 is used as the stack pointer. FIGURE 3-11: Stack Grows Towards Higher Address 0x0000 The stack pointer always points to the first available free word and grows from lower addresses towards higher addresses. It pre-decrements for stack pops and post-increments for stack pushes as shown in Figure 3-11. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. Note: A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. There is a Stack Pointer Limit register (SPLIM) associated with the stack pointer. SPLIM is uninitialized at Reset. As is the case for the stack pointer, SPLIM is forced to `0' because all stack operations must be word aligned. Whenever an effective address (EA) is generated using W15 as a source or destination pointer, the address thus generated is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a Stack Error Trap will not occur. The Stack Error Trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a Stack Error Trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value, 0x1FFE. Similarly, a stack pointer underflow (stack error) trap is generated when the stack pointer address is found to CALL STACK FRAME 15 0 PC W15 (before CALL) 000000000 PC W15 (after CALL) POP : [-W15] PUSH : [W15+] 2004 Microchip Technology Inc. Advance Information DS70139A-page 33 DS70139A-page 34 Advance Information 0024 0026 0028 002A 002C 002E 0030 ACCAH ACCAU ACCBL ACCBH ACCBU PCL PCH Legend: - Bit 14 - OA - OB - - - - - - - Bit 15 u = uninitialized bit 0042 0022 ACCAL SR 0020 SPLIM 0040 001E W15 003E 001C W14 DOENDH 001A W13 DOENDL 0018 W12 003C 0016 W11 DOSTARTH 0014 W10 003A 0012 W9 DOSTARTL 0010 W8 0038 000E W7 DCOUNT 000C W6 0036 000A W5 RCOUNT 0008 W4 0032 0006 W3 0034 0004 W2 PSVPAG 0002 TBLPAG 0000 W0 W1 SFR Name Bit 12 Bit 11 SA - - - - - SB - - - - - OAB - - - - - Sign-Extension (ACCB) SAB - - - - - Bit 10 Sign-Extension (ACCA) Bit 13 CORE REGISTER MAP Address (Home) TABLE 3-3: DA - - - - - DCOUNT RCOUNT - - - PCL ACCBH ACCBL ACCAH ACCAL SPLIM W15 W14 W13 W12 W11 W10 W9 W8 W7 W6 W5 W4 W3 W2 W1 DC - DOENDL - IPL2 - - - Bit 7 W0/WREG Bit 8 DOSTARTL Bit 9 IPL1 Bit 6 IPL0 Bit 5 Bit 3 RA N DOENDH DOSTARTH PSVPAG TBLPAG PCH ACCBU ACCAU Bit 4 OV Bit 2 Z Bit 1 C 0 0 Bit 0 0000 0000 0000 0000 0000 0000 0uuu uuuu uuuu uuuu uuuu uuu0 0000 0000 0uuu uuuu uuuu uuuu uuuu uuu0 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Reset State dsPIC30F2011/2012/3012/3013 2004 Microchip Technology Inc. 2004 Microchip Technology Inc. 004E 0050 0052 YMODSRT YMODEND XBREV DISICNT - BREN - YMODEN - Bit 14 US - - Bit 12 - Bit 13 EDT Bit 11 DL1 Bit 9 BWM DL2 Bit 10 YE YS XE XS DL0 Bit 8 Bit 4 SATDW ACCSAT Bit 5 YWM SATB Bit 6 DISICNT XB SATA Bit 7 Note: Refer to dsPIC30F Family Reference Manual (DS70046 DS70046) for descriptions of register bit fields. u = uninitialized bit 004C XMODEND Legend: 0048 004A XMODSRT XMODEN - 0044 0046 CORCON Bit 15 CORE REGISTER MAP (CONTINUED) Address (Home) MODCON SFR Name TABLE 3-3: IPL3 Bit 3 RND Bit 1 XWM PSV Bit 2 1 0 1 0 IF Bit 0 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu1 uuuu uuuu uuuu uuu0 uuuu uuuu uuuu uuu1 uuuu uuuu uuuu uuu0 0000 0000 0000 0000 0000 0000 0010 0000 Reset State dsPIC30F2011/2012/3012/3013 Advance Information DS70139A-page 35 dsPIC30F2011/2012/3012/3013 NOTES: DS70139A-page 36 Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4.0 ADDRESS GENERATOR UNITS Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046 DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer's Reference Manual (DS70030 DS70030). The dsPIC core contains two independent address generator units: the X AGU and Y AGU. The Y AGU supports word sized data reads for the DSP MAC class of instructions only. The dsPIC AGUs support three types of data addressing: · Linear Addressing · Modulo (Circular) Addressing · Bit-Reversed Addressing FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). Most file register instructions employ a working register W0, which is denoted as WREG in these instructions. The destination is typically either the same file register, or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space during file register operation. 4.1.2 MCU INSTRUCTIONS The three-operand MCU instructions are of the form: Operand 3 = Operand 1 Operand 2 Linear and Modulo Data Addressing modes can be applied to data space or program space. Bit-reversed addressing is only applicable to data space addresses. 4.1 4.1.1 Instruction Addressing Modes The addressing modes in Table 4-1 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions are somewhat different from those in the other instruction types. where Operand 1 is always a working register (i.e., the addressing mode can only be register direct), which is referred to as Wb. Operand 2 can be a W register, fetched from data memory, or a 5-bit literal. The result location can be either a W register or an address location. The following addressing modes are supported by MCU instructions: · · · · · Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified 5-bit or 10-bit Literal Note: TABLE 4-1: Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes. FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the File register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the EA. Register Indirect Post-modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset 2004 Microchip Technology Inc. The sum of Wn and a literal forms the EA. Advance Information DS70139A-page 37 dsPIC30F2011/2012/3012/3013 4.1.3 MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instructions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode. Note: For the MOV instructions, the addressing mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (register offset) field is shared between both source and destination (but typically only used by one). In summary, the following addressing modes are supported by move and accumulator instructions: · · · · · · · · Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-bit Literal 16-bit Literal Note: 4.1.4 Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes. MAC INSTRUCTIONS The dual source operand DSP instructions (CLR, ED, EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred to as MAC instructions, utilize a simplified set of addressing modes to allow the user to effectively manipulate the data pointers through register indirect tables. The 2 source operand pre-fetch registers must be a member of the set {W8, W9, W10, W11}. For data reads, W8 and W9 will always be directed to the X RAGU and W10 and W11 will always be directed to the Y AGU. The effective addresses generated (before and after modification) must, therefore, be valid addresses within X data space for W8 and W9 and Y data space for W10 and W11. Note: In summary, the following addressing modes are supported by the MAC class of instructions: · · · · · Register Indirect Register Indirect Post-modified by 2 Register Indirect Post-modified by 4 Register Indirect Post-modified by 6 Register Indirect with Register Offset (Indexed) 4.1.5 OTHER INSTRUCTIONS Besides the various addressing modes outlined above, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. 4.2 Modulo Addressing Modulo addressing is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms. Modulo addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into program space) and Y data spaces. Modulo addressing can operate on any W register pointer. However, it is not advisable to use W14 or W15 for modulo addressing since these two registers are used as the stack frame pointer and stack pointer, respectively. In general, any particular circular buffer can only be configured to operate in one direction, as there are certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing buffers) based upon the direction of the buffer. The only exception to the usage restrictions is for buffers which have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bidirectional mode (i.e., address boundary checks will be performed on both the lower and upper address boundaries). Register indirect with register offset addressing is only available for W9 (in X space) and W11 (in Y space). DS70139A-page 38 Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4.2.1 START AND END ADDRESS 4.2.2 The modulo addressing scheme requires that a starting and an ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table 3-3). Note: Y space modulo addressing EA calculations assume word sized data (LS bit of every EA is always clear). The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes). W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control register MODCON contains enable flags as well as a W register field to specify the W address registers. The XWM and YWM fields select which registers will operate with modulo addressing. If XWM = 15, X RAGU and X WAGU modulo addressing is disabled. Similarly, if YWM = 15, Y AGU modulo addressing is disabled. The X Address Space Pointer W register (XWM), to which modulo addressing is to be applied, is stored in MODCON (see Table 3-3). Modulo addressing is enabled for X data space when XWM is set to any value other than `15' and the XMODEN bit is set at MODCON. The Y Address Space Pointer W register (YWM), to which modulo addressing is to be applied, is stored in MODCON. Modulo addressing is enabled for Y data space when YWM is set to any value other than `15' and the YMODEN bit is set at MODCON. FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE Byte Address MOV MOV MOV MOV MOV MOV MOV #0x0000,W0 ;W0 holds buffer fill value MOV 0x1100 #0x1100,W0 W0,XMODSRT #0x1163,W0 W0,MODEND #0x8001,W0 W0,MODCON #0x1110,W1 ;point W1 to buffer DO AGAIN,#0x31 MOV W0,[W1+] AGAIN: INC W0,W0 0x1163 ;set modulo start address ;set modulo end address ;enable W1, X AGU for modulo ;fill the 50 buffer locations ;fill the next location ;increment the fill value Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words 2004 Microchip Technology Inc. Advance Information DS70139A-page 39 dsPIC30F2011/2012/3012/3013 4.2.3 MODULO ADDRESSING APPLICABILITY Modulo addressing can be applied to the effective address (EA) calculation associated with any W register. It is important to realize that the address boundaries check for addresses less than, or greater than the upper (for incrementing buffers), and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes may, therefore, jump beyond boundaries and still be adjusted correctly. Note: 4.3 The modulo corrected effective address is written back to the register only when PreModify or Post-Modify Addressing mode is used to compute the effective address. When an address offset (e.g., [W7+W2]) is used, modulo address correction is performed but the contents of the register remain unchanged. Bit-Reversed Addressing Bit-reversed addressing is intended to simplify data reordering for radix-2 FFT algorithms. It is supported by the X AGU for data writes only. The modifier, which may be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. 4.3.1 2. 3. XB is the bit-reversed address modifier or `pivot point' which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size. Note: BWM (W register selection) in the MODCON register is any value other than `15' (the stack cannot be accessed using bit-reversed addressing) and the BREN bit is set in the XBREV register and the addressing mode used is Register Indirect with Pre-Increment or Post-Increment. FIGURE 4-2: All bit-reversed EA calculations assume word sized data (LS bit of every EA is always clear). The XB value is scaled accordingly to generate compatible (byte) addresses. When enabled, bit-reversed addressing will only be executed for register indirect with pre-increment or post-increment addressing and word sized data writes. It will not function for any other addressing mode or for byte sized data, and normal addresses will be generated instead. When bit-reversed addressing is active, the W address pointer will always be added to the address modifier (XB) and the offset associated with the Register Indirect Addressing mode will be ignored. In addition, as word sized data is a requirement, the LS bit of the EA is ignored (and always clear). Note: BIT-REVERSED ADDRESSING IMPLEMENTATION Bit-reversed addressing is enabled when: 1. If the length of a bit-reversed buffer is M = 2N bytes, then the last `N' bits of the data buffer start address must be zeros. Modulo addressing and bit-reversed addressing should not be enabled together. In the event that the user attempts to do this, bit-reversed addressing will assume priority when active for the X WAGU, and X WAGU modulo addressing will be disabled. However, modulo addressing will continue to function in the X RAGU. If bit-reversed addressing has already been enabled by setting the BREN (XBREV) bit, then a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer DS70139A-page 40 Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY 16-ENTRY) Normal Address A3 A2 A1 A0 Bit-Reversed Address Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15 TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) XB Bit-Reversed Address Modifier Value 1024 0x0200 512 0x0100 256 0x0080 128 0x0040 64 0x0020 32 0x0010 16 0x0008 8 0x0004 4 0x0002 2 0x0001 2004 Microchip Technology Inc. Advance Information DS70139A-page 41 dsPIC30F2011/2012/3012/3013 NOTES: DS70139A-page 42 Advance Information 2004 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 5.0 FLASH PROGRAM MEMORY 5.2 Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046 DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer's Reference Manual (DS70030 DS70030). RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes) at a time and can write program memory data, 32 instructions (96 bytes) at a time. The dsPIC30F family of devices contains internal program Flash memory for executing user code. There are two methods by which the user can program this memory: 1. 2. 5.1 5.3 Table Instruction Operation Summary The TBLRDL and the TBLWTL instructions are used to read or write to bits of program memory. TBLRDL and TBLWTL can access program memory in Word or Byte mode. Run-Time Self-Programming (RTSP) In-Circuit Serial ProgrammingTM (ICSPTM) The TBLRDH and TBLWTH instructions are used to read or write to bits of program memory. TBLRDH and TBLWTH can access program memory in Word or Byte mode. In-Circuit Serial Programming (ICSP) dsPIC30F devices can be serially programmed while in the end application circuit. This is simply done with two lines for Programming Clock and Programming Data (which are named PGC and PGD respectively), and three other lines for Power (VDD), Ground (VSS) and Master Clear (MCLR). this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. FIGURE 5-1: Run-Time Self-Programming (RTSP) A 24-bit program memory address is formed using bits of the TBLPAG register and the effective address (EA) from a W register specified in the table instruction, as shown in Figure 5-1. ADDRESSING FOR TABLE AND NVM REGISTERS 24 bits Using Program Counter Program Counter 0 0 NVMADR Reg EA Using NVMADR Addressing 1/0 NVMADRU Reg 8 bits 16 bits Working Reg EA Using Table Instruction User/Configuration Space Select 2004 Microchip Technology Inc. 1/0 TBLPAG Reg 8 bits 16 bits 24-bit EA Advance Information Byte Select DS70139A-page 43 dsPIC30F2011/2012/3012/3013 5.4 RTSP Operation 5.5 The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instructions, or 96 bytes. Each panel consists of 128 rows, or 4K x 24 instructions. RTSP allows the user to erase one row (32 instructions) at a time and to program four instructions at one time. RTSP may be used to program multiple program memory panels, but the table pointer must be changed at each panel boundary. Each panel of program memory contains write latches that hold 32 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the panel write latches. The data to be programmed into the panel is loaded in sequential order into the write latches; instruction 0, instruction 1, etc. The instruction words loaded must always be from a group of 32 boundary. The basic sequence for RTSP programming is to set up a table pointer, then do a series of TBLWT instructions to load the write latches. Programming is performed by setting the special bits in the NVMCON register. 32 TBLWTL and four TBLWTH instructions are required to load the 32 instructions. If multiple panel programming is required, the table pointer needs to be changed and the next set of multiple write latches written. All of the table write operations are single word writes (2 instruction cycles), because only the table latches are written. A programming cycle is required for programming each row. The Flash Program Memory is readable, writable and erasable during normal operation over the entire VDD range. Control Registers The four SFRs used to read and write the program Flash memory are: · · · · NVMCON NVMADR NVMADRU NVMKEY 5.5.1 The NVMCON register controls which blocks are to be erased, which memory type is to be programmed, and start of the programming cycle. 5.5.2 NVMADR REGISTER The NVMADR register is used to hold the lower two bytes of the effective address. The NVMADR register captures the EA of the last table instruction that has been executed and selects the r