NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: logic array and embedded array gates are calculated. APEX 20K gates are compared to gate array gates, using LSI Logic's LCA300K LCA300K family of standard "sea-of-gates" gate arrays as a reference. Gate Count , 20K Device Features Feature Typical Gates Maximum System Gates Logic Elements Embedded System , Array Gates Logic array gates are the total number of usable gates available in the logic array of a , logic functions such as digital signal processing (DSP), microcontroller, wide data-path manipulation ... | Original |
8 pages, |
20K Preset datasheet d flipflop driving gates EP20K100 EP20K100E EP20K160E EP20K200 EP20K200E EP20K300E of the basic logic gates LCA300K EP20K60E EP20K600E EP20K400E datasheet abstract |
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| Abstract: SEPARATE NON-STANDARD ECL LOGIC FUNCTIONS -4 DUAL AND GATES • HIGHER SYSTEM RELIABILITY AND LOWER COST BY , presettable, multifunction MSI building block useful for a large number of counting, digital integration, and conversion applications. Up to 9 decades can be cascaded with no speed degradation using the standard 9500 gates. With 95H00 95H00 gates a multidecade synchronous load counter to over 150 MHz can be built. Typical , DESCRIPTION The 9507 is a Temperature Compensated Quad EC(L(L AND gate using series gating and collector and ... | OCR Scan |
1 pages, |
95H29 95H10 95H00 ECL D flip flop BCD 8421 synchronous counter using flip flip digital clock using logic gates digital clock using gates synchronous counter using 4 flip flip 95H10 abstract |
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| Abstract: designs containing between 62,000 and 158,000 gates of logic and RAM). This technical brief discusses how , EPF10K100 EPF10K100 device as the target device. The same FFT design was compiled using an LSI Logic LCA500K LCA500K gate , For the LSI Logic LCA500K LCA500K gate array, a total of 106,929 gates is required for FFT design , Gates Logic 3,458 LEs 46,637 Gates 128 Ã- 32 ROM 2,356 Gates The EPF10K100 EPF10K100 EABs , largest programmable logic device (PLD) currently available. Designers can use the EPF10K100 EPF10K100 to implement ... | Original |
2 pages, |
twiddle memory compiler gating a signal using NAND gates EPF10K100 fft algorithm digital clock using gates digital clock using logic gates EPF10K100 abstract |
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| Abstract: Interface Unit Communicates with SD/SDIO/MMC cards using the SD bus interface. It contains card clock , ), and software reset for DAT (clears the datapath logic). Configurability Area & Speed (clk clock , designs. The silicon area is below 16k gates for the simple single-slot version without DMA, or as little as 37k gates for the fully-featured 4slot version. Each slot can be individually controlled through , Applications Digital cameras and camcorders, storing images and video Digital audio players and cellular ... | Original |
2 pages, |
vhdl code dma controller silicon fingerprint technology sdio memory sdio GPS clock code using VHDL AMBA BUS vhdl code vhdl code for memory card tsmc 0.18um SDHC specification datasheet abstract |
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| Abstract: DVFS The basic equation describing the dynamic and static power consumption of a digital CMOS logic , the digital IC; VDD = supply voltage of the digital IC: fcu< = clock frequency of the digital IC; lL , back-biasing [also known as threshold march 2007 power management scaling], passively using multi-VT logic , achieve this is using National Semiconductor's Advanced Power Controller IP Power management is an , , between 30 and 50 per cent of the total energy budget may be consumed by digital processing. Traditionally ... | OCR Scan |
2 pages, |
PMIC digital clock using logic gates "power gating" switching management datasheet abstract |
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| Abstract: 288 macrocells (800 to 6,400 gates). These devices are manufactured using advanced 0.35u Flash , logic into new applications that include digital cameras, digital television, set-top boxes, arcade , Communications, editor@xilinx.com 2 XCell Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124-3450 , Programmable Logic Company is a service mark of Xilinx, Inc. Other brand or product names are trademarks or , person or entity using such information in any way releases and waives any claim it might have against ... | Original |
1 pages, |
XC9500XL XC9500 XC40110XV XC4000XV XC4000XLA XC4000XL datasheet abstract |
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| Abstract: 1. ORCA ORT4622-Available FPGA Logic Device Usable System Gates* Number of LUTs Number , , fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates , Highlights Allows the user to integrate the core with up to 120K gates of programmable logic (all in , FPGA logic to create complex functions, such as digital phase-locked loops, frequency counters, and , multiplexing/demultiplexing for 77.76 MHz byte-wide data processing in FPGA logic. On-chip phase-lock ... | Original |
6 pages, |
STS-48 ORT4622 bottle counter IEEE format BC432 8B10B intel 8098 digital clock using logic gates ORT4622 abstract |
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| Abstract: less silicon area (working in single-buffer mode only). SYN Â Synchronization Logic Cross clock , Dual-Port RAM. The core is competitive in its use of silicon space, requiring under 33K gates for a simple single-slot configuration without DMA, or 69K gates for a 4-slot version with Advanced DMA. The , devices such as digital cameras, camcorders, digital audio players, GPS receivers, cellular phones, and , wireless modems, digital TV tuners, and fingerprint recognition cards. Block Diagram compliant - ... | Original |
2 pages, |
sd card soc digital clock using logic gates SDXC datasheet abstract |
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| Abstract: , 10 Gbps Optical Transport Networks (OTN) using digital wrapper & strong FEC, or 10 Gbps SONET/SDH , synchronous interface with built-in clock and data recovery (CDR) in standard-cell logic, along with up to , System-on-a-Chip (FPSC) devices to its comprehensive line of in-system programmable logic solutions. The Optimized , features up to 900K usable FPGA sytem gates, high-speed I/O, embedded RAM, on-chip PLLs, and other , industry's first FPGA to include built-in system-level features like a Programmable Clock Manager & ... | Original |
2 pages, |
ORT8850 ORT82G5 ORT4622 ORLI10G OR3LP26B FPGA SoC, Chip, telecom datasheet abstract |
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| Abstract: flip-flops as handshaking flip-flops, a typical number of October 1993 logic AND gates is about 4 , programmable logic array to control the flip-flops. It accepts two clock sources and permits the internal , Programmable Logic Devices Application Note PLUS405-55 PLUS405-55 Â the ideal high speed interface common clock , on the clock's complement. Almost hidden from view in Figure 2 are two additional OR gates which , logic array. The two inverted OR gates (i.e., NOR gates) are called complement arrays. They are used ... | Original |
5 pages, |
single one jk flipflop PLUS405-55 digital clock using logic gates AN034 AN-034 PLUS405-55 abstract |
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| supermarket for digital logic. Motorola's reputation as a leading edge supplier for standard logic families Gate Arrays OPTOBUS Logic New Product Calendar Press Releases Press Releases can be found using the Press Release Database and searching on keywords. Search using the word Logic using the AN application note number. LOGIC LITERATURE Document Number Current Revision Document Title BR1332/D BR1332/D BR1332/D BR1332/D 3Q96 Logic New Product Calendar BR1333/D BR1333/D BR1333/D BR1333/D R5 Timing Solutions - Low Skew Clock www.datasheetarchive.com/files/motorola/design-n/logic/index.htm |
Motorola | 25/11/1996 | 4.95 Kb | HTM | index.htm |
| ) OTHER DIGITAL LOGIC 1. DIGITAL PLL DESIGN USING THE SN54/74LS297 SN54/74LS297 SN54/74LS297 SN54/74LS297 sdla005b.pdf (598 KBytes Application Reports for DIGITAL LOGIC Application Reports for DIGITAL LOGIC . GTL/BTL: A LOW-SWING SOLUTION FOR HIGH-SPEED DIGITAL LOGIC scea003a.pdf (198 KBytes) (Abstract .pdf (437 KBytes) (Abstract) 16. SYSTEM TESTABILITY USING STANDARD LOGIC scta037a.pdf (75 . MINIMIZING CLOCK DRIVER OUTPUT SKEW USING GANGED OUTPUTS scaa032.pdf (54 KBytes) (Abstract) 6 www.datasheetarchive.com/files/texas-instruments/data/sc/docs/psheets/app_log.htm |
Texas Instruments | 08/02/1999 | 27.14 Kb | HTM | app_log.htm |
| logic previously available to digital designers in the 500,000-gate Xilinx XC40250XV XC40250XV XC40250XV XC40250XV ä device Offerings Virtex device Logic cells System gates Block RAM delivering fast and predictable performance. The Virtex CLB implements logic using four independent four requirements exceed 100 MHz, digital designers cannot tolerate long clock-to-output times, input set-up times digital delay locked loop circuits that allow internal and external clock synchronization. This www.datasheetarchive.com/files/xilinx/docs/wcd00012/wcd012af.htm |
Xilinx | 16/02/1999 | 21.4 Kb | HTM | wcd012af.htm |
| logic previously available to digital designers in the 500,000-gate Xilinx XC40250XV XC40250XV XC40250XV XC40250XV ä device Offerings Virtex device Logic cells System gates Block RAM delivering fast and predictable performance. The Virtex CLB implements logic using four independent four requirements exceed 100 MHz, digital designers cannot tolerate long clock-to-output times, input set-up times digital delay locked loop circuits that allow internal and external clock synchronization. This www.datasheetarchive.com/files/xilinx/docs/rp0001f/rp01fee.htm |
Xilinx | 29/02/2000 | 21.33 Kb | HTM | rp01fee.htm |
| , fundamentally redefines programmable logic by expanding the traditional capabilities of field programmable gate digital designers in the 500,000-gate Xilinx XC40250XV XC40250XV XC40250XV XC40250XV ™ device. All of the initial nine members of the CLB implements logic using four independent four-input lookup tables, four independent set . DLL for Advanced Clock Synchronization As system performance requirements exceed 100 MHz, digital nanoseconds. The clock mirror for using the Virtex Series DLL to lock on to a system clock and provide www.datasheetarchive.com/files/xilinx/docs/rp0006e/rp06edd.htm |
Xilinx | 29/02/2000 | 18.6 Kb | HTM | rp06edd.htm |
| /O standards, digital delay lock loops for system clock management, and a hierarchy of high performance . The Xilinx Ã' Virtex devices fundamentally redefined programmable logic by expanding the traditional offer one million system gates. The latest Virtex-E devices, unveiled in September 1999, increase device density beyond three million system gates. "The market acceptance of Virtex FPGAs is unparalleled in the history of the programmable logic industry," said Xilinx CEO Wim Roelandts. "No other www.datasheetarchive.com/files/xilinx/docs/rp00001/rp00156.htm |
Xilinx | 29/02/2000 | 4.95 Kb | HTM | rp00156.htm |
| -12-16 AN263 AN263 AN263 AN263_2.pdf: Power considerations when using CMOS and BiCMOS logic devices 2002-02-05 AN10161 AN10161 AN10161 AN10161_2.pdf: PicoGate Logic footprints 2002 AN00070 AN00070 AN00070 AN00070_1.pdf: TDA8752B TDA8752B TDA8752B TDA8752B Triple 8-bit A/D converter dual chip solution for high resolution digital Speed Logic 1998-04-02 AN2301 AN2301 AN2301 AN2301.pdf: Simulation Support : Thermal Considerations for Advanced Logic Families AN97023 AN97023 AN97023 AN97023 www.datasheetarchive.com/files/philips/catalog/appnotes/29313-v1.html |
Philips | 01/06/2005 | 7.28 Kb | HTML | 29313-v1.html |
| . Delay-Locked Loop Associated with each global clock input buffer is a fully digital Delay 150 Max System Gates 15,000 30,000 50,000 100,000 150,000 Logic Cells -II Architectural Features Block Diagram The Spartan-II family of Field Programmable Gate Arrays Logic Blocks (CLBs), surrounded by a perimeter of programmable Input/Output Blocks www.datasheetarchive.com/files/xilinx/docs/rp00001/rp001e4.htm |
Xilinx | 19/03/2000 | 18.29 Kb | HTM | rp001e4.htm |
| ( clk: in std_logic; - word rate clock (74.25 MHz) rst: in std_logic; - async reset ce: in std_logic; - clock enable d: in hd_vid20 author's - efforts. Thank you for using our products ! - - Disclaimer: THESE DESIGNS ARE . - - Description of module: - - SMPTE 292M-1998 292M-1998 292M-1998 292M-1998 high-definition serial digital interface (HD-SDI) is a - standard for transmitting high-definition digital video over a serial link. - - HD-SDI specifies that www.datasheetarchive.com/download/91397821-996025ZC/xapp681.zip (hdsdi_decoder.vhd) |
Xilinx | 09/01/2004 | 89.65 Kb | ZIP | xapp681.zip |
| /98 XC4000 XC4000 XC4000 XC4000 Configurable Logic for Digital Signal Processing 140 KB Summary 12/96 XC4000 XC4000 XC4000 XC4000 Using Programmable Logic to Accelerate DSP Functions 190 KB Summary 12/96 XC4000 XC4000 XC4000 XC4000 A Guide to Using Field Programmable Gate Arrays (FPGAs) for resources of a DA processor for equal throughputs. Configurable Logic for Digital Signal Processing are using Synplicity and Xilinx to design a high density FPGA (100,000 gates). Phase I describes www.datasheetarchive.com/files/xilinx/docs/rp00003/rp0031b.htm |
Xilinx | 06/03/2000 | 36.71 Kb | HTM | rp0031b.htm |