500 MILLION PARTS FROM 12000 MANUFACTURERS

Part | Manufacturer | Description | Samples | Ordering |

TMDXL138LOGICEXP | Texas Instruments | OMAP-L138 Experimenter Kit | |||

TMDX138LOGICEXP | Texas Instruments | OMAP-L138 Experimenter Kit | |||

TTL-LOGIC-DATABOOK | Texas Instruments | TTL-LOGIC-DATABOOK |

Part | Manufacturer | Description | Last Check | Distributor | Ordering |

Catalog Datasheet | MFG & Type | Document Tags |

Abstract: gates: AND, OR, and NOT. In fact, we will see that any digital logic circuit can be made using only , design involving the drawing of logic diagrams when the digital circuit may contain thousands of gates , gates? As programmable logic devices replaced TTL chips in new designs a new approach to digital design , editor to draw logic circuits using basic gates. When you compile these block diagrams Active-HDL will , Introduction to Digital Design Using Digilent FPGA Boards â Block Diagram / Verilog Examples ... | Digilent Original |
111 pages, |
free transistor equivalent book full adder circuit using nor gates TEXT |

Abstract: implementation also requires the availability of a bit-rate clock for the FPGA. By using Virtex-II devices, a , next clock cycle. Ten 3-input XOR gates form the SDI descrambler. These gates generate the ten , clock cycles. The offset logic block generates the trs, nsp, and out_rdy outputs. The out_rdy signal is , of the bits of the bit_cntr. If downstream logic requires more setup time, the clock cycle when , detection logic examines. A series of ten-bit wide AND and NOR gates examine the 39-bit input vector to ... | Xilinx Original |
11 pages, |
video pattern generator using vhdl XAPP248 vhdl code 8 bit LFSR vhdl code for 8 bit barrel shifter XAPP247 test bench for 16 bit shifter XAPP298 sdi verilog code transmitter test bench verilog code for barrel shifter parallel scrambler 24 bit lfsr verilog code of 4 bit comparator vhdl code 4 bit LFSR barrel shifter using verilog SDI scrambler SDI descrambler vhdl code for 4 bit barrel shifter XAPP288 verilog code 8 bit LFSR in scrambler verilog code 8 bit LFSR in descrambler TEXT |

Abstract: Interface Unit Communicates with SD/SDIO/MMC cards using the SD bus interface. It contains card clock , ), and software reset for DAT (clears the datapath logic). Configurability Area & Speed (clk clock , . The silicon area is below 16k gates for the simple single-slot version without DMA, or as little as 37k gates for the fully-featured 4slot version. Each slot can be individually controlled through the , . Applications Digital cameras and camcorders, storing images and video Digital audio players and cellular ... | Cast Original |
2 pages, |
AMBA BUS vhdl code vhdl code dma controller silicon fingerprint technology sdio memory sdio MMC version 4 digital clock using logic gates GPS clock code using verilog GPS clock code using VHDL vhdl code for memory card tsmc 0.18um SD host controller vhdl SDHC specification TEXT |

Abstract: 1.8V 128 Macrocells (3,200 Gates), 9 I/O Standards, Slew Rate Control, Clock Doubler, Clcok Divider , , TQ144 TQ144 1.8V 256 Macrocells (6,400 Gates), 9 I/O Standards, Slew Rate Control, Clock Doubler, Clcok , TQ144 TQ144, PQ208 PQ208 1.8V 384 Macrocells (9,600 Gates), 9 I/O Standards, Slew Rate Control, Clock Doubler , MHz PQ208 PQ208 1.8V 512 Macrocells (12,800 Gates), 9 I/O Standards, Slew Rate Control, Clock , designs at any time. With our unique Internet Reconfigurable Logic (IRLTM) capability, you can remotely ... | Xilinx Original |
8 pages, |
DSKIT95XL Spartan-II pin details SPARTAN-II xc2s200 XC2S xc2s200 pq208 xc2s30 tq144 XC2S50E TQ144 XC9536XL XC9500XL XC9500 XC95 XC9572XL DS-KIT-95XL-PAK DS-KIT-2S300E DS-KIT-2C64 COOLRUNNER-II examples DS-KIT-95XL-XPLA3-PAK DS-KIT-95XL SPARTAN-II xc2s200 pq208 Xilinx usb cable Schematic TEXT |

Abstract: gates: AND, OR, and NOT. In fact, we will see that any digital logic circuit can be made using only , design involving the drawing of logic diagrams when the digital circuit may contain thousands of gates , gates? As programmable logic devices replaced TTL chips in new designs a new approach to digital design , block diagram editor to draw logic circuits using basic gates. When you compile these block diagrams , Introduction to Digital Design Using Digilent FPGA Boards â Block Diagram / VHDL Examples ... | Digilent Original |
124 pages, |
TEXT |

Abstract: , digital designers for the first time can use an FPGA to perform not only familiar logic functions, but , transistors. The Virtex XCV1000 XCV1000 doubles the density of programmable logic previously available to digital , CLB implements logic using four independent four-input lookup tables, four independent set/reset , digital designers with continuously higher levels of logic density and performance while offering more , MHz, digital designers cannot tolerate long clock-tooutput times, input set-up times, or on-chip clock ... | Xilinx Original |
9 pages, |
xilinx virtex 7 XC40250XV XCV100 XCV1000 XCV150 XCV200 XCV300 XCV400 XCV50 XCV600 XCV800 uart vhdl fpga virtex 6 digital clock using logic gates TEXT |

Abstract: less silicon area (working in single-buffer mode only). SYN Synchronization Logic Cross clock , Dual-Port RAM. The core is competitive in its use of silicon space, requiring under 33K gates for a simple single-slot configuration without DMA, or 69K gates for a 4-slot version with Advanced DMA. The , devices such as digital cameras, camcorders, digital audio players, GPS receivers, cellular phones, and , wireless modems, digital TV tuners, and fingerprint recognition cards. Block Diagram compliant - ... | Cast Original |
2 pages, |
sd card soc digital clock using logic gates SDXC TEXT |

Abstract: Digital Design Using Digilent FPGA Boards - Verilog / Active-HDL Edition Table of Contents 1. Introduction to Digital Logic 1.1 Background 1.2 Digital Logic 1.3 Verilog 1 1 5 8 2. Basic Logic Gates 2.1 Truth Tables and Logic Equations The Three Basic Gates Four New Gates 2.2 Positive and , Circuits 4.1 Implementing Gates 4.2 Transistor-Transistor Logic (TTL) 4.3 Programmable Logic Devices , -Bit Divider using a Task 6.6 Arithmetic Logic Unit (ALU) Verilog Examples Example 36 â 4-Bit ALU ... | Digilent Original |
6 pages, |
binary to gray code converter verilog code for binary division binary multiplier Verilog code 8-bit counter VERILOG verilog code for half subtractor 4 bit binary half adder Verilog code of 1-bit full subtractor verilog code of 16 bit comparator verilog code of 2 bit comparator half subtractor 4 bit alu verilog code 16 BIT ALU design with verilog code verilog code for distributed arithmetic verilog code for multiplexer 2 to 1 verilog code of 4 bit comparator full subtractor circuit using decoder verilog code of 8 bit comparator TEXT |

Abstract: transferred to FPGAs. Using good digital design techniques can prevent such problems. Wherever logic lies , resources, resulting in efficient logic utilization and high performance. Using cores to replace HDL code , general idea which Spartan device has sufficient logic resources to hold the design, count "system gates , density of ASICs is commonly measured using a "logic gate count", which is the total number of two-input NAND gates (four transistors per gate) in the design. One logic gate is equivalent to two system ... | Xilinx Original |
7 pages, |
XCS40 XCS30 XAPP119 hdl3 digital clock using logic gates vhdl code for spartan 6 The ten commandments TEXT |

Abstract: transferred to FPGAs. Using good digital design techniques can prevent such problems. Wherever logic lies , resources, resulting in efficient logic utilization and high performance. Using cores to replace HDL code , general idea which Spartan device has sufficient logic resources to hold the design, count "system gates , density of ASICs is commonly measured using a "logic gate count", which is the total number of two-input NAND gates (four transistors per gate) in the design. One logic gate is equivalent to two system ... | Xilinx Original |
7 pages, |
XCS40 XCS30 XAPP119 The ten commandments vhdl code for spartan 6 VHDL code for generate sound TEXT |

Abstract | Saved from | Date Saved | File Size | Type | Download |

Virtex series, digital designers for the first time can use an FPGA to perform not only familiar logic Virtex XCV1000 XCV1000 doubles the density of programmable logic previously available to digital designers in the Virtex CLB implements logic using four independent four-input lookup tables, four independent set/reset , FPGAs have provided digital designers with continuously higher levels of logic density and performance , or on-chip clock skew. To solve this, the Xilinx Virtex devices offer four independent, fully digital
/datasheets/files/xilinx/docs/wcd00012/wcd012af.htm |
Xilinx | 16/02/1999 | 21.4 Kb | HTM | wcd012af.htm |

Virtex series, digital designers for the first time can use an FPGA to perform not only familiar logic Virtex XCV1000 XCV1000 doubles the density of programmable logic previously available to digital designers in the Virtex CLB implements logic using four independent four-input lookup tables, four independent set/reset , FPGAs have provided digital designers with continuously higher levels of logic density and performance , or on-chip clock skew. To solve this, the Xilinx Virtex devices offer four independent, fully digital
/datasheets/files/xilinx/docs/rp0001f/rp01fee.htm |
Xilinx | 29/02/2000 | 21.33 Kb | HTM | rp01fee.htm |

Associated with each global clock input buffer is a fully digital Delay-Locked Loop (DLL) that can XC2S15 XC2S15 XC2S30 XC2S30 XC2S50 XC2S50 XC2S100 XC2S100 XC2S150 XC2S150 Max System Gates 15,000 30,000 50,000 100,000 150,000 Logic Cells 432 972 1728 2700 3888 (FPGAs) is implemented with a regular, flexible, programmable architecture of Configurable Logic advanced functions such as Block RAM and clock control blocks. Input/Output
/datasheets/files/xilinx/docs/rp00001/rp001e4.htm |
Xilinx | 19/03/2000 | 18.29 Kb | HTM | rp001e4.htm |

(47 KBytes) (Abstract) OTHER DIGITAL LOGIC 1. DIGITAL PLL DESIGN USING THE SN54 Application Reports for DIGITAL LOGIC Application Reports for DIGITAL LOGIC To view the following documents, Acrobat Reader 3.x is required. BACKPLANE LOGIC (GTL, FB/FBPLUS, ETL) 1. GTL/BTL: A LOW-SWING SOLUTION FOR HIGH-SPEED DIGITAL LOGIC slma003a.pdf (110 KBytes) (Abstract) 5. MINIMIZING CLOCK DRIVER OUTPUT SKEW USING GANGED
/datasheets/files/texas-instruments/data/sc/docs/psheets/app_log.htm |
Texas Instruments | 08/02/1999 | 27.14 Kb | HTM | app_log.htm |

delivering fast and predictable performance. The Virtex CLB implements logic using four independent , FPGAs have provided digital designers with continuously higher levels of logic density and performance on-chip clock skew. To solve this, the Xilinx Virtex devices offer four independent, fully digital delay clock-to-output delays of less than five nanoseconds. The clock mirror for using the Virtex Series DLL to routed on the board. For systems with logic on both clock domains, the edges of the 1X and 2X clock are
/datasheets/files/xilinx/docs/rp0006e/rp06edd.htm |
Xilinx | 29/02/2000 | 18.6 Kb | HTM | rp06edd.htm |

amount of logic used at the expense of one additional clock cycle, in reference to the implementation in Using Xilinx FPGAs to Design Custom DSPs Using Xilinx FPGAs to Design Custom Digital Signal Processing Devices by Gregory R. Goslin Corporate Applications Engineer Xilinx, Inc. Overview: Traditionally, digital signal processing (DSP) algorithms are most commonly implemented using general-purpose (programmable) DSP chips for low rate
/datasheets/files/xilinx/docs/wcd00010/wcd010b1-v1.htm |
Xilinx | 17/07/1998 | 26.65 Kb | HTM | wcd010b1-v1.htm |

amount of logic used at the expense of one additional clock cycle, in reference to the implementation in Using Xilinx FPGAs to Design Custom DSPs Using Xilinx FPGAs to Design Custom Digital Signal Processing Devices by Gregory R. Goslin Corporate Applications Engineer Xilinx, Inc. Overview: Traditionally, digital signal processing (DSP) algorithms are most commonly implemented using general-purpose (programmable) DSP chips for low rate
/datasheets/files/xilinx/docs/rp00020/rp0208a.htm |
Xilinx | 29/02/2000 | 26.6 Kb | HTM | rp0208a.htm |

No abstract text available
/download/71018457-977823ZC/rp06f2e.ppt |
Xilinx | 23/02/2000 | 1023 Kb | PPT | rp06f2e.ppt |

No abstract text available
/download/39162463-995960ZC/xapp288.zip () |
Xilinx | 26/04/2004 | 67.11 Kb | ZIP | xapp288.zip |

DL6035x.fm5 Table 1 DL6035X DL6035X Device Gates Logic Blocks Max User RAM Bits Flip Flops Clock Table 1 DL6000 DL6000 Family Device Gates Logic Blocks Max User RAM Bits Flip Flops Clock Trees I O Blocks Device Gates Logic Blocks Input Blocks Output Blocks Flip Flops Clock Trees DL5064 DL5064 1,250 64 48 49 212 6 Family Device Gates Logic Blocks Max User SRAM Bits Flip flops Clock Trees I O Blocks Availability DY6009 DY6009 Application Note Using Clock Enable in DynaChip 5K and 6K Devices . http://www.dyna.com
/datasheets/files/xilinx/docs/wcd00000/wcd0005d-v1.htm |
Xilinx | 16/02/1999 | 101.01 Kb | HTM | wcd0005d-v1.htm |