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digital clock using logic gates

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: gates: AND, OR, and NOT. In fact, we will see that any digital logic circuit can be made using only , design involving the drawing of logic diagrams when the digital circuit may contain thousands of gates , gates? As programmable logic devices replaced TTL chips in new designs a new approach to digital design , editor to draw logic circuits using basic gates. When you compile these block diagrams Active-HDL will , Introduction to Digital Design Using Digilent FPGA Boards â"' Block Diagram / Verilog Examples Digilent
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full adder circuit using nor gates free transistor equivalent book 16 bit carry select adder verilog code
Abstract: implementation also requires the availability of a bit-rate clock for the FPGA. By using Virtex-II devices, a , next clock cycle. Ten 3-input XOR gates form the SDI descrambler. These gates generate the ten , clock cycles. The offset logic block generates the trs, nsp, and out_rdy outputs. The out_rdy signal is , of the bits of the bit_cntr. If downstream logic requires more setup time, the clock cycle when , detection logic examines. A series of ten-bit wide AND and NOR gates examine the 39-bit input vector to Xilinx
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XAPP288 XAPP298 verilog code 8 bit LFSR in descrambler verilog code 8 bit LFSR in scrambler vhdl code for 4 bit barrel shifter SDI descrambler SDI scrambler 259M-1997 CLC011 CY7C9335 XAPP195
Abstract: Interface Unit Communicates with SD/SDIO/MMC cards using the SD bus interface. It contains card clock , ), and software reset for DAT (clears the datapath logic). Configurability Area & Speed (clk clock , . The silicon area is below 16k gates for the simple single-slot version without DMA, or as little as 37k gates for the fully-featured 4slot version. Each slot can be individually controlled through the , . Applications Digital cameras and camcorders, storing images and video Digital audio players and cellular Cast
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SDHC specification SD host controller vhdl tsmc 0.18um vhdl code for memory card GPS clock code using VHDL GPS clock code using verilog
Abstract: 1.8V 128 Macrocells (3,200 Gates), 9 I/O Standards, Slew Rate Control, Clock Doubler, Clcok Divider , , TQ144 1.8V 256 Macrocells (6,400 Gates), 9 I/O Standards, Slew Rate Control, Clock Doubler, Clcok , TQ144, PQ208 1.8V 384 Macrocells (9,600 Gates), 9 I/O Standards, Slew Rate Control, Clock Doubler , MHz PQ208 1.8V 512 Macrocells (12,800 Gates), 9 I/O Standards, Slew Rate Control, Clock , designs at any time. With our unique Internet Reconfigurable Logic (IRLTM) capability, you can remotely Xilinx
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Xilinx usb cable Schematic SPARTAN-II xc2s200 pq208 DS-KIT-95XL DS-KIT-95XL-XPLA3-PAK COOLRUNNER-II examples DS-KIT-2S300E QS9000
Abstract: gates: AND, OR, and NOT. In fact, we will see that any digital logic circuit can be made using only , design involving the drawing of logic diagrams when the digital circuit may contain thousands of gates , gates? As programmable logic devices replaced TTL chips in new designs a new approach to digital design , block diagram editor to draw logic circuits using basic gates. When you compile these block diagrams , Introduction to Digital Design Using Digilent FPGA Boards â"' Block Diagram / VHDL Examples Digilent
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Abstract: , digital designers for the first time can use an FPGA to perform not only familiar logic functions, but , transistors. The Virtex XCV1000 doubles the density of programmable logic previously available to digital , CLB implements logic using four independent four-input lookup tables, four independent set/reset , digital designers with continuously higher levels of logic density and performance while offering more , MHz, digital designers cannot tolerate long clock-tooutput times, input set-up times, or on-chip clock Xilinx
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uart vhdl fpga virtex 6 XCV800 XCV600 XCV50 XCV400 XCV300
Abstract: less silicon area (working in single-buffer mode only). SYN ­ Synchronization Logic Cross clock , Dual-Port RAM. The core is competitive in its use of silicon space, requiring under 33K gates for a simple single-slot configuration without DMA, or 69K gates for a 4-slot version with Advanced DMA. The , devices such as digital cameras, camcorders, digital audio players, GPS receivers, cellular phones, and , wireless modems, digital TV tuners, and fingerprint recognition cards. Block Diagram compliant - Cast
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SDXC sd card soc
Abstract: Digital Design Using Digilent FPGA Boards - Verilog / Active-HDL Edition Table of Contents 1. Introduction to Digital Logic 1.1 Background 1.2 Digital Logic 1.3 Verilog 1 1 5 8 2. Basic Logic Gates 2.1 Truth Tables and Logic Equations The Three Basic Gates Four New Gates 2.2 Positive and , Circuits 4.1 Implementing Gates 4.2 Transistor-Transistor Logic (TTL) 4.3 Programmable Logic Devices , -Bit Divider using a Task 6.6 Arithmetic Logic Unit (ALU) Verilog Examples Example 36 â'" 4-Bit ALU Digilent
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verilog code of 8 bit comparator full subtractor circuit using decoder verilog code for multiplexer 2 to 1 verilog code of 4 bit comparator verilog code for distributed arithmetic 16 BIT ALU design with verilog code
Abstract: transferred to FPGAs. Using good digital design techniques can prevent such problems. Wherever logic lies , resources, resulting in efficient logic utilization and high performance. Using cores to replace HDL code , general idea which Spartan device has sufficient logic resources to hold the design, count "system gates , density of ASICs is commonly measured using a "logic gate count", which is the total number of two-input NAND gates (four transistors per gate) in the design. One logic gate is equivalent to two system Xilinx
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XAPP119 The ten commandments vhdl code for spartan 6 hdl3 XCS30 XCS40
Abstract: transferred to FPGAs. Using good digital design techniques can prevent such problems. Wherever logic lies , resources, resulting in efficient logic utilization and high performance. Using cores to replace HDL code , general idea which Spartan device has sufficient logic resources to hold the design, count "system gates , density of ASICs is commonly measured using a "logic gate count", which is the total number of two-input NAND gates (four transistors per gate) in the design. One logic gate is equivalent to two system Xilinx
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VHDL code for generate sound
Abstract: programmable logic devices (PLDs) much faster than they could by using traditional methods, such as , solutions, design tools, and IP cores · Internet Configurable Logic (IRL): Field upgradeability using , The third method connects the gates by using software-controlled switches within the PLD Once the , risks. IP cores implement predefined logic functions such as digital signal processing (DSP), bus , is based on a CMOS chain of gates as the base building block for CPLD logic. The primary benefit of Xilinx
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toshiba satellite laptop battery pinout samsung plasma tv schematic diagram toshiba laptop schematic diagram XILINX vhdl code download REED SOLOMON TUTORIALS xilinx FFT samsung laptop battery pinout WP129
Abstract: the four PIOs per PIC is counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I , cycle for input clock rates from 5 MHz to 120 MHz. The PCM may be combined with FPGA logic to create , supply voltage for speed and compatibility. Up to 340,000 usable gates in 0.25 um. Up to 612 user I/Os , , selectable on a per-pin basis, when using 3.3 V I/O supply.) Twin-quad programmable function unit (PFU , byte-wide functions. Allows for mixed arithmetic and logic functions in a single PFU. Nine user registers Lattice Semiconductor
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OR3L165B 208-P 240-P 352-P 432-P 680-P
Abstract: Digital Design Using Digilent FPGA Boards â"' VHDL / Active-HDL Edition Table of Contents 1. Introduction 1.1 Background 1.2 Digital Logic 1.3 VHDL 1 1 5 8 2. Basic Logic Gates 2.1 Truth Tables and Logic Equations The Three Basic Gates Four New Gates 2.2 Positive and Negative Logic: De , 41 41 42 44 46 46 49 52 4. Implementing Digital Circuits 4.1 Implementing Gates 4.2 , -Input Gates Example 2: Multiple-Input Gates Problems 9 9 9 11 13 15 16 18 18 23 26 3 Digilent
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vhdl code for 16 BIT BINARY DIVIDER vhdl code for multiplexer 32 BIT BINARY VHDL code for PWM vhdl code for multiplexer 32 to 1 vhdl code for motor speed control PWM code using vhdl
Abstract: conditions are minimized. 2. The logic maps efficiently into the CPLD architecture. To perform digital , . Since most CPLDs have a regular structure consisting of LOGIC GATES -> REGISTER, it makes for efficient , levels of asynchronous logic continue to add in series and limit the maximum clock speed that can be , 4.8kHz. The modular PN generator uses more logic gates, as the EXOR operation is performed in parallel , combines a high-density programmable logic device, a crystal oscillator, and a pair of matched low-pass Maxim Integrated Products
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MAX2361 verilog code for cdma transmitter verilog code for matrix inversion 15-bit* pn sequence digital mixer verilog code code for pn generator in digital PN generator circuit 9152MH CY37256 2288MH E4433B AN918
Abstract: Manufacturer DIGITAL AND LINEAR MACROS A wide range of fully characterised elements, from logic gates and , 100MHz and complexities from 500 to 10,000 gates. *DS' Series of ULAs for 100 MHz Digital ASIC Systems , Logic' flip-flop: clock to output delay 1.5ns clock frequency 250MHz Gate delay: Ins virtually independent of fan-out, supply voltage and clock frequency LOW POWER PERFORMANCE 'Differential Logic , stacked across the supply rail (Fig. 1). Many complex and elegant logic functions can be implemented using -
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ferranti ula ula ferranti ferranti ula flip flop ULA100DS 901 SERIES 100MH 165//W
Abstract: gates. The line interface includes logic to divide the data rate down to 167 MHz or less (1/4 line , -192/STM-48), 10 Gbits/s optical transport networks (OTN) using digital wrapper and strong FEC, or 10 , gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs used as RAM are counted , gates are used for each PLL and 50k gates for the embedded system bus and microprocessor interface logic , -bit LVDS data interface for each) with a separate clock for each for transfer to the FPGA logic. s Lucent Technologies
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ORLI10G TTRN0110G TRCV0110G 4-bit GTL to LVTTL transceiver digital clock using gates write operation using ram in fpga PB01-048NCIP PB01-021NCIP
Abstract: FPGA gates. The line interface includes logic to divide the data rate down to 1/4 line rate or 1/8 , -192/STM-48), 10 Gbits/s optical transport networks (OTN) using digital wrapper and strong FEC, or 10 , System Chip (FPSC) which combines a high-speed line interface with a flexible FPGA logic core. Built on , line-side and system-side data rates, and a programmable logic interface at the system end for use with SONET/SDH, Ethernet, or OTN/digital wrapper with strong Forward Error Correction (FEC) system device Lattice Semiconductor
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OTN SWITCH STM-16 STM-64 OIF-SFI401 OC-192 1-800-LATTICE I0136A
Abstract: usable FPGA gates. The line interface includes logic to divide the data rate down to 167 MHz or less (1 , 10 Gbits/s SONET/SDH (OC-192/STM-48), 10 Gbits/s optical transport networks (OTN) using digital , groups are counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs , each) with a separate clock for each for transfer to the FPGA logic. POS-PHY4 interface for 10 , Block Diagram EMBEDDED CORE FPGA LOGIC (400K GATES) TRANSMIT PLLs 10 Gbit TXCLK 64:16 Lucent Technologies
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OC192
Abstract: can use multiple cells â  Digital features in s gate delays Differential logic giving , per column Columns Matrix cells Matrix gates 2 (Logic) Analog cells Bond pads 16 14 1 224 , logic gates and functions with d iffering complexities, functionality and speed/power attributes. The , transistors and 2 resistors. Gates with effective delays to below 1ns, and 1.5ns clock to output flip-flops , voltage and clock frequency. ^ T m 5 ^Tme ^ T m 7 Vs = internal logic supply rail Fig 4. DF -
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D011-
Abstract: .21 Horizontal Clock Shaping Logic , delays. Operating the CCD at its limits, using a 40MHz pixel clock, makes it very difficult to generate , a digital CCD camera with true 12-bit performance. © Philips Electronics N.V. 2000 All rights , . Besides some CCD theory it provides very useful information on how to design a high performance digital , applications including digital photography, broadcast and medical imaging. Chapter 6 summarizes all critical Philips Semiconductors
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EPF8282ALC84-4 SANYO 35CV10gX PPG SENSOR PRICE TL082D anFT18 light sensor LM358 CCD output buffer ANFT18 16CV100GX 35CV10GX 35CV47GX 35CV22GX 6CV220GX
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