NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS

Datasheet Archive - Datasheet Search Engine

 

Direct from the Manufacturer

Part Manufacturer Description PDF Samples Ordering
PROMOCLOCKE Freescale Semiconductor BINARY CLOCK 9S08QG8 ri Buy
CS2000CP-CZZR Cirrus Logic IC PHASE LOCKED LOOP, 30 MHz, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10, PLL or Frequency Synthesis Circuit ri Buy
CS2000P-DZZ Cirrus Logic IC PHASE LOCKED LOOP, 30 MHz, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10, PLL or Frequency Synthesis Circuit ri Buy

digital clock using logic gates

Catalog Datasheet Results Type PDF Document Tags
Abstract: logic array and embedded array gates are calculated. APEX 20K gates are compared to gate array gates, using LSI Logic's LCA300K LCA300K family of standard "sea-of-gates" gate arrays as a reference. Gate Count , 20K Device Features Feature Typical Gates Maximum System Gates Logic Elements Embedded System , Array Gates Logic array gates are the total number of usable gates available in the logic array of a , logic functions such as digital signal processing (DSP), microcontroller, wide data-path manipulation ... Original
datasheet

8 pages,
131.34 Kb

20K Preset datasheet d flipflop driving gates EP20K100 EP20K100E EP20K160E EP20K200 EP20K200E EP20K300E of the basic logic gates EP20K60E EP20K600E EP20K400E datasheets of the basic logic gates datasheet abstract
datasheet frame
Abstract: SEPARATE NON-STANDARD ECL LOGIC FUNCTIONS -4 DUAL AND GATES • HIGHER SYSTEM RELIABILITY AND LOWER COST BY , presettable, multifunction MSI building block useful for a large number of counting, digital integration, and conversion applications. Up to 9 decades can be cascaded with no speed degradation using the standard 9500 gates. With 95H00 95H00 gates a multidecade synchronous load counter to over 150 MHz can be built. Typical , DESCRIPTION The 9507 is a Temperature Compensated Quad EC(L(L AND gate using series gating and collector and ... OCR Scan
datasheet

1 pages,
50.02 Kb

95H00 95H10 jk flip flop to d flip flop conversion ECL D flip flop BCD 8421 95H29 synchronous counter using flip flip digital clock using logic gates digital clock using gates synchronous counter using 4 flip flip 95H10 abstract
datasheet frame
Abstract: designs containing between 62,000 and 158,000 gates of logic and RAM). This technical brief discusses how , EPF10K100 EPF10K100 device as the target device. The same FFT design was compiled using an LSI Logic LCA500K LCA500K gate , For the LSI Logic LCA500K LCA500K gate array, a total of 106,929 gates is required for FFT design , Gates Logic 3,458 LEs 46,637 Gates 128 - 32 ROM 2,356 Gates The EPF10K100 EPF10K100 EABs , largest programmable logic device (PLD) currently available. Designers can use the EPF10K100 EPF10K100 to implement ... Original
datasheet

2 pages,
151.24 Kb

twiddle memory compiler gating a signal using NAND gates EPF10K100 fft algorithm digital clock using gates digital clock using logic gates EPF10K100 abstract
datasheet frame
Abstract: Interface Unit Communicates with SD/SDIO/MMC cards using the SD bus interface. It contains card clock , ), and software reset for DAT (clears the datapath logic). Configurability Area & Speed (clk clock , designs. The silicon area is below 16k gates for the simple single-slot version without DMA, or as little as 37k gates for the fully-featured 4slot version. Each slot can be individually controlled through , Applications Digital cameras and camcorders, storing images and video Digital audio players and cellular ... Original
datasheet

2 pages,
561.56 Kb

AMBA BUS vhdl code GPS clock code using verilog sdio sdio memory silicon fingerprint technology vhdl code dma controller GPS clock code using VHDL digital clock using logic gates vhdl code for memory card tsmc 0.18um SD host controller vhdl SDHC specification datasheet abstract
datasheet frame
Abstract: DVFS The basic equation describing the dynamic and static power consumption of a digital CMOS logic , the digital IC; VDD = supply voltage of the digital IC: fcu< = clock frequency of the digital IC; lL , back-biasing [also known as threshold march 2007 power management scaling], passively using multi-VT logic , achieve this is using National Semiconductor's Advanced Power Controller IP Power management is an , , between 30 and 50 per cent of the total energy budget may be consumed by digital processing. Traditionally ... OCR Scan
datasheet

2 pages,
858.34 Kb

Solar panel regulator PMIC digital clock using logic gates "power gating" switching management solar voltage regulator powerwise interface datasheet abstract
datasheet frame
Abstract: 1. ORCA ORT4622-Available FPGA Logic Device Usable System Gates* Number of LUTs Number , , fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates , Highlights Allows the user to integrate the core with up to 120K gates of programmable logic (all in , FPGA logic to create complex functions, such as digital phase-locked loops, frequency counters, and , multiplexing/demultiplexing for 77.76 MHz byte-wide data processing in FPGA logic. On-chip phase-lock ... Original
datasheet

6 pages,
60.24 Kb

STS-48 scrambling ORT4622 bottle counter IEEE format BC432 8B10B intel 8098 digital clock using logic gates ORT4622 abstract
datasheet frame
Abstract: 288 macrocells (800 to 6,400 gates). These devices are manufactured using advanced 0.35µ Flash , logic into new applications that include digital cameras, digital television, set-top boxes, arcade , Communications, editor@xilinx.com 2 XCell Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124-3450 , Programmable Logic Company is a service mark of Xilinx, Inc. Other brand or product names are trademarks or , person or entity using such information in any way releases and waives any claim it might have against ... Original
datasheet

1 pages,
202.69 Kb

XC9500XL XC9500 XC40110XV XC4000XV XC4000XLA XC4000XL datasheet abstract
datasheet frame
Abstract: less silicon area (working in single-buffer mode only). SYN ­ Synchronization Logic Cross clock , Dual-Port RAM. The core is competitive in its use of silicon space, requiring under 33K gates for a simple single-slot configuration without DMA, or 69K gates for a 4-slot version with Advanced DMA. The , devices such as digital cameras, camcorders, digital audio players, GPS receivers, cellular phones, and , wireless modems, digital TV tuners, and fingerprint recognition cards. Block Diagram compliant - ... Original
datasheet

2 pages,
138.33 Kb

sd card soc digital clock using logic gates SDXC datasheet abstract
datasheet frame
Abstract: , 10 Gbps Optical Transport Networks (OTN) using digital wrapper & strong FEC, or 10 Gbps SONET/SDH , synchronous interface with built-in clock and data recovery (CDR) in standard-cell logic, along with up to , System-on-a-Chip (FPSC) devices to its comprehensive line of in-system programmable logic solutions. The Optimized , features up to 900K usable FPGA sytem gates, high-speed I/O, embedded RAM, on-chip PLLs, and other , industry's first FPGA to include built-in system-level features like a Programmable Clock Manager & ... Original
datasheet

2 pages,
19.58 Kb

ORT8850 ORT82G5 ORT4622 ORLI10G OR3LP26B FPGA SoC, Chip, telecom datasheet abstract
datasheet frame
Abstract: flip-flops as handshaking flip-flops, a typical number of October 1993 logic AND gates is about 4 , programmable logic array to control the flip-flops. It accepts two clock sources and permits the internal , Programmable Logic Devices Application Note PLUS405-55 PLUS405-55 ­ the ideal high speed interface common clock , on the clock's complement. Almost hidden from view in Figure 2 are two additional OR gates which , logic array. The two inverted OR gates (i.e., NOR gates) are called complement arrays. They are used ... Original
datasheet

5 pages,
50.27 Kb

single one jk flipflop Maximum Megahertz Project digital clock using logic gates AN034 AN-034 PLUS405-55 PLUS405-55 abstract
datasheet frame

Datasheet Content (non pdf)

Abstract Saved from Date Saved File Size Type Download
Over 1.1 million files (1986-2014): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer.
 
LOADING scea004.pdf (47 KBytes) (Abstract) OTHER DIGITAL LOGIC 1. DIGITAL PLL DESIGN USING THE Application Reports for DIGITAL LOGIC To view the following documents HIGH-SPEED DIGITAL LOGIC scea003a.pdf (198 KBytes) (Abstract) 2. NEXT-GENERATION BTL/FUTUREBUS slma003a.pdf (110 KBytes) (Abstract) 5. MINIMIZING CLOCK DRIVER OUTPUT SKEW USING GANGED OUTPUTS ) (Abstract) DIGITAL LOGIC 1. 12-MM 12-MM 12-MM 12-MM TAPE-AND-REEL COMPONENT-DELIVERY SYSTEM slza001.pdf (69 KBytes
www.datasheetarchive.com/files/texas-instruments/data/sc/docs/psheets/app_log.htm
Texas Instruments 08/02/1999 27.14 Kb HTM app_log.htm
, digital designers for the first time can use an FPGA to perform not only familiar logic functions, but transistors. The Virtex XCV1000 XCV1000 XCV1000 XCV1000 doubles the density of programmable logic previously available to digital The Virtex CLB implements logic using four independent four-input lookup tables, four independent set , FPGAs have provided digital designers with continuously higher levels of logic density and performance four independent, fully digital delay locked loop circuits that allow internal and external clock
www.datasheetarchive.com/files/xilinx/docs/wcd00007/wcd00791-v2.htm
Xilinx 04/06/1999 21.34 Kb HTM wcd00791-v2.htm
, digital designers for the first time can use an FPGA to perform not only familiar logic functions, but transistors. The Virtex XCV1000 XCV1000 XCV1000 XCV1000 doubles the density of programmable logic previously available to digital The Virtex CLB implements logic using four independent four-input lookup tables, four independent set , FPGAs have provided digital designers with continuously higher levels of logic density and performance four independent, fully digital delay locked loop circuits that allow internal and external clock
www.datasheetarchive.com/files/xilinx/docs/wcd00012/wcd012af.htm
Xilinx 16/02/1999 21.4 Kb HTM wcd012af.htm
, digital designers for the first time can use an FPGA to perform not only familiar logic functions, but transistors. The Virtex XCV1000 XCV1000 XCV1000 XCV1000 doubles the density of programmable logic previously available to digital The Virtex CLB implements logic using four independent four-input lookup tables, four independent set , FPGAs have provided digital designers with continuously higher levels of logic density and performance four independent, fully digital delay locked loop circuits that allow internal and external clock
www.datasheetarchive.com/files/xilinx/docs/rp0001f/rp01fee.htm
Xilinx 29/02/2000 21.33 Kb HTM rp01fee.htm
CLB implements logic using four independent four-input lookup tables, four independent set/reset , digital designers cannot tolerate long clock-to-output times, input set-up times, or on-chip clock skew. less than five nanoseconds. The clock mirror for using the Virtex Series DLL to lock on to a system board. For systems with logic on both clock domains, the edges of the 1X and 2X clock are aligned to Clock Synchronization SelectRAM+ ™ and Memory Hierarchy Virtex SelectI/O ™ Virtex Core
www.datasheetarchive.com/files/xilinx/docs/rp0006e/rp06edd.htm
Xilinx 29/02/2000 18.6 Kb HTM rp06edd.htm
FPGAs, digital designers for the first time can use the devices to perform not only familiar logic fundamentally redefined programmable logic by expanding the traditional capabilities of FPGAs to include a designs. The Virtex series was also the industry's first line of FPGAs to offer one million system gates system gates. "The market acceptance of Virtex FPGAs is unparalleled in the history of the programmable logic industry," said Xilinx CEO Wim Roelandts. "No other product has ever ramped as fast, and
www.datasheetarchive.com/files/xilinx/docs/rp00001/rp00156.htm
Delay-Locked Loop Associated with each global clock input buffer is a fully digital Delay-Locked XC2S150 XC2S150 XC2S150 XC2S150 Max System Gates 15,000 30,000 50,000 100,000 150,000 Logic Cells Logic Blocks (CLBs), surrounded by a perimeter of programmable Input/Output Blocks architecture also provides advanced functions such as Block RAM and clock control blocks.
www.datasheetarchive.com/files/xilinx/docs/rp00001/rp001e4.htm
Xilinx 19/03/2000 18.29 Kb HTM rp001e4.htm
possible to cross the United States via automobile using less than a pint of fuel. For digital 0.6-micron CMOS DSP, the TMS320LC545 TMS320LC545 TMS320LC545 TMS320LC545, using a 0.35-micron CMOS process with 0.25-micron transistor gates. The time critical logic functions in the CPU were built using faster transistors with a lower threshold of Make your PCI bus perform 4x faster TI-Japan, Matsushita develop 1394 IC for digital video The power of 1V TI demonstrates 1-V DSP for digital wireless phones In a breakthrough for
www.datasheetarchive.com/files/texas-instruments/data/sc/docs/integrat/97mar/1v.htm
Texas Instruments 08/02/1999 9.53 Kb HTM 1v.htm
efficiently into the CPLD architecture. To perform digital design using modern hardware description consisting of LOGIC GATES -> REGISTER, it makes for efficient mapping into the CPLD if the Verilog code random data in this design, being clocked at 4.8kHz. The modular PN generator uses more logic gates : module i_code_s( clock, resetn, i_code_out); // Generate the 15-bit PN code using the polynomial high-density programmable logic device, a crystal oscillator, and a pair of matched low-pass filters to provide
www.datasheetarchive.com/files/maxim/0004/appno015-v1.htm
Maxim 02/05/2002 21.64 Kb HTM appno015-v1.htm
performance advantages over traditional off-the-shelf DSP solutions. Using Programmable Logic to Accelerate DSP Functions This paper discusses the benefits of using programmable logic in Digital 300 KB Summary 11/98 XC4000 XC4000 XC4000 XC4000 Configurable Logic for Digital Signal Summary 12/96 XC4000 XC4000 XC4000 XC4000 Using Programmable Logic to Accelerate DSP Functions filters using Xilinx FPGA technology. The implementation provides a significant savings in device logic
www.datasheetarchive.com/files/xilinx/docs/rp00003/rp0031b.htm
Xilinx 06/03/2000 36.71 Kb HTM rp0031b.htm