NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 7.85ÍREF.) 0.309(REF.) DVI_D(M) CKT DETAIL A 0.531MAX 531MAX.) DFP(M) BACK SIDE cxxx ^-WEEK NO.FOR -YEAR NO. -"C" FOR MOLEX YEAR. CHINA DETAIL C 88741-8621 DVI.D-DFP DIGITAL CABLE ASS'Y 5M PARCHMENT WHT 5000 ± 150 I9S.9 ± 5.9 PARCHMENT WHITE 887808287 88741-8611 DVI.D-DFP DIGITAL CABLE ASS'Y 3M PARCHMENT WHT 3000 ± SO 1 IB. 1 ± 3.1 PARCHMENT WHITE 887808287 88741-8601 DVI.D-DFP DIGITAL CABLE ASS'Y 2M PARCHMENT WHT 2000 t 60 78.7 ± 2.4 PARCHMENT WHITE 887808827 88741-8620 DVI.D-DFP DIGITAL CABLE ASS'Y 5M BLK ... | OCR Scan |
2 pages, |
molex CT Connector dvi-d 24 pin diagram dvi to dfp DFP to DVI dfp cable molex mx digital clock ckt diagram dfp 20 pin 16-PIN 16-PIN abstract |
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| Abstract: 15 DATA 2nd 16 CLOCK 2nd 17 Fref IN Block Diagram ( CT10DS CT10DS ) LPF 1st MIX HPF HPF LPF , Digital CATV Tuner CT10DS CT10DS Part No.: ENA4 0 Type : Type CT10DS CT10DS ( Double Conversion ), high per formance for digital/analog Hybrid transmission receiver. Features Low profile / Compact size , /downstream data filter circuit Recommended Applications CATV Set Top Box for digital and analog Hybrid , / Digital ) Gain Power Supply Noise Figure Phase Noise Tuning Voltage AGC Range U.S.A. Channel 54 ... | Original |
2 pages, |
ENA4 digital clock ckt diagram CT10DS LPF, HPF, BPF filter rf CT10DS abstract |
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| Abstract: Digital CATV Tuner CT10DS CT10DS Part No.: ENA4 0 Type : Type CT10DS CT10DS ( Double Conversion ), high performance for CATV digital/analog Hybrid transmission receiver. Features Low profile / Compact size , /downstream data filter circuit Recommended Applications CATV Set Top Box for digital and analog Hybrid , 3. RF Input Impedance 4. PLL Interface 5. Output Frequency ( Analog / Digital ) Europe Channel , EN38 Digital CATV Tuner Dimensions in mm (not to scale) CT10DS CT10DS 8.8 3.8 0.6 3.9 4.0 ... | Original |
2 pages, |
EN38 digital clock ckt diagram CT10DS BP 109 transistor ENA4 LPF, HPF, BPF filter rf CT10DS abstract |
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| Abstract: sync input for receive and transmit digital data. J13 Common clock for CODEC data transfer and , 0 1 x 1 CLOCK GENERATION & MUX 0 J15 FIGURE 6. DIGITAL LOOP BACK CONNECTORS AND , JP7 CODEC APP CKT JP8 ISL5585 ISL5585 APP CKT J12 J13 JP5 JP1 JP11 JP12 J2 JP2 J14 JP10 J1 S1 S2 S3 S4 S5 CLOCK GENERATION & MUX S6 J15 FIGURE 2. EVALUATION BOARD FUNCTIONAL DIAGRAM Evaluation Board Jumper Definitions JUMPER DESCRIPTION JP1 ... | Original |
13 pages, |
XO-43B APPLICATION AN1038 application note 1038 ISL55185XEVAL1 ISL5585 rx 411 socket S1 TIP 411 X0-43B 1N400X XO-43B RJ11 socket connector pinout BNC connector FOOT PRINT BAS21ZXCT ISL5585XEVAL AN1038 ISL5585XEVAL abstract |
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| Abstract: transmit digital data. J13 Common clock for CODEC data transfer and conversion. J14 20 pin, 100 , selects on board clock and frame sync generator. J14, POSN 1 Connects the CODEC digital output DT , The signal levels for digital loop back are independent of the clock selected by JP10. Refer to the , JP3 JP9 JP6 JP4 J3 JP8 JP7 CODEC APP CKT J12 HC5518x APP CKT J13 JP5 JP1 JP11 JP12 J2 JP2 J14 JP10 J1 S1 S2 S3 S4 S5 CLOCK GENERATION & MUX S6 ... | Original |
13 pages, |
XO-43B APPLICATION rx 411 HC55183 HC55182 HC55180 BNC connector FOOT PRINT BAS21ZXCT HC5518XEVAL AN9814 HC5518XEVAL abstract |
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| Abstract: input for receive and transmit digital data. J13 Common clock for CODEC data transfer and , 0.674VRMS 674VRMS . The signal levels for digital loop back are independent of the clock selected by JP10. Refer , APP CKT JP8 J12 HC55185 HC55185 APP CKT J13 JP5 JP1 JP11 JP12 J2 JP2 J14 JP10 J1 S1 S2 S3 S4 S5 CLOCK GENERATION & MUX S6 J15 FIGURE 2. EVALUATION BOARD FUNCTIONAL DIAGRAM Evaluation Board Jumper Definitions JUMPER DESCRIPTION JP1 Connects SW- ... | Original |
13 pages, |
X0-43B RJ11 socket connector pinout HC55185 digital clock ckt diagram CBJR20 BAS21ZXCT HC5518XEVAL HC5518XEVAL abstract |
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| Abstract: Timing Diagram Signal DCLK VSYNC HSYNC IDATA DE Parameter Pixel clock frequency Low , Diagram Notes: 1. In blanked (controlled) clock mode, there are four extra load clock cycles at the , : RCK to CONV Timing Diagram Signal Parameter Symbol RCK Row clock pulse width. Row off , clock cycle. In this mode, some of the programming pins (CK_P, DINV, ST, PIX_O, CK_D, CK_T, CV_W, CD_E , pixels are output per clock 34 Dual Edge Clocking CK_D = 0 Dual edge clocking is off CK_T ... | Original |
19 pages, |
tx2/rx2 CDTA14 201C DFP 30 pin cable nec monitor lcd monitor ckt datasheet abstract |
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| Abstract: MARCONI CKT TECHNOLOGY 3GE D - 57031442 0G01S2 0G01S2Û S - • Digital Switch Maa-cona Electronic , Respective Manufacturer 3542 A-09 MARCONI CKT TECHNOLOGY 30E » - S7"3442.0001S30 0001S30 3 - T" 3 Marconi Digital Switch Electronic Devices Module MA811 MA811 Fig. 1 DSM Block Diagram PCM Inputs 2.048 Mb/s Master Clock , Mat^^L^C^pyrìghtec^By Respective Manufacturer MARCONI CKT TECHNOLOGY 3GE D - S7"3442 DQ01S33 DQ01S33 1 - Digital Switch , Manufacturer MARCONI CKT TECHNOLOGY 3DE D - S7-344E -344E GGG1535 GGG1535 H - T" 3 Digital Switch MA811 MA811 Module Marc®iii ... | OCR Scan |
17 pages, |
MA811 G732 0G01S2 0G01S2 abstract |
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| Abstract: + 70 °C 0.75 mm BLOCK DIAGRAM 36 35 34 33 32 31 30 29 28 27 26 25 , _ 39 21 BUFFER 2 MUTE BUFFER 1 ADDRESS DECODER LED DRIVING CKT 37 S-P , Manual Selection S/W for VTR 19 D-GND Digital GND 20 RESET RESET 21 MUTIN I Not use 22 CEIN I Enable Input from MICOM 23 CLIN I Clock Input , 26 MUTIM Muting time decision during Manual Control 27 VCC VCC (Digital ... | Original |
8 pages, |
KA22293Q KA22293 48-QFP-1010E 48-QFP-1010D KA22293/Q 48-QFP-1010D/1010E KA22293/Q abstract |
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| Abstract: 1 S1A0293A S1A0293A AUDIO SIGNAL PROCESSOR BLOCK DIAGRAM 36 35 34 33 32 31 30 29 , CKT 37 S-P CONVERTER 43 SWITCH CONTROLLER Analog Switch (R) 44 45 46 47 48 MUTE , for VTR 19 D-GND - Digital GND 20 RESET - RESET 21 MUTIN I Not use 22 CEIN I Enable Input from MICOM 23 CLIN I Clock Input from MICOM 24 DAIN , Muting time decision during Manual Control 27 VCC - VCC (Digital) 28 VCC - VCC ... | Original |
8 pages, |
S1A0293A 48-QFP-1010E S1A0293A abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| - outputs • Linear slope integrating Analog to Digital -conversion techniques - advantages -digital low level. When the voltage at VIN+ is greater than the voltage at VIN-, the output of the comparator is at a digital high level. The shaded areas of the -comparator output waveform represent the contents of the PORTA data latch are placed on the pin. The value at the pin, which can be a digital Comparators Reset Mode except that RA0 through RA3 are digital I/O. This mode may consume more -current if www.datasheetarchive.com/files/microchip/ech_src/an611/an611.txt |
Microchip | 08/06/1995 | 106.41 Kb | TXT | an611.txt |
| three external outputs in the completed design. The system clock is an internally generated signal external output pin assignments for TENSOUT, ONESOUT, and TENTHSOUT output buses. • DEBUG_CKT Schematic www.datasheetarchive.com/download/87884801-985620ZC/wcd00f5d.zip (wd_fnd_15a.pdf) |
Xilinx | 12/02/1999 | 1645.78 Kb | ZIP | wcd00f5d.zip |
| shutdown pin respond to digital stimulus, and * (d) used digital simulation for the internal logic ; internal clock period + deadtime = 1us ; internal clock deadtime * Pin 6 (RT pin) NOT NECESSARY due to *|* AND DEMONSTRATES THE USE OF THE 1524B 1524B 1524B 1524B MACROMODEL. *| *|.LIB "swit_reg.lib" *|.LIB "digital ; 1.25A LOAD CURRENT AT OUTPUT *|UPRS STIM(1,1) $G_DPWR $G_8 10 IO_STM 0S 0 ; DIGITAL SHUTDOWN (only two bipolars per output driver), * (c) the sync pin is ignored (can drive clock directly if needs www.datasheetarchive.com/files/spicemodels/misc/spice_model_cd/mixed part list/spice-models-collection/swit_reg.lib |
Spice Models | 29/07/2012 | 79.15 Kb | LIB | swit_reg.lib |
| . 10450 ~ ~ Circuit( 10451 ~ ~ Diagram 10452 ~ ~ PCB Layout 10453 ~ ~ Page( 10454 ~ ~ EDWin XP simcode 11460 ~ ~ Model/Sub ckt 11461 ~ ~ EDWin 2000 - Editing Package ( 11462 ~ ~ part name not . : 11695 ~ ~ Use EDSpice : 11696 ~ ~ Element Code : 11697 ~ ~ Model/Sub Ckt. : 11698 www.datasheetarchive.com/files/kaleidoscope/cad/visionics_edwinxp140/country/italian/e2klocal.txt |
Kaleidoscope | 10/05/2004 | 456.61 Kb | TXT | e2klocal.txt |
| 99945 ~ ~ Not used in symbol 99946 ~ ~ No variables selected for diagram 99947 ~ ~ Node 99948 www.datasheetarchive.com/files/kaleidoscope/cad/visionics_edwinxp140/country/english/e2klocal.txt |
Kaleidoscope | 03/06/2005 | 375.42 Kb | TXT | e2klocal.txt |
| 99945 ~ ~ Not used in symbol 99946 ~ ~ No variables selected for diagram 99947 ~ ~ Node 99948 www.datasheetarchive.com/files/kaleidoscope/cad/visionics_edwinxp140/country/chinese/e2klocal.txt |
Kaleidoscope | 10/05/2004 | 373.4 Kb | TXT | e2klocal.txt |
| 99945 ~ ~ Not used in symbol 99946 ~ ~ No variables selected for diagram 99947 ~ ~ Node 99948 www.datasheetarchive.com/files/kaleidoscope/cad/visionics_edwinxp140/country/polish/e2klocal.txt |
Kaleidoscope | 10/05/2004 | 373.4 Kb | TXT | e2klocal.txt |
| 99945 ~ ~ Not used in symbol 99946 ~ ~ No variables selected for diagram 99947 ~ ~ Node 99948 www.datasheetarchive.com/files/kaleidoscope/cad/visionics_edwinxp140/country/german/e2klocal.txt |
Kaleidoscope | 10/05/2004 | 373.4 Kb | TXT | e2klocal.txt |
| -25 Preset Pin or Clear Pin . 2-27 Using Clock -skew Clock Buffers . 3-2 Inserting Clock Buffers. 3-4 Instantiating Internal Global Clock Buffers. 3-4 Using Dedicated . Performing a timing simulation of your design. Figure 1-1 HDL Flow Diagram for a New Design The design flow transition from graphical concepts, such as block diagrams, state machines, flow diagrams and truth tables www.datasheetarchive.com/download/42526031-958227ZC/hdl_dg.zip (HDL_DG.PDF) |
Xilinx | 05/09/1996 | 1562.66 Kb | ZIP | hdl_dg.zip |
| shutdown pin respond to digital stimulus, and * (d) used digital simulation for the internal logic ; internal clock period + deadtime = 1us ; internal clock deadtime * Pin 6 (RT pin) NOT NECESSARY due to *|* AND DEMONSTRATES THE USE OF THE 1524B 1524B 1524B 1524B MACROMODEL. *| *|.LIB "swit_reg.lib" *|.LIB "digital ; 1.25A LOAD CURRENT AT OUTPUT *|UPRS STIM(1,1) $G_DPWR $G_8 10 IO_STM 0S 0 ; DIGITAL SHUTDOWN (only two bipolars per output driver), * (c) the sync pin is ignored (can drive clock directly if needs www.datasheetarchive.com/files/spicemodels/misc/swit_reg.lib |
Spice Models | 01/09/2009 | 320.85 Kb | LIB | swit_reg.lib |