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Part Manufacturer Description Datasheet BUY
SN74161J-00 Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-16 visit Texas Instruments
SN74161N-10 Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16 visit Texas Instruments
SN74161N3 Texas Instruments Synchronous 4-bit binary counters 16-PDIP 0 to 70 visit Texas Instruments
SN74161N-00 Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16, CERAMIC, DIP-16 visit Texas Instruments
SN74161N Texas Instruments Synchronous 4-bit binary counters 16-PDIP 0 to 70 visit Texas Instruments
SN74161D Texas Instruments Synchronous 4-bit binary counters 16-SOIC 0 to 70 visit Texas Instruments

diagram of IC 74161

Catalog Datasheet MFG & Type PDF Document Tags

IC 74161

Abstract: lm 74161 (see Figure B). For conventional operation of 74160, 74161 and 74163, the following transitions should , Count (HHHH for '161 and HLLH for ' 160). (b) The HIGH-to-LOW transition of CEP or CET on the 74161 and , e tta b le d e ca de (74160, 74LS160A, 74LS162A) and 4-bit (74161, 74LS161A, 74163, 74LS163A , operation is pro vided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The Clock input is buffered. The outputs of the counters may be preset to HIGH or LOW level. A
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LS160A IC 74161 lm 74161 IC 74160 IC 74160 decade counter diagram ic 74163 74161/74160 function table LS161A LS162A LS163A N74160N N74LS160AN

ic 74160

Abstract: IC 74160 decade counter diagram enable the next cascaded stage (see Figure B). For conventional operation of 74160, 74161 and 74163, the , Terminal Count (HHHH for '161 and HLLH for '160). (b) The HIGH-to-LOW transition of CEP or CET on the 74161 , transition of PE on the 74161 and 74160 should only occur while CP is HIGH for conventional operation. (d , Signetics 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A Counters Logic Products '160 , -bit (74161, 74LS161 A, 74163, 74LS163A) counters feature an internal carry look ahead and can be used for
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pin diagram of ic 74163 diagram of IC 74160 of 74160 ic LM 74160 diagram of IC 74161 H C 5287 equivalent 54LS/74LS S4LS/74LS F08270S

74LS163DC

Abstract: 74LS163D 161 â'¢ 163 /O fO ^ % 3 / 0 > 0 CO NNECTIO N DIAGRAM PINOUT A , dividers and have tw o types of C ount Enable inputs plus a Ter­ minal Count output for versatility in , edge of the clock. For functional description and detail specifications please refer to the â'™160 , â'™161 "SR fo r â'™163 LO G IC SYMBOL 9 PIN OUT 5 6 PE Po Pi P2 P3 CET T
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74LS163DC 74LS163D MLS/74LS161 4LS/74 LS163 74163PC 74LS163PC 74161DC

Truth Table 74160

Abstract: Truth Table 74161 . The LOW -to-HIGH transition of SPE on the 54/74161 and 54/74160 should only occur w hile CP is high , to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite , (SEU) Immunity < 2 x 10"9 Errors/Bit-Day (Typ) level of reliability. The Harris HCTS160T is a , the low-to-high transition of the clock. A low level on the synchronous parallel enable input, SPE , discharge; follow proper IC Handling Procedures. 1-800-4-H AR R IS | C opyright © Harris C orporation 1999
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Truth Table 74160 Truth Table 74161 MIL-PRF-38535 HCTS160 TA14445A 1-800-4-HARRIS

Truth Table 74161

Abstract: ark of Harris C orporation. HCTS160T Functional Diagram PO P1 P2 P3 TRUTH TABLE , HLLH for 160). 2. The H IG H-to-LO W transition of PE or TE on the 54/74161 and 54/74160 should only , devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large , - Single Event Upset (SEU) Immunity < 2 x 10"9 Errors/Bit-Day (Typ) level of reliability. The , accomplished synchronously with the low-to-high transition of the clock. A low level on the synchronous
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1-800-4-HARR

Truth Table 74160

Abstract: IC 74160 atellite A pplications FlowTM (SAF) is a tradem ark of Harris C orporation. HCTS160T Functional Diagram , transition of PE or TE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation. 3. The LOW -to-HIGH transition of SPE on the 54/74161 and 54/74160 should only occur w hile CP is , intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Harris HCTS160T is a Radiation Hardened High Speed Presettable
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IC 74160

Abstract: Truth Table 74161 . The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation. 3. The LOW-to-HIGH transition of SPE on the 54/74161 and 54/74160 should , standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil HCTS160T is a Radiation Hardened , low-to-high transition of the clock. A low level on the synchronous parallel enable input, SPE, disables
Intersil
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data sheet IC 74161 IC 74160 DATA SHEET logic diagram of 74160 CDFP4-F16 HCTS160DTR HCTS160KTR FN4626 ISO9000

Truth Table 74160

Abstract: IC 74160 trademark of Intersil Corporation. HCTS160T Functional Diagram P0 P1 3 P2 4 P3 5 6 , HLLH for 160). 2. The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation. 3. The LOW-to-HIGH transition of SPE on the 54/74161 , standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil HCTS160T is a Radiation Hardened
Intersil
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4626 74161 truth table

sn 74373

Abstract: SN 74114 graphic and text designs S chem atic captu re with Valid Logic's V alidG KD or V iew log ic's V iew d ra w , relational operations Full A lte ra /V a lid Logic and A l te r a /V ie w lo g ic cro ss-com patibility via , V ie w log ic V iew sim chip- and board-level sim ulators or with Logic A u to m a tio n 's S m artM , , Valid L ogic and V iew logic library 9 Figure 1. PLS-WS/SN Block Diagram Valid Logic/Viewlogic , are entered either with V a lid G E D by Valid Logic or with V ie w d raw by V iew log ic (see Figure
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sn 74373 SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC QIC-24

74191, 74192, 74193 circuit diagram

Abstract: IC 7402, 7404, 7408, 7432, 7400 a rd w a re Figure 1. PLS-WS/HP Block Diagram Device Simulation Board Simulation - Shading , pplications for the most up-to-date list of m appings. Table 2. Mentor Graphics Library Mapping File-Macrofunctions (P arti of 3) Mentor Graphics 74LSTTL Function 74LS00 74LS02 74LS04 74LS08 74LS10 74LS11 74LS20 , /HP Data Sheet Table 2. Mentor Graphics Library Mapping File-Macrofunctions (Part 2 of 3 , 74147 74148 74151 74153 74154 74155 74156 74157 74158 74160 74161 74162 74163 74164 74165 74166 74168
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74191, 74192, 74193 circuit diagram counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions counter 74168 74191, 74192, 74193 HP400 IC-24

14 pin ic 7404

Abstract: sn 7404 n ic diagram diagram of ( l) a r e a + 12 V Ri = lk f i C, = 5 0 0 p F CK Q D Q L 1 I ( System Configuration , IC l IC 2. 5.6 IC 3 IC4 IC 7. 8.9 SN 74132 SN 74107 SN 7404 SN 7474 SN 74161 OS Vss NC NC Vss , . Output non-uniformity ± 10% of Vqut MAX 3. 2048 photoelements on a single chip ; Photo ele ment size 14 , Inspection machines 8. 22 pin dual-in-line package (CERDIP) Block Diagram SHARP 452 CCD Linear , AX - X 100, X ; average output of PRNU all elem ents, ^ X ; difference be tw een signal output and X
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LZ2019 14 pin ic 7404 sn 7404 n ic diagram pin DIAGRAM OF IC 7474 7474 ic pin configuration pin configuration of ic 7404 7404 ic diagram
Abstract: terminal count (HHHH for 161 and HLLH for 160) 2. The HIGH-to-LOW transition of PE or T E o n the 54/74161 , transition of SPE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation , are accomplished synchro­ nously with the low-to-high transition of the clock. A low level on the , device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS160MS is supplied , I.C. Handling Procedures. Copyright © H arris C orporation 1992 _ 7-351 File Number -
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MIL-STD-1835 CDIP2-T16

14 pin ic 7404

Abstract: pin DIAGRAM OF IC 7474 ' OS' J\ ( ti>40ns t5>10ns Enlarged diagram of (l)area System Configuration Example lkn -y^i DO-H , SN 74161 CK Q Q CLR 1 CK Q Q CLR IC9 CIC Q Q CLR zir- cK RC E(P,T) ABCD L r IC, a CK Q D Q C1 DS , one output amplifier. â  Features 1. Dynamic range 1000 TPY. 2. Output non-uniformity ±10% of Vout , package (CERDIP) â  Block Diagram LZ2019 Pin Connections 452 SHARP» SHARP ELEK/ MELEC DIV 1SE 0 I , output voltage VsAT 0.8 1.2 - V Photoresponse Non-uniformity PRNU AX - ^ X100, X ; average output of all
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CI 7474 IC 7474 ic 74132 pin DIAGRAM OF IC 7404 ic 7474 pin diagram CI 74107 T-41-55 L12-1-2

MSM6999

Abstract: 74164 with ic PIN DIAGRAM MSM6996H/6996V/6997H/6997V/6998/6999 Example of Multi-Channel Connections (8ch) +5 V 74161(1) 2 1 , CMOS ICs containing filters for A/D and D/A converting of the voice signal ranging from 300 Hz to 3400 , /MSM6997V/MSM6999 : m-law · Capable of independent operation of transmission and reception · Transmission clock in the range of 64 kHz to 2048 kHz · Adjustable transmit gain · 600 W drive for analog output , ) 1/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 BLOCK DIAGRAM MSM6996H/V
OKI Electric Industry
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MSM6999 74164 with ic PIN DIAGRAM IC 74164 V74161 pin diagram of ic 74164 ic 74164 data sheet E2U0010-28-81 MSM6996H/MSM6996V/MSM6998 MSM6997H/MSM6997V/MSM6999 MSM6996H/MSM6996V/MSM6997H/MSM6997V MSM6998/MSM6999 MSM6996V/MSM6997V

MSM6999

Abstract: IC 74164 .3 No.8 Example of Multi-Channel Timing 74161(1) QC Output 74161(2) QB Output QA 74164 Output , CMOS ICs containing filters for A/D and D/A converting of the voice signal ranging from 300 Hz to 3400 , /MSM6997V/MSM6999 : m-law · Capable of independent operation of transmission and reception · Transmission clock in the range of 64 kHz to 2048 kHz · Adjustable transmit gain · 600 W drive for analog output , ) 1/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 BLOCK DIAGRAM MSM6996H/V
OKI Electric Industry
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MSM6999AS 74161 MSM6997 M4520 DIP16-P-300-2 MSM6996HRS/MSM6997HRS MSM6996VRS/MSM6997VRS MSM6998RS/MSM6999RS DIP16-G-300-2 MSM6996HAS/MSM6997HAS

16CUDSLR

Abstract: 7474 D flip flop free PL D s H ierarch ical d esig n entry m eth o d s for b oth g rap h ic and text d esig n s M u , , arithm etic and relational op eration s D elay p red iction and tim ing an aly sis fo r g ra p h ic an d , create, verify, and program com p lex logic d esig n s. Figure 1 sh o w s a b lock d iagram of M A X +P L U S . Figure 1. MAX+PLUS Block Diagram MAX+PLUS Design Processing (Compiler) T h e P L D S-M , ith a variety of d esign entry m ethods. M A X +P L U S su p p orts hierarch ical en try o f b oth G
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16CUDSLR 7474 D flip flop free alu 74382 pin diagram of ic 74190 ALU IC 74381 HFJV1

74160 pin layout

Abstract: HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation 3. The LOW-to-HIGH transition of SPE on the 54/74161 and 54/74160 should only occur , parallel presetting are accomplished synchro nously with the iow-to-high transition of the clock. A low , achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic , . Users should follow p roper I.C. Handling Procedures. Copyright © H arris C orporation 1992 7 351
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74160 pin layout

IC 74160

Abstract: -to-HIGH transition of SPE on the 54/74161 and 54/74160 should only occur while CP is high for conventional , static burn-in 2. Each pin except VCC and GND will have a resistor of 1 K ii ± 5% for dynam ic burn-in , Pinouts 16 LEAD CERAM IC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) M IL-STD-1835 CDIP2-T16, LEAD FINISH C , Input Logic Levels -VIL = 30% of VCC Max -VIH = 70% of VCC Min · Input Current Levels li < 5 ^ @ VOL , . Counting and parallel presetting are accomplished synchronously with the lowto-high transition of the clock
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HCS160MS

Truth Table 74161

Abstract: 74161 pin diagram and truth table . The LOW-to-HIGH transition of SPE on the 54/74161 and 54/74160 should only occur while CP is high for , . Counting and parallel presetting are accomplished synchronously with the lowto-high transition of the clock , high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The H C T S 16 0M S is s u p p lie d in a 16 lead C e ra m ic fla tp a c k (K su ffix) or a S BD IP P , electrostatic discharge. Users should tollow proper I.C. Handling Procedures. Copyright ©Harris Corporation 1995
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74161 pin diagram and truth table CTS160
Abstract: 161 and HLLH for 160) 2. The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/74160 should , transition of the c lock. A low level on the synchronous parallel enable input, SPE, disables counting and , CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The H C T S 1 6 0 M S is s u p p lie d in a 16 lead C e ra m ic fla tp a , v ic e s a re s e n s itiv e to e le c tro s ta tic d is c h a rg e . U s e rs s h o u ld fo llo w p -
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