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MSP-TS430RGC64USB Texas Instruments MSP430F55xx 64-Pin Target board only ri Buy
MSP-FET430U64USB Texas Instruments MSP430F55xx 64-Pin FET tool and target board combination ri Buy
SN74LS31DRE4 Texas Instruments IC ACTIVE DELAY LINE, TRUE OUTPUT, PDSO16, PLASTIC, SOP-16, Delay Line ri Buy

delay 64us

Catalog Datasheet Results Type PDF Document Tags
Abstract: IN TRAP 14 DL(R-Y) Delay (R-Y) SG18 : 1VP-P 15 5V, 12 5V, 7 0V 15 DL(B-Y) Delay (B-Y) SG16 : 1VP-P 15 5V, 12 0V, 7 0V 16 GH(R-Y) Gain (R-Y) VCA:Hi SG18 , calculation method Measure the current to flow in pin 11 5V 5µs SG2 0V 64µs 3 4 5 1V SG18 SG17 SG16 52µs 2µs 0V 10µs E Output at pin 15 5V 5µs SG2 0V 64µs , method 5V 5µs SG2 0V 10 11 64µs Output at pin 15 VS 0.5VP-P 0V SG14 ... Original
datasheet

22 pages,
233.34 Kb

SG14 RGB to NTSC/PAL Encoder M52390FP delay 64us 64us delay line 20P2N-A 20P2N SG16 TH317 M52390FP abstract
datasheet frame
Abstract: of command blocks within a time period ranging from 64µs to 4.194s. The minor frame scheduling is , frame block that includes the execution time of the MIL-STD-1553 MIL-STD-1553 message and an additional 2ms delay , delay, outside of a minor frame block, the SKIP command block can be protected by surrounding it with , second LMFT command shown in command block #4 will delay subsequent command execution until the original , the LMFT command in command block #2 is loaded with a value smaller than the SKIP delay and is ... Original
datasheet

10 pages,
54.45 Kb

1553 bus Diode SMD SJ02 MM023A MM026 sj02 UT69151 RT 0100 MM024A Tj02 MM011A 1553 SUmmit MM010A MM025A MM027A MM012A UT69151 abstract
datasheet frame
Abstract: (time point 2). After a 64µs delay, RESET is pulled low. The RESET delay allows the PWRGD signal to be , goes high. On power failure, RESET will go low 64µs after PWRGD goes low. REF (Pin 8): The Reference , 4). After a 200ms delay, RESET is pulled high. The weak pull-up current source to VCCLO on PWRGD , VOUTLO B V1 LTC1421 LTC1421 ­12V 0V PWRGD VEE 64µs ­12V RESET ~1ms ~1ms Figure 5. Negative Supply Control 200ms < 64µs < 200ms 200ms 1421 F05 1421 F07 Figure 7. ... Original
datasheet

20 pages,
385.83 Kb

zener 24.5v 2w ASD10-48D12 LTC1421 LTC1421CG LTC1421CSW MMDF2N02E MTB50N06E QS3384 Si4936DY 64us delay line cricuit breaker LT1074CT LS7004 LS7404 LTC1421 abstract
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Abstract: wave and pulse can be input as a subcarrier. · Built-in band pass filter for the C signal and delay , G-OUT Y/C MIX B-OUT REGULATOR DELAY SYNC ADD MATRIX CLAMP BPF R-Y Modulator , /C MIX CLAMP 18 20k NTSC S5 SIN-PULSE DELAY 47µ 5V 19 VIDEO OUT , SYNC IN 2.0V 64µs 0.8V 4.5µs 10µs SG1 RIN 0.8V 1.0Vp-p SG2 GIN 64µs , 2.0V 64µs 0.8V 4.5µs 10µs SG1 RIN Fig. 3 fc = 20log 1.0Vp-p SG2 GIN VO ... Original
datasheet

14 pages,
296.26 Kb

transistor BC 337 220u 16v capacitor 220u capacitance pin diagram 24PIN B100 .47k capacitor image CXA1645P G100 SG3 100 CXA1645 rgb composite rgb-Composite Sync cxa1645m CXA1645P/M CXA1645P/M CXA1645P/M abstract
datasheet frame
Abstract: CXL5506M/P CXL5506M/P CMOS-CCD 1H Delay Line for PAL Description The CXL5506M/P CXL5506M/P are CMOS-CCD delay line ICs that provide 1H delay time for PAL signals including the external low-pass filter. CXL5506M CXL5506M 8 pin , 500mV 150mV 1H 64µs Input waveform (5) The internal clock component to the output signal , meter, in BPF 100kHz to 5MHz, Sub Carrier Trap mode. 175mV 325mV 150mV 1H 64µs Input , 330k 1000p 1k 470 27p Delay time 190ns LPF 5V 2200 Transistor used NPN ... Original
datasheet

9 pages,
105.6 Kb

CXL5506P CXL5506M 2SC2785 2SA1175 CXL5506M/P CXL5506M/P abstract
datasheet frame
Abstract: CXL5505M/P CXL5505M/P CMOS-CCD 1H Delay Line for PAL Description The CXL5505M/P CXL5505M/P are CMOS-CCD delay line ICs that provide 1H delay time for PAL signals including the external low-pass filter. CXL5505M CXL5505M 14 pin , 5-staircase wave is fed. 150mV 350mV 500mV 150mV 1H 64µs Input waveform (5) The internal clock , 150mV 1H 64µs Input waveform Clock fsc (4.433619MHz) sine wave 0.3 to 1.0Vp-p (0.5Vp-p typ. , Delay time 190ns LPF 5V 2200 Transistor used NPN: 2SC2785 2SC2785 2200 2200 (ex. ... Original
datasheet

9 pages,
123.29 Kb

CXL5505P CXL5505M clamp meter circuit diagram 4 npn transistor ic 14pin 2SC403 2SC2785 2SA1175 CXL5505M/P CXL5505M/P abstract
datasheet frame
Abstract: CXL5506M/P CXL5506M/P CMOS-CCD 1H Delay Line for PAL For the availability of this product, please contact the sales office. Description The CXL5506M/P CXL5506M/P are CMOS-CCD delay line ICs that provide 1H delay time , 5-staircase wave is fed. 150mV 350mV 500mV 150mV 1H 64µs Input waveform (5) The internal clock , 150mV 1H 64µs Input waveform Clock 4fsc (17.734475MHz) sine wave 0.3 to 1.0Vp-p (0.5Vp-p , (Inverted signal) 3 6 10 560k 1µ 330k 1000p 1k 470 27p Delay time 190ns ... Original
datasheet

9 pages,
103.6 Kb

CXL5506P CXL5506M 2SC2785 2SA1175 CXL5506M/P CXL5506M/P abstract
datasheet frame
Abstract: CXL5505M/P CXL5505M/P CMOS-CCD 1H Delay Line for PAL For the availability of this product, please contact the sales office. Description The CXL5505M/P CXL5505M/P are CMOS-CCD delay line ICs that provide 1H delay time , 1H 64µs Input waveform (5) The internal clock component to the output signal during no-signal , BPF 100kHz to 5MHz, Sub Carrier Trap mode. 175mV 325mV 150mV 1H 64µs Input waveform , 2 1µ 4 11 5 10 1k 470 7 8 27p Delay time 190ns LPF 5V ... Original
datasheet

9 pages,
119.46 Kb

CXL5505P CXL5505M 4 npn transistor ic 14pin 2SC403 2SC2785 2SA1175 CXL5505M/P CXL5505M/P abstract
datasheet frame
Abstract: CXL5515M/P CXL5515M/P CMOS-CCD 1H Delay Line for PAL Description The CXL5515M/P CXL5515M/P are CMOS-CCD delay line ICs designed for processing video signals. This ICs provide a 1H delay time for PAL chroma signals including the external lowpass filter. Features · Single 5V power supply · Low power consumption · Built-in , 500mV 150mV 1H 64µs 5. Leakage of internal clock components and related high frequency component , noise meter, in BPF 100kHz to 5MHz, Sub Carrier Trap mode. 175mV 325mV 150mV 1H 64µs CLOCK ... Original
datasheet

9 pages,
140.11 Kb

CXL5515P CXL5515M 2SC403 2SA403 CXL5515M/P CXL5515M/P abstract
datasheet frame
Abstract: CXL5514M/P CXL5514M/P CMOS-CCD 1H Delay Line for PAL Description The CXL5514M/P CXL5514M/P are CMOS-CCD delay line ICs designed for processing video signals. This ICs provide a 1H delay time for PAL signals including the external lowpass filter. Features · Single 5V power supply · Low power consumption · Built-in , wave is fed. 150mV 350mV 500mV 150mV 1H 64µs 5. Leakage of internal clock components and , 150mV 1H 64µs CLOCK fSC (4.433619MHz) Sine wave 400mVp-p (Typ.) ­4­ ­5­ 50% white ... Original
datasheet

9 pages,
141.59 Kb

CXL5514P CXL5514M 2SC403 2SA403 4.433619MHZ CXL5514M/P CXL5514M/P abstract
datasheet frame

Datasheet Content (non pdf)

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Baseband ICs Part Function Key Features Package U3665M U3665M U3665M U3665M TV baseband delay line Alignment-free integrated 64µs delay DIP16 DIP16 DIP16 DIP16, SO16 U3666M U3666M U3666M U3666M TV baseband delay line Improved version of U3665M U3665M U3665M U3665M (latch up) DIP16 DIP16 DIP16 DIP16, SO16
www.datasheetarchive.com/files/temic/hn/communic/base.htm
Temic 20/11/1998 1.52 Kb HTM base.htm
/Crosspoints Switching Regulation Timing Circuits Video Voltage Reference HS-139RH HS-139RH HS-139RH HS-139RH Prop Delay. View Online Answer Id: 3835 Question What are some Prop Delay representative points? Answer Here 50mV, 1.7uS, 6.4uS 90mV, 1.5uS, 6.0uS As you delay. This was with a 5Kohm and approx 50pF load, bench setup. Load resistor has a substantial
www.datasheetarchive.com/files/intersil/device_pages/faq_3835.html
Intersil 13/10/2005 9.04 Kb HTML faq_3835.html
Control Logic Function for Local and Global Modes Low Port-to-Port Data Propagation Delay Drives and TEST low. While in the self-exerciser mode, a 6.4-us packet is generated of consistent preamble on the GTX driver port with a 6.4-us idle time. The GTX driver, with the help of loop back connectors
www.datasheetarchive.com/files/texas-instruments/data/html/slls150a.htm
Texas Instruments 31/05/1997 9.17 Kb HTM slls150a.htm
Function for Local and Global Modes Low Port-to-Port Data Propagation Delay Drives Twisted-Pair invoked by pulling both GLOBAL and TEST low. While in the self-exerciser mode, a 6.4-us packet is generated of consistent preamble on the GTX driver port with a 6.4-us idle time. The GTX driver, with the
www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/datasht/slls150a.htm
Texas Instruments 01/06/1998 12.99 Kb HTM slls150a.htm
No abstract text available
www.datasheetarchive.com/download/23106712-844026ZC/an1083.zip (CST_CC.ASM)
STMicroelectronics 19/12/2000 26.58 Kb ZIP an1083.zip
No abstract text available
www.datasheetarchive.com/download/90015441-845096ZC/an1083.zip (CST_CC.ASM)
STMicroelectronics 25/05/2000 26.58 Kb ZIP an1083.zip
No abstract text available
www.datasheetarchive.com/download/98588234-314023ZC/an1731sw.zip (AN1731.pdf)
KyteLabs 11/06/2002 173.75 Kb ZIP an1731sw.zip
No abstract text available
www.datasheetarchive.com/download/59753275-93224ZC/mc9s12dp256b.zip (S12BDLCV1.pdf)
Elektronikladen 27/01/2004 3575.98 Kb ZIP mc9s12dp256b.zip
No abstract text available
www.datasheetarchive.com/download/25147629-314048ZC/9s12dt128b-zip.zip (S12BDLCV1.pdf)
KyteLabs 11/06/2002 3525.16 Kb ZIP 9s12dt128b-zip.zip
No abstract text available
www.datasheetarchive.com/download/44857794-314047ZC/9s12dp256b-zip.zip (S12BDLCV1.pdf)
KyteLabs 11/06/2002 3199.39 Kb ZIP 9s12dp256b-zip.zip