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Part Manufacturer Description Datasheet BUY
1N4964US Microsemi Corporation Zener Diode, 18V V(Z), 5%, 5W, Silicon, Unidirectional, HERMETIC SEALED, GLASS, D58, 2 PIN visit Digikey Buy
JAN1N4464US Microsemi Corporation Zener Diode, 9.1V V(Z), 5%, 1.5W, Silicon, Unidirectional, HERMETIC SEALED, GLASS PACKAGE-2 visit Digikey Buy
JAN1N6164US Microsemi Corporation Trans Voltage Suppressor Diode, 1500W, 62.2V V(RWM), Unidirectional, 1 Element, Silicon, MELF-2 visit Digikey Buy
JAN1N4964US Microsemi Corporation Zener Diode, 18V V(Z), 5%, 5W, Silicon, Unidirectional, HERMETIC SEALED, GLASS PACKAGE-2 visit Digikey Buy
JANTX1N6464US Microsemi Corporation Trans Voltage Suppressor Diode, 500W, 15V V(RWM), Unidirectional, 1 Element, Silicon, SURFACE MOUNT PACKAGE-2 visit Digikey Buy
JANTX1N4964US Microsemi Corporation Zener Diode, 18V V(Z), 5%, 5W, Silicon, Unidirectional, HERMETIC SEALED, GLASS PACKAGE-2 visit Digikey Buy

delay+64us

Catalog Datasheet MFG & Type PDF Document Tags

TH317

Abstract: SG16 calculation method Measure the current to flow in pin 11 5V 5us SG2 0V 64us 3 4 5 1V SG18 SG17 SG16 52us 2us 0V 10us E Output at pin 15 5V 5us SG2 0V 64us , method 5V 5us SG2 0V 10 11 64us Output at pin 15 VS 0.5VP-P 0V SG14 , 5us SG2 0V 64us 1V SG18 (SG16) 0V Output at pin 52us 2us 14 (15) 10u , 0V 64us VnH 20 21 22 Output at pin V(n+1)H 10B VB1=VnH VB2=VnH VB3=VnH - V(n
Mitsubishi
Original

280NS

Abstract: 37CH TABLE 4 ) (PAL) 560nS 2.8uS CONV TRIG 840nS 6.4uS (MM) H TRIG 3.1uS (MF) 2.8uS 3.9uS CP 1.7uS 560nS 8.7uS PRE BL 840nS 6.4uS (MM) B BL (NTSC) 980nS CK
Sony
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BL19

Abstract: IC 41 BF BLKG VARIABLE RANGE ( SEE TABLE 4 ) (PAL) 560nS 2.8uS CONV TRIG 840nS 6.4uS (MM) H TRIG 3.1uS (MF) 2.8uS 3.9uS CP 1.7uS 560nS 8.7uS PRE BL 840nS 6.4uS (MM
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LS7404

Abstract: 12v DC ,2A power supply circuit go low 64us after PWRGD goes low. REF (Pin 8): The Reference Voltage Output. VOUT = 1.232V ±1%. , goes high, and PWRGD is immediately pulled low (time point 2). After a 64us delay, RESET is pulled , below the reset threshold for less than 64us, the PWRGD output will trip, but again the RESET output , V2 VOUTLO V1 RESET TIMING PWRGD 64us 200ms < 64us < 200ms 200ms Figure 7 , monitor trip voltage to 4.65V. However, if the FB pin is pulled to ground for more than 64us via a push
Linear Technology
Original

CXA2075M

Abstract: cxa2075 64us 0.8V 4.5us 10us SG1 RIN 0.8V 1.0Vp-p SG2 GIN 64us 1.0Vp-p 4.5us , 1.0Vp-p SYNC IN f = 200kHz/27MHz DEF BC point ROUT GOUT BOUT YOUT CVOUT 2.0V 64us , / 4.43MHz SG4 SYNC IN R/BN = VO (BN) VO (CG) VO (CB) VO (CR) tD (B) 64us 0.8V A point
Sony
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LS7404

Abstract: LT1074CT 200ms after PWRGD goes high. On power failure, RESET will go low 64us after PWRGD goes low. REF (Pin , VOUTLO B V1 LTC1421 ­12V 0V PWRGD VEE 64us ­12V RESET ~1ms ~1ms Figure 5. Negative Supply Control 200ms < 64us < 200ms 200ms 1421 F05 1421 F07 Figure 7 , (time point 2). After a 64us delay, RESET is pulled low. The RESET delay allows the PWRGD signal to be , is not affected (time point 3). If VOUTLO drops below the reset threshold for less than 64us, the
Linear Technology
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LS7404 LT1074CT LS7004 cricuit breaker 64us delay line Si4936DY LTC1155 LTC1477/LTC1478

f25n05l

Abstract: F25NO5L . There is nothing sacred about the delay period. We set the TMR0 prescaler to 64us. The 15us delay , negative duty cycle duration and toggles the output pin. As long as the delay routine is called every 64us , over then the output ; (GPIO,OUTPUT) is toggled. The value in DUTY_CYC is the number ; of 64us periods that GPIO,OUTPUT stays low. The complement ; of DUTY_CYC is the number of 64us periods that GPIO
Microchip Technology
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f25n05l F25NO5L F25N05L TRANSISTOR REPLACEMENT F25n05 2N3904 H05 12c508 POTENTIOMETER PIC12CXXX DS40160A/2

2SA403

Abstract: 434M a vector scope when the 5-staircase wave is fed. 150mV 350mV 500mV 150mV 1H 64us 5 , Carrier Trap mode. 175mV 325mV 150mV 1H 64us CLOCK fSC (4.433619MHz) Sine wave 400mVp
Sony
Original
CXL5515M CXL5515P 2SA403 434M 2SC403 4.433619 4.433619MHZ CXL5515M/P 433619MH DIP-8P-01 DIP008-P-0300-A

UT69151DXE

Abstract: 1553 SUmmit within a time period ranging from 64us to 4.194s. The minor frame scheduling is frequently used to , message error occurs, the first LMFT will be loaded with a 64us time out value. Immediately following , frame timer with a time out value of 64us. Since the SKIP command will be executed before the minor , (RTXX T SA1 WC32) #1 Load MFT = 64us #2 SKIP = 1.94ms #3 Load MFT = 0ns #4 1553
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UT69151 UT69151DXE 1553 SUmmit Tj02 MM011A RT 0100 MIL-STD-1553

4.433619MHZ

Abstract: 2SC403 -staircase wave is fed. 150mV 350mV 500mV 150mV 1H 64us 5. Leakage of internal clock components and , 150mV 1H 64us CLOCK fSC (4.433619MHz) Sine wave 400mVp-p (Typ.) ­4­ ­5­ 50% white
Sony
Original
CXL5514M CXL5514P CXL5514M/P

CCD SMD

Abstract: (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4us). SUB is output at the , 18MHz). This chart shows a period of 115ck (6.4us). SUB is output at the timing shown above when output , approximately 3.1 to 10.4us (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4us). , period of 115ck (6.4us). Chart-7 Quadruple-speed mode · ICX224 Horizontal Direction Timing Chart , frequency is 18MHz). This chart shows a period of 115ck (6.4us). Chart-8 · ICX232 Vertical Direction
Sony
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CCD SMD CXD2470R 2020K 1250K 48PIN LQFP-48P-L01 LQFP048-P-0707

d14 smd

Abstract: Sony ICX 252 the drive frequency is 18MHz). This chart shows a period of 115ck (6.4us). SUB is output at the , chart shows a period of 115ck (6.4us). SUB is output at the timing shown above when output is , to 10.4us (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4us). SUB is , to 13.4us (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4us). Logic , 18MHz). This chart shows a period of 115ck (6.4us). 56 72 88 104 120 136 152 168 1071 MODE
Sony
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ICX284 ICX202 d14 smd Sony ICX 252 sony icx P-LQFP48-7 42/COPPER P-LQFP48-7X7-0 LQFP-48P-L282

2SA403

Abstract: 2SC403 500mV 150mV 1H 64us 5. Leakage of internal clock components and related high frequency component , noise meter, in BPF 100kHz to 5MHz, Sub Carrier Trap mode. 175mV 325mV 150mV 1H 64us CLOCK
Sony
Original

Sony ICX 252

Abstract: SONY icx the drive frequency is 18MHz). This chart shows a period of 115ck (6.4us). SUB is output at the , chart shows a period of 115ck (6.4us). SUB is output at the timing shown above when output is , to 10.4us (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4us). SUB is , to 13.4us (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4us). Logic , 18MHz). This chart shows a period of 115ck (6.4us). 56 72 88 104 120 136 152 168 1071
Sony
Original
CXA2006Q ICX224/ICX284 ICX202/ICX232

cxa1645m

Abstract: rgb-Composite Sync 2.0V SG5 SYNC IN 2.0V 64us 0.8V 4.5us 10us SG1 RIN 0.8V 1.0Vp-p SG2 GIN 64us 1.0Vp-p 4.5us Fig. 1 SG3 1.0Vp-p BIN SG1 to 3 RIN 2.5V GIN BIN 1.0Vp , YOUT CVOUT 2.0V 64us 0.8V 4.5us 10us SG1 RIN Fig. 3 fc = 20log 1.0Vp-p SG2 , -p SCIN f = 3.58MHz/ 4.43MHz VO (BN) VO (CG) VO (CB) VO (CR) tD (B) 64us 0.8V A point
Sony
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CXA1645P 24PIN cxa1645m rgb-Composite Sync rgb composite pal video sync generator CXA1645 CXA1645P/M CXA1645M DIP-24P-01 DIP024-P-0400-A

Sony ICX 238

Abstract: Sony ICX 252 the drive frequency is 18MHz). This chart shows a period of 115ck (6.4us). SUB is output at the , chart shows a period of 115ck (6.4us). SUB is output at the timing shown above when output is , to 10.4us (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4us). SUB is , to 13.4us (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4us). Logic , 18MHz). This chart shows a period of 115ck (6.4us). 56 72 88 104 120 136 152 168 1071 MODE
Sony
Original
Sony ICX 238 CCD ICX 252 L282 smd code D39 ccd image sensor sony

clamp meter circuit diagram

Abstract: 2SC403 . 150mV 350mV 500mV 150mV 1H 64us 5. Leakage of internal clock components and related high , noise meter, in BPF 100kHz to 5MHz, Sub Carrier Trap mode. 175mV 325mV 150mV 1H 64us CLOCK
Sony
Original
clamp meter circuit diagram

CCD SMD

Abstract: CXA2006 (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4us). SUB is output at the , 18MHz). This chart shows a period of 115ck (6.4us). SUB is output at the timing shown above when output , approximately 3.1 to 10.4us (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4us). , period of 115ck (6.4us). Chart-7 Quadruple-speed mode · ICX224 Horizontal Direction Timing Chart , frequency is 18MHz). This chart shows a period of 115ck (6.4us). Chart-8 · ICX232 Vertical Direction
Sony
Original
CXA2006 sck 104 Ternary CAM

SAE J2190

Abstract: sae j2178 part 1 64us. The bus can transition from a low potential to a high potential, or visa-versa; but it is the , symbol is. In this case, if the bus remains in its high potential for 64us, then we would consider the symbol to be a "one" bit. VPW J1850 protocol defines a high potential bus driven for 64us as a "dominant , long low potential on the J1850 bus. A dominant one bit symbol is a 64us long high potential on the J1850 bus. Conversely, a passive zero bit symbol is a 64us long low potential on the J1850 bus and a
Intel
Original
SAE J2190 sae j2178 part 1 sae j2178 sae j1850 pwm controller sae j2178 2 J2178 MAY94 J2178/1 J2178/2 J2178/3 J2178/4 SP-1070

1u 5V

Abstract: 2SA1175 500mV 150mV 1H 64us Input waveform (5) The internal clock component to the output signal , meter, in BPF 100kHz to 5MHz, Sub Carrier Trap mode. 175mV 325mV 150mV 1H 64us Input
Sony
Original
CXL5506M CXL5506P 1u 5V 2SA1175 2SC2785 CXL5506M/P DIP008-P-0300
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