NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: IN TRAP 14 DL(R-Y) Delay (R-Y) SG18 : 1VP-P 15 5V, 12 5V, 7 0V 15 DL(B-Y) Delay (B-Y) SG16 : 1VP-P 15 5V, 12 0V, 7 0V 16 GH(R-Y) Gain (R-Y) VCA:Hi SG18 , calculation method Measure the current to flow in pin 11 5V 5us SG2 0V 64us 3 4 5 1V SG18 SG17 SG16 52us 2us 0V 10us E Output at pin 15 5V 5us SG2 0V 64us , method 5V 5us SG2 0V 10 11 64us Output at pin 15 VS 0.5VP-P 0V SG14 ... | Original |
22 pages, |
SG14 RGB to NTSC/PAL Encoder M52390FP delay 64us 20P2N-A SG16 TH317 M52390FP abstract |
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| Abstract: of command blocks within a time period ranging from 64us to 4.194s. The minor frame scheduling is , frame block that includes the execution time of the MIL-STD-1553 MIL-STD-1553 message and an additional 2ms delay , delay, outside of a minor frame block, the SKIP command block can be protected by surrounding it with , second LMFT command shown in command block #4 will delay subsequent command execution until the original , the LMFT command in command block #2 is loaded with a value smaller than the SKIP delay and is ... | Original |
10 pages, |
UT69151 sj02 Diode SMD SJ02 1553 bus RT 0100 MM024A MM011A 1553 SUmmit MM010A MM023A MM025A MM027A MM012A MM026A MM013A UT69151 abstract |
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| Abstract: (time point 2). After a 64us delay, RESET is pulled low. The RESET delay allows the PWRGD signal to be , goes high. On power failure, RESET will go low 64us after PWRGD goes low. REF (Pin 8): The Reference , 4). After a 200ms delay, RESET is pulled high. The weak pull-up current source to VCCLO on PWRGD , VOUTLO B V1 LTC1421 LTC1421 12V 0V PWRGD VEE 64us 12V RESET ~1ms ~1ms Figure 5. Negative Supply Control 200ms < 64us < 200ms 200ms 1421 F05 1421 F07 Figure 7. ... | Original |
20 pages, |
zener 24.5v 2w LTC1421 LTC1421CG LTC1421CSW MMDF2N02E MTB50N06E QS3384 Si4936DY 64us delay line LT1074CT cricuit breaker LS7004 LS7404 LTC1421 abstract |
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| Abstract: wave and pulse can be input as a subcarrier. · Built-in band pass filter for the C signal and delay , G-OUT Y/C MIX B-OUT REGULATOR DELAY SYNC ADD MATRIX CLAMP BPF R-Y Modulator , /C MIX CLAMP 18 20k NTSC S5 SIN-PULSE DELAY 47u 5V 19 VIDEO OUT , SYNC IN 2.0V 64us 0.8V 4.5us 10us SG1 RIN 0.8V 1.0Vp-p SG2 GIN 64us , 2.0V 64us 0.8V 4.5us 10us SG1 RIN Fig. 3 fc = 20log 1.0Vp-p SG2 GIN VO ... | Original |
14 pages, |
transistor BC 337 G100 CXA1645P B100 24PIN .47k capacitor image rgb-Composite Sync CXA1645 cxa1645m CXA1645P/M CXA1645P/M abstract |
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| Abstract: CXL5505M/P CXL5505M/P CMOS-CCD 1H Delay Line for PAL Description The CXL5505M/P CXL5505M/P are CMOS-CCD delay line ICs that provide 1H delay time for PAL signals including the external low-pass filter. CXL5505M CXL5505M 14 pin , 5-staircase wave is fed. 150mV 350mV 500mV 150mV 1H 64us Input waveform (5) The internal clock , 150mV 1H 64us Input waveform Clock fsc (4.433619MHz) sine wave 0.3 to 1.0Vp-p (0.5Vp-p typ. , Delay time 190ns LPF 5V 2200 Transistor used NPN: 2SC2785 2SC2785 2200 2200 (ex. ... | Original |
9 pages, |
CXL5505P CXL5505M clamp meter circuit diagram 4 npn transistor ic 14pin 2SC403 2SC2785 2SA1175 CXL5505M/P CXL5505M/P abstract |
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| Abstract: CXL5506M/P CXL5506M/P CMOS-CCD 1H Delay Line for PAL Description The CXL5506M/P CXL5506M/P are CMOS-CCD delay line ICs that provide 1H delay time for PAL signals including the external low-pass filter. CXL5506M CXL5506M 8 pin , 500mV 150mV 1H 64us Input waveform (5) The internal clock component to the output signal , meter, in BPF 100kHz to 5MHz, Sub Carrier Trap mode. 175mV 325mV 150mV 1H 64us Input , 330k 1000p 1k 470 27p Delay time 190ns LPF 5V 2200 Transistor used NPN ... | Original |
9 pages, |
CXL5506P CXL5506M 2SC2785 2SA1175 CXL5506M/P CXL5506M/P abstract |
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| Abstract: CXL5506M/P CXL5506M/P CMOS-CCD 1H Delay Line for PAL For the availability of this product, please contact the sales office. Description The CXL5506M/P CXL5506M/P are CMOS-CCD delay line ICs that provide 1H delay time , 5-staircase wave is fed. 150mV 350mV 500mV 150mV 1H 64us Input waveform (5) The internal clock , 150mV 1H 64us Input waveform Clock 4fsc (17.734475MHz) sine wave 0.3 to 1.0Vp-p (0.5Vp-p , (Inverted signal) 3 6 10 560k 1u 330k 1000p 1k 470 27p Delay time 190ns ... | Original |
9 pages, |
CXL5506P CXL5506M 2SC2785 2SA1175 CXL5506M/P CXL5506M/P abstract |
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| Abstract: CXL5505M/P CXL5505M/P CMOS-CCD 1H Delay Line for PAL For the availability of this product, please contact the sales office. Description The CXL5505M/P CXL5505M/P are CMOS-CCD delay line ICs that provide 1H delay time , 1H 64us Input waveform (5) The internal clock component to the output signal during no-signal , BPF 100kHz to 5MHz, Sub Carrier Trap mode. 175mV 325mV 150mV 1H 64us Input waveform , 2 1u 4 11 5 10 1k 470 7 8 27p Delay time 190ns LPF 5V ... | Original |
9 pages, |
CXL5505P CXL5505M 4 npn transistor ic 14pin 2SC403 2SC2785 2SA1175 CXL5505M/P CXL5505M/P abstract |
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| Abstract: approximate delay between power sequencing events. Given the wide range in power supply startups (hundreds of , , ispPAC-POWR1208, and ispPAC-POWR1208P1) can be as much as 50% at lower delay settings. For the second-generation Power Manager devices, the worst-case inaccuracy is 12.5% at lower delay settings. Unless otherwise , , 256 or 512. The output clock period from the prescaler determines unit delay of all timers on-chip. , 32us ÷ 16 64us ÷ 32 128us ÷ 64 256us ÷ 128 512us ÷ 256 1024us ÷ 512 ... | Original |
8 pages, |
timer circuits POWR604 AN6076 on delay timer circuit diagram delay timer circuit diagram -POWR604 AN6076 abstract |
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| Abstract: CXL5514M/P CXL5514M/P CMOS-CCD 1H Delay Line for PAL Description The CXL5514M/P CXL5514M/P are CMOS-CCD delay line ICs designed for processing video signals. This ICs provide a 1H delay time for PAL signals including the external lowpass filter. Features · Single 5V power supply · Low power consumption · Built-in , wave is fed. 150mV 350mV 500mV 150mV 1H 64us 5. Leakage of internal clock components and , 150mV 1H 64us CLOCK fSC (4.433619MHz) Sine wave 400mVp-p (Typ.) 4 5 50% white ... | Original |
9 pages, |
CXL5514P CXL5514M 2SC403 2SA403 4.433619MHZ CXL5514M/P CXL5514M/P abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| Integrated baseband delay line (64 us) Sync processor which generates the horizontal and vertical drive demodulator without extra reference circuit Switchable group delay correction circuit which can be used to compensate the group delay pre-correction of the B/G TV standard in multistandard TV receivers Several (I with CVBS output and Y/C input Integrated chrominance trap circuit Integrated luminance delay line with adjustable delay time Integrated chrominance band-pass filter with switchable centre frequency www.datasheetarchive.com/files/philips/pip/tda9321h_2.html |
Philips | 23/04/2003 | 5.25 Kb | HTML | tda9321h_2.html |
| baseband delay line (64 us) Sync processor which generates the horizontal and vertical drive pulses ) circuit AM demodulator without extra reference circuit Switchable group delay correction circuit which can be used to compensate the group delay pre-correction of the B/G TV standard in circuit Integrated luminance delay line with adjustable delay time Integrated chrominance band helper signals for PALplus and EDTV-2 Internal baseband delay line Two linear RGB inputs with www.datasheetarchive.com/files/philips/pip/tda9321h_2-v1.html |
Philips | 15/06/2005 | 7.79 Kb | HTML | tda9321h_2-v1.html |
| is generic ( GBL_TM_DELAY : time := 2 ns; - Global timing delay DIV clk = '1' THEN q_p(i) www.datasheetarchive.com/download/23037380-996044ZC/xapp759.zip (timer_srl.vhd) |
Xilinx | 26/04/2004 | 2752.08 Kb | ZIP | xapp759.zip |
| SN75LBC088 SN75LBC088 SN75LBC088 SN75LBC088 AUI CONCENTRATOR SLLS150A SLLS150A SLLS150A SLLS150A - DECEMBER 1992 - REVISED MAY 1993 Copyright © 1993, Texas Instruments Incorporated features Meets or Exceeds the Standards Set by ISO 8802.3:1990 and ANSI/IEEE 802.3-1990 Receiver Squelch Circuit Integrity Improved With Noise Filter Differential (Twisted-Pair) I/O Driver and Receiver 84-Pin, Plastic Leaded Chip Carrier (PLCC) Package Control Logic Function for Local and Global Modes Low Port-to-Port Data Propagation Delay Drives www.datasheetarchive.com/files/texas-instruments/data/html/slls150a.htm |
Texas Instruments | 31/05/1997 | 9.17 Kb | HTM | slls150a.htm |
| Delay Drives Twisted-Pair Transmission Lines Up to 50 Meters Collision Detection for Multiple www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/datasht/slls150a.htm |
Texas Instruments | 01/06/1998 | 12.99 Kb | HTM | slls150a.htm |
| :f= 31.3khz -> T= 32us ] DC.B %00000000 ;value is 0 for "7" [clock:f= 15.6khz -> T= 64us .B 1 ;off_time of the clock PWM in current mode .present_ki DS.B 1 ;delay coefficient RUNNING .mmcomp DS.B 1 ;mem of the real delay .mmzreg DS.B 1 ;mem of the zero crossing event www.datasheetarchive.com/download/23106712-844026ZC/an1083.zip (CST_CC.ASM) |
STMicroelectronics | 19/12/2000 | 26.58 Kb | ZIP | an1083.zip |
| :f= 31.3khz -> T= 32us ] DC.B %00000000 ;value is 0 for "7" [clock:f= 15.6khz -> T= 64us .B 1 ;off_time of the clock PWM in current mode .present_ki DS.B 1 ;delay coefficient RUNNING .mmcomp DS.B 1 ;mem of the real delay .mmzreg DS.B 1 ;mem of the zero crossing event www.datasheetarchive.com/download/90015441-845096ZC/an1083.zip (CST_CC.ASM) |
STMicroelectronics | 25/05/2000 | 26.58 Kb | ZIP | an1083.zip |
| Active Bus 64us 64us 128us 128us AN1731 AN1731 AN1731 AN1731 6 MOTOROLA Application Note VPW J1850 J1850 J1850 J1850 receive pin polarity bit (RXPOL) in the BDLC analog and roundtrip delay register (BARD). That way the , Continued SYM. RETURN � NOT USED WAKE DID THE CRC ERROR DELAY FOR AN EOF TIME PERIOD RETURN CLEAR THE 4X * * * BDLC Register Equates * bard equ $3b ;BDLC analog and roundtrip delay bcr1 ; inverted polarity, 16 us delay mov #$c0,bcr2 ;Remain in loopback modes, set NBFS if using www.datasheetarchive.com/download/98588234-314023ZC/an1731sw.zip (AN1731.pdf) |
KyteLabs | 11/06/2002 | 173.75 Kb | ZIP | an1731sw.zip |
| 111 & Disabled 8 s 16 s 32 s 64 s 128 s 256 s 512 s Disabled 64 us 128 us 256 us 1 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 & 64 us 43221100 CAS# Pulse Width For Bank 0 RAS# to CAS# Delay Timing For Bank 0 RAS# Precharge Timing For Bank Pulse Width 3 Cycle RAS# To CAS# Delay 4 Cycle RESERVED RAS# To CAS# Delay 2 Cycle RAS# To CAS# Delay 3 Cycle RAS# Precharge Time 4 Cycle RESERVED RAS# Precharge Time 2 Cycle RAS# Precharge Time 3 www.datasheetarchive.com/download/49127042-847939ZC/gr-v1.zip (STPC_REG.DAT) |
STMicroelectronics | 16/12/1998 | 632.06 Kb | ZIP | gr-v1.zip |
| delay timing for banks 0 01 reserved 10 RAS# to CAS# delay 2 cycle 11 RAS# to CAS# delay 3 cycle 00 RAS# to CAS# delay 4 cycle Bit 1-0 bk0casnc: CAS pulse width for banks 0 01 CAS# low Bit 3-2 bk1rcdnc: These bits control the RAS to CAS delay timing. 01 reserved 10 RAS# to CAS# delay 2 cycle 11 RAS# to CAS# delay 3 cycle 00 RAS# to CAS# delay 4 cycle Bit 1 Bit 3-2 bk2rcdnc: These bits control the RAS to CAS delay timing. 01 reserved www.datasheetarchive.com/download/49127042-847939ZC/gr-v1.zip (REG.TXT) |
STMicroelectronics | 16/12/1998 | 632.06 Kb | ZIP | gr-v1.zip |