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ddr2 Datasheet

Part Manufacturer Description PDF Type
DDR2-400 Infineon Technologies Memory DRAM Modules Original
DDR2-533 Infineon Technologies Memory DRAM Modules Original
DDR2CTWB-M2-U Lattice Semiconductor Software, Programmers, Development Systems, IP CORE DDR2 SDRAM XO2 Original
DDR2CTWB-M2-UT Lattice Semiconductor Software, Programmers, Development Systems, IP CORE DDR2 SDRAM XO2 Original
DDR2-P-E3-U6 Lattice Semiconductor Software, Programmers, Development Systems, IP CORE DDR2 SDRAM CTLR ECP3 Original
DDR2-P-E3-UT6 Lattice Semiconductor Software, Programmers, Development Systems, SITE LICENSE DDR2 SDRAM ECP3 Original
DDR2-P-P2-U6 Lattice Semiconductor Software, Programmers, Development Systems, IP CORE DDR2 SDRAM CTLR ECP2 Original
DDR2-P-P2-UT6 Lattice Semiconductor Software, Programmers, Development Systems, SITE LICENSE DDR2 SDRAM ECP2 Original
DDR2-P-PM-U6 Lattice Semiconductor Software, Programmers, Development Systems, IP CORE DDR2 SDRAM CTLR ECP2M Original
DDR2-P-PM-UT6 Lattice Semiconductor Software, Programmers, Development Systems, SITE LICENSE DDR2 SDRAM ECP2M Original
DDR2-P-SC-U6 Lattice Semiconductor Software, Programmers, Development Systems, IP CORE DDR2 SDRAM CTLR SC/SCM Original
DDR2-P-X2-U6 Lattice Semiconductor Software, Programmers, Development Systems, IP CORE DDR2 SDRAM CTLR XP2 Original

ddr2

Catalog Datasheet MFG & Type PDF Document Tags

controller for sdram

Abstract: DDR2 SDRAM ECC PLB Double Data Rate (DDR2) Synchronous DRAM (SDRAM) Controller (v1.01a) 0 DS326 March 22 , Local Bus DDR2 SDRAM (PLB DDR2 SDRAM) controller connects to the PLB and provides the control interface for DDR2 SDRAMs. It is assumed that the reader is familiar with DDR2 SDRAMs and the IBM PowerPC , plb_ddr2 Resources Used The Xilinx PLB DDR2 SDRAM controller is a soft IP core designed for Xilinx , auto-refresh cycles Supports 32-bit and 64-bit of DDR2 SDRAM devices Provides big-endian connections to
Xilinx
Original
controller for sdram DDR2 SDRAM ECC ddr2 datasheet vhdl sdram CLK180 XC2VP20 JESD79-2A DS458

DDR2800D

Abstract: IS46DR16320B , DDR2-533C, DDR2-667D, DDR2-800E DDR2-400B, DDR2-533C DDR2-533C DDR2-533C, DDR2-667D, DDR2-800E, DDR2-800D DDR2-533C, DDR2-667D DDR2-533C, DDR2-667D, DDR2-800E, DDR2-800D DDR2-667D, DDR2-800E, DDR2-800D, DDR2-1066F DDR2-667D DDR2-667D, DDR2-800E, DDR2-800D Pkg. BGA(126) BGA(126) BGA(126) BGA(84) BGA(84) BGA(60) BGA , = 5) tCK (CL = 6) tCK (CL = 7) Frequency (max) -3D DDR2-667D 5-5-5 5 3.75 3 3 3 333 -25E -25D DDR2-800E DDR2-800D 6-6-6 5-5-5 5 5 3.75 3.75 3 2.5 2.5 2.5 2.5 2.5 400 400 -19F DDR2-1066F 7-7-7 5 3.75 3 2.5
Integrated Silicon Solution
Original
IS43DR16320B IS46DR16320B DDR2800D BGA84 BGA-84 IS43DR16320 533MH IS43DR32800A IS43DR32801A IS46DR32801A IS43DR16160A IS46DR16160A

HYMP512S64CP8-Y5

Abstract: HYMP564S64CP6-Y5 DDR400 (Planar) DDR333 256Mx4 DDR266A (Stack) DDR266B DDR200 1GB 128MX72 128MX4 DDR400 DDR333 64Mx4 DDR400 (Planar) DDR333 128Mx4 DDR266A (Stack) DDR266B DDR200 512MB 64Mx72 , DDR266A 512MB 64MX72 (ECC) 64MX64 32Mx8 DDR266B 64MX8 DDR400 DDR333 DDR266B 32Mx8 DDR500 DDR400 DDR333 DDR266A DDR266B PART NUMBER HYMD512726A8J-D43 HYMD512726B(P)8J , ECC DDR333 DDR266A DDR266B 32Mx64 32Mx8 DDR333 DDR266A DDR266B 16Mx16
Hynix Semiconductor
Original
H5TQ1G43BFR-H9C H5TQ1G83BFR-H9C H5TQ1G63BFR-H9C HYMP512S64CP8-Y5 HYMP564S64CP6-Y5 h5ps2g83afr-s6c H5PS1G63EFR-Y5C H5TQ1G43AFP-H9C H5TQ1G43TFR-H9C H5TQ1G43AFP-G7C H5TQ1G43BFR-G7C H5TQ1G43TFR-G7C

DDR2 pcb layout

Abstract: DDR2 layout guidelines interface is compatible with x16 DDR2-533 speed grade DDR2 devices. Table 1. Compatible JEDEC DDR2 Devices , (3) DDR2-533 92 x16 x16 Bits Higher DDR2 speed grades are supported due to inherent , Application Report SPRAB03A ­ October 2008 Implementing DDR2 PCB Layout on the TMS320DM357 , instructions for the DDR2 interface contained on the TMS320DM357 digital media system-on-chip (DMSoC) devices. The approach that was taken to specify interface timing for the DDR2 interface is quite different
Texas Instruments
Original
DDR2 pcb layout DDR2 layout guidelines SPRU811 DDR2 pcb design DDR2 schematic DM357

TN-47-16

Abstract: DDR2 tFAW (x16) DDR2-400 DDR2-533 DDR2-667 DDR2-800 256M (1KB ) 512M (2KB , tFAW tFAW 3 3 tFAW t FAW (x4 x8) DDR2-400 DDR2-533 DDR2-667 DDR2-800 256M (1KB ) 512M (1KB ) 1G (1KB ) 2G (1KB ) 37.5 37.5 37.5 , /ddr2sdram/technote.html TN-47-08 DDR2 Package Sizes and Layout Requirements DDR2 , http:/ /www.micron.com/products/modules/ddr2sdram/technote.html TN-47-08 DDR2 Package Sizes and
Micron Technology
Original
TN-47-16 DDR2 DDR2 DIMM JEDEC 256MX16 DDR2 layout so-dimm 47-16 l7 TN-47-1

MT47H16M16FG

Abstract: XAPP768 ) ddr2_clk* Output Memory differential clock signals ddr_odt[4:0] Initializing DDR2 SDRAM , figure are sub-blocks of the ddr2_top module. The function of each block is explained in the following sections. user_clk Infrastructure DDR2_IF user_data Data Path Command & Address IOBS , Application Note: Spartan-3 FPGAs R XAPP454 (v1.1.1) June 11, 2007 DDR2 SDRAM Memory , a DDR2 SDRAM memory interface implementation in a SpartanTM-3 device, interfacing with a Micron
Xilinx
Original
XAPP768 MT47H16M16FG-37E MT47H16M16FG XAPP768c interface ddr2 sdram with spartan3 MT47H16M16FG-37E IT

MT47H128M16HG-37E

Abstract: MT47H64M16BT-37E with this interface. Generally, the DDR2 interface is compatible with all x16 DDR2-533 speed grade DDR2 devices and most x8 DDR2-533 speed grade DDR2 devices. When implementing four x8 devices to achieve a 32-bit memory solution, the maximum clock frequency is reduced to 250 MHz for DDR2-500 , See Note 1 DDR2-533 JEDEC DDR2 Device Size 256M Higher DDR2 speed grades are supported , JEDEC DDR2 compatible devices are recommended: · MT47H128M16HG-37E - Micron 2Gb DDR2-533 84 ball
Texas Instruments
Original
MT47H64M16BT-37E DDR2 layout MT47H128M16HG micron DDR2 pcb layout mt47h128m16 MT47H128M16HG-3 TMS320C6472/TMS320TCI6486 C6472/TCI6486

ddr2 ram

Abstract: DDR2 chip DDR2_DQS (C_DDR_DQS_WIDTH ­ 1:0) DDR2 I/O DDR2 data strobe DDR2_DQS_N (C_DDR_DQS_WIDTH ­ 1:0 , DDR2_BA (C_DDR_BAWIDTH ­ 1:0) DDR2 O DDR2 bank address DDR2_RAS_N DDR2 O DDR2 row address strobe DDR2_CAS_N DDR2 O DDR2 column address strobe DDR2_WE_N DDR2 O DDR2 write enable DDR2_CS_N (C_NUM_RANKS_MEM ­ 1 down to 0) DDR2 O DDR2 chip selects DDR2_ODT , DDR2_CK (C_NUM_CLK_PAIRS ­ 1:0) DDR2 O DDR2 clock DDR2_CK_N (C_NUM_CLK_PAIRS ­ 1:0) DDR2
Xilinx
Original
DS567 PPC440MC ddr2 ram DDR2 chip FIFO36 verilog code hamming AR29-3 APU FCM

C6424

Abstract: DDR2 layout guidelines . Generally, the DDR2 interface is compatible with x16 DDR2-533 speed grade DDR2 devices. Table 1. Compatible , See Note (3) DDR2-400 92 x16 x16 Bits Higher DDR2 speed grades are supported due , Application Report SPRAB08 ­ October 2008 Implementing DDR2 PCB Layout on the TMS320C6424 DSP , DDR2 interface contained on the TMS320C6424 digital signal processor (DSP) device. The approach to specifying interface timing for the DDR2 interface is quite different than on previous devices. The
Texas Instruments
Original
C6424 DDR2 x32

Msi 533 Motherboard

Abstract: Msi 533 845gv Motherboard Motherboard Compatibility List AET560UD00-370 256 MByte DDR2-533 CL4 240-Pin DIMM Description , DDR2-533 CL4 D915GEV Pentium 4 Intel 915G DDR2-533 CL4 Gigabyte Motherboard Processor Chipset Max. Speed 8ANXP-D Pentium 4 Intel 925X + ICH6R DDR2-533 CL4 8ANXP-D (Rev 2.0) Pentium 4 Intel 925X + ICH6R DDR2-533 CL4 8AENXP-D Pentium 4 Intel 925XE + ICH6R DDR2-533 CL4 8AENXP-DW Pentium 4 Intel 925XE + ICH6R DDR2-533 CL4 8AENXP Dual
AENEON
Original
D925XCV 8I915P 8IPE775 865GV MCP04 Msi 533 Motherboard Msi 533 845gv Motherboard Msi 533 845gv ich4 Motherboard gigabyte motherboard intel motherboard intel d915gev motherboard 240-P 8I925X-G 8I925XE 8I915G-D

DDR2 pcb layout

Abstract: TMS320C6452 evm interface is compatible with x16 DDR2-533 speed grade DDR2 devices. Table 1. Compatible JEDEC DDR2 Devices , (3) DDR2-533 92 x16 x16 Bits Higher DDR2 speed grades are supported due to inherent , Application Report SPRAAL0A ­ March 2008 Implementing DDR2 PCB Layout on the TMS320C6452 DSP , for the DDR2 interface contained on the TMS320C6452 digital signal processor (DSP) device. The approach to specifying interface timing for the DDR2 interface is quite different than on previous
Texas Instruments
Original
TMS320C6452 evm ddr2 controller CACLM-50 C6452

tms320tci6488 evm

Abstract: TMS320TCI6488 5.3 Effect of DDR2 Bank and Row Switch on Multiple Masters Sharing DDR2. . . . . . . . 23 5.4 Effect , to DDR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Effect of BPRIO on Multiple EDMA TCs Access to DDR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 , slightly for the DDR2->DDR2 case. If the source and destination are in the same bank, the DDR2 row switch , . Figure 3 shows data collected from 1GHz TCI6488 EVM with 32-bit 667MHz DDR2. The time required for 1024
Texas Instruments
Original
TMS320TCI6488 tms320tci6488 evm SPRAB57--J 667MH 16GB/ 333GB/

vhdl code for ddr2

Abstract: vhdl sdram DDR & DDR2 SDRAM Controller Compiler Errata Sheet June 2006, Compiler Version 3.4.0 This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version 3.4.0. Errata are functional defects or errors, which may cause the DDR and DDR2 SDRAM , issues that affect the DDR and DDR2 SDRAM Controller Compiler v3.4.0. Table 1. DDR and DDR2 SDRAM , for this release, refer to the errata sheet on the Altera® website: 1 DDR & DDR2 SDRAM
Altera
Original
vhdl code for ddr2 vhdl code for sdram controller sdram controller sdram verilog Verilog DDR memory model DDR2 SDRAM component data sheet 800-EPLD

JESD79D-2A

Abstract: JESDEC79-2A TMS320DM647/DM648 DSP DDR2 Memory Controller User's Guide Literature Number: SPRUEK5A , . 2.7 DDR2 Memory Controller Interface , . 2.11 DDR2 SDRAM Memory Initialization , . 3 Using the DDR2 Memory Controller . 3.1 Connecting the DDR2 Memory Controller to DDR2 SDRAM
Texas Instruments
Original
JESD79D-2A JESDEC79-2A DM648 DM648 layout C6000 TMS320C6000

JESD79-2c

Abstract: P6860 ColdFire Implementation of DDR2. . . . . . . . . . . . . . . . . . 3 3.1 ColdFire Internal Architecture , reviews how the MCF5445x implements support for DDR2. 3.1 ColdFire Internal Architecture and DDR2 , information. The SDRAM control register (SDCR) contains a DDR2_MODE bit, which must be set to enable the LMR , Freescale Semiconductor Application Note AN3522 Rev. 0, 09/2007 DDR2 SDRAM on the ColdFire MCF5445x Microprocessor Designing for power and performance with DDR2 on ColdFire by: John Weil
Freescale Semiconductor
Original
JESD79-2c P6860 DDR2 Considerations for Designing SODIMM ddr2 P6880 MCF54455 MCF5445
Abstract: -pin DIMM (Halogen-free) â'¢ Frequency/CAS latency â'" 2.5ns @ CL = 5 (DDR2-800) â'" 3.0ns @ CL = 5 (DDR2-667 , test conditions. Table 10: IDD Specifications â'" 1GB DDR2-667 (Die revision H) IDD_IDLE , (x72, SR) 240-Pin DDR2 SDRAM FBDIMM Serial Presence-Detect Table 11: IDD Specifications â'" 1GB DDR2-667 , 8.8 4.5 W Table 12: IDD Specifications â'" 1GB DDR2-800 (All die revisions) Symbol , 1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM Features DDR2 SDRAM FBDIMM MT9HTF12872FZ â'" 1GB Micron Technology
Original
PC2-5300 PC2-6400 MO-256

TMS320DM643x

Abstract: DDR2 pin out . Generally, the DDR2 interface is compatible with x16 DDR2-533 speed grade DDR2 devices. Table 1. Compatible , See Note (3) DDR2-400 92 x16 x16 Bits Higher DDR2 speed grades are supported due , Application Report SPRAAL6A ­ June 2008 Implementing DDR2 PCB Layout on the TMS320DM643x DSP , DDR2 interface contained on the TMS320DM643x digital signal processor (DSP) device. The approach to specifying interface timing for the DDR2 interface is quite different than on previous devices. The
Texas Instruments
Original
TMS320DM643x DDR2 pin out TMS320DM6435 TMS320DM6437 TMS320DM643 DM643

DDR2 pcb layout

Abstract: DDR2 layout guidelines Application Report SPRAAL2D ­ November 2009 Implementing DDR2/mDDR PCB Layout on the , . ABSTRACT This application report contains implementation instructions for the DDR2/mDDR , specifying interface timing for the DDR2/mDDR interface is quite different than on previous devices. The , (PCB) using high-speed simulation to close system timing. For the DM335 DDR2/mDDR interface, the approach is to specify compatible DDR2/mDDR devices and provide the PCB routing rule solution directly. TI
Texas Instruments
Original
TMS320DM335 40X20

ddr2

Abstract: DDR2-800E IS43DR16320C IS43DR86400C IS43DR16640B 1G IS43DR81280B IS43DR16128 2G 128Mx8 DDR2-667D, DDR2-800E, DDR2-800D 128Mx16 DDR2-667D 512M Den. 256M Org. 8Mx32 16Mx16 32Mx8 16Mx32 32Mx16 64Mx8 64Mx16 Speeds DDR2-400B, DDR2-533C DDR2-400B, DDR2-533C, DDR2-667D, DDR2-800E DDR2-533C DDR2-400B, DDR2-533C, DDR2-667D DDR2-533C, DDR2-667D, DDR2-800E, DDR2-800D DDR2-533C, DDR2-667D, DDR2-800E, DDR2-800D DDR2-667D, DDR2-800E, DDR2-800D Pkg , DDR2-533C 4-4-4 5 3.75 3.75 3.75 266 -3D DDR2-667D 5-5-5 5 3.75 3 3 333 -25E DDR2-800E 6-6-6 5 3.75 3
Integrated Silicon Solution
Original
IS46DR 5bbl 126-ball 800E BGA60 IS43DR83200A IS43DR32160C

MT47H64M16BT-37E

Abstract: DDR2 pcb layout x16 device width. Any JEDEC DDR2-533 speed grade device at these densities in the x16 width will work , 1Gb DDR2-533 92 ball package MT47H32M16BT-37E - Micron 512Mb DDR2-533 92 ball package MT47H32M16CC-37E - Micron 512Mb DDR2-533 84 ball package MT47H16M16BG-37E - Micron 256Mb DDR2-533 84 ball package EDE5116ABSE-5C-E - Elpida 512Mb DDR2-533 84 ball package EDE5116AFSE-5C-E - Elpida 512Mb DDR2-533 84 ball package EDE2516ABSE-5C-E - Elpida 256Mb DDR2-533 84 ball package Note that the 84 and 92 ball DDR2 BGA
Texas Instruments
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DDR2 routing JESD-79A MT47H64M16* pcb elpida DDR2 routing MT47H32M16 Resistor Packs TMS320TCI6482 TCI6482

MT36HTF51272FZ

Abstract: 4GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Features DDR2 SDRAM FBDIMM MT36HTF51272FZ ­ 4GB For , precise control and repeatable memory behavior · Automatic DDR2 SDRAM bus and channel calibration · , ) Options · Package ­ 240-pin DIMM (halogen-free) · Frequency/CAS latency (CL) ­ 2.5ns @ CL = 5 (DDR2-800) ­ 3ns @ CL = 5 (DDR2-667) Marking Z -80E -667 Key Timing Parameters Industry Nomenclature , notice. 4GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Features Table 2: Parameter Refresh count Device
Micron Technology
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PC2-4200
Abstract: 512MB, 1GB, 2GB Unbuffered DIMMs DDR2 SDRAM DDR2 Unbuffered SDRAM MODULE 240pin Unbuffered , Revised IDD Current Values History DDR2 SDRAM Rev. 1.1 Aug. 2005 512MB, 1GB, 2GB Unbuffered DIMMs DDR2 Unbuffered DIMM Ordering Information Part Number M378T6464AZ3-CE6/D5/CC M378T2863AZ3-CE6/D5 , Component Composition 64Mx16(K4T1G164QA)*4 128Mx8(K4T1G084QA)*8 128Mx8(K4T1G084QA)*16 DDR2 SDRAM Number , products. Features · Performance range E6(DDR2-667) Speed@CL3 Speed@CL4 Speed@CL5 CL-tRCD-tRP 400 533 Samsung Electronics
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M378T2863AZ3-CE6/D5/CC M378T5663AZ3-CE6/D5/CC M391T2863AZ3-CE6/D5/CC M391T5663AZ3- 2863AZ3/M391T2863AZ3 M378T5663AZ3/M391T5663AZ3
Abstract: 8GB (x72, QR) 240-Pin DDR2 SDRAM FBDIMM Features DDR2 SDRAM FBDIMM MT72HTS1G72FZ â'" 8GB Features Figure 1: 240-Pin FBDIMM (MO-256) â'¢ 240-pin, DDR2 fully buffered DIMM (FBDIMM) â'¢ Fast , '" Delivers precise control and repeatable memory behavior â'¢ Automatic DDR2 SDRAM bus and channel , '" 240-pin DIMM (halogen-free) â'¢ Frequency/CAS latency â'" 2.5ns @ CL = 5 (DDR2-800) â'" 3.0ns @ CL = 5 (DDR2-667) Z -80E -667 Features (Continued) â'¢ VDD = V DDQ = 1.8V for DRAM â'¢ VREF = Micron Technology
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TN47-19

Abstract: 92-Ball TN-47-19: DDR2 (Point-to-Point) Features and Functionality Introduction Technical Note DDR2 , needed. However, DDR2 SDRAM memory has changed this legendary tradition. Unlike previous DRAM, DDR2 , . DDR2 SDRAM offers several options: · Maximum bandwidth up to 800 MT/s (mega transfers per second) · , · Signal reflections controlled through selectable output drive levels. Unlike on DDR, DDR2 , high-density devices in extremely compact footprints A side-by-side comparison of DDR2 with SDR and DDR
Micron Technology
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TN47-19 92-Ball EMR01 DDR2 SDRAM with SSTL_18 interface DDR2 2gb x16 industrial DDR2800 3815/S TN4719
Abstract: 256MB,512MB Unbuffered DIMMs DDR2 SDRAM DDR2 Unbuffered SDRAM MODULE 240pin Unbuffered , 256MB,512MB Unbuffered DIMMs DDR2 Unbuffered DIMM Ordering Information Part Number Density Organization Component Composition Number of Rank 1 2 1 2 DDR2 SDRAM Height x64 Non ECC M378T3253FG(Z)0 , . Features · Performance range E6(DDR2-667) Speed@CL3 Speed@CL4 Speed@CL5 CL-tRCD-tRP 400 533 667 5-5-5 D5(DDR2-533) 400 533 4-4-4 CC(DDR2-400) 400 400 3-3-3 Unit Mbps Mbps Mbps CK · JEDEC standard 1.8V ± Samsung Electronics
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M378T6453FG M391T3253FG M391T6453FG K4T56083QF 267MH 333MH
Abstract: 8GB (x72, ECC, QR) 240-Pin DDR2 SDRAM FBDIMM Features DDR2 SDRAM FBDIMM MT72HTS1G72F ­ 8GB Features · · · · · · · · · · · 240-pin, DDR2 fully buffered DIMM (FBDIMM) Fast data transfer rates: PC2 , Automatic DDR2 SDRAM bus and channel calibration Transmitter de-emphasis to reduce ISI MBIST and IBIST test , (Pb-free) · Frequency/CAS latency ­ 2.5ns @ CL = 5 (DDR2-800) ­ 3.0ns @ CL = 5 (DDR2-667) Marking Y , Technology, Inc. All rights reserved. 8GB (x72, ECC, QR) 240-Pin DDR2 SDRAM FBDIMM Features Table 1: Key Micron Technology
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Implementation of DDR2 on AT91SAM9G45 Devices

Abstract: MT47H64M8CF-3 Implementation of DDR2 on AT91SAM9G45 Devices 1. Scope The AT91SAM9G45 microprocessor features: · One multi-port DDR2 controller that supports 16-bit DDR2 or 16-bit LP-DDR memories only · One single-port DDR2 controller that supports 16-bit DDR2, 16-bit LP-DDR, 16- or 32-bit SDR or LP-SDR memories , DDR2. Each DDR2 controller is described separately. AT91 ARM Thumb-based Microcontrollers Application Note 6492A­ATARM­22-Sep-09 2. Multi-Port DDR2 Controller Overview The DDR2 controller
Atmel
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Implementation of DDR2 on AT91SAM9G45 Devices MT47H64M8CF-3 MT47H64M8CF AT91SAM9 DDR2 AT91SAM9g45-EKes ddram

M393T5750EZA-CE

Abstract: Preliminary RDIMM DDR2 SDRAM DDR2 Registered SDRAM MODULE 240pin Registered Module based , Release History DDR2 SDRAM 2 of 23 Rev. 0.1 April 2006 Preliminary RDIMM DDR2 Registered , )*36EA Number of Rank 1 1 1 2 2 2 1 1 1 2 2 DDR2 SDRAM Parity Register X O O X O O X O O X O Height , Performance range E7(DDR2-800) Speed@CL3 Speed@CL4 Speed@CL5 CL-tRCD-tRP 400 533 800 5-5-5 E6(DDR2-667) 400 533 667 5-5-5 D5(DDR2-533) 400 533 4-4-4 CC(DDR2-400) 400 400 3-3-3 Unit Mbps Mbps Mbps CK · JEDEC
Samsung Electronics
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M393T5750EZA-CE 60FBGA M393T6553EZ3-CD5/CC M393T6553EZA-CE7/E6/D5/CC M392T6553EZA-CE7/E6/D5/CC M393T2953EZ3-CD5/CC M393T2953EZA-CE7/E6/D5/CC

PC2-5300F-555-10-B

Abstract: Preliminary 240-Pin 512MB, 1GB, 2GB DDR2 SDRAM FBDIMM (DR, FB, x72) Features DDR2 SDRAM , the Micron Web site: www.micron.com Features · 240-pin DDR2 fully buffered, dual in-line memory , transfer rates: PC2-4200 and PC2-5300, using 533 MT/s and 667 MT/s DDR2 SDRAM components · 3.2 Gb/s and 4.0 , density scaling with up to 8 dual-rank modules (288 DDR2 SDRAM devices) per channel · SMBus interface to , control and repeatable memory behavior · Automatic DDR2 SDRAM bus and channel calibration · Transmitter
Micron Technology
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PC2-5300F-555-10-B MT18HTF6472FD MT18HTF12872FD MT18HTF25672FD HTF18C64

MT36HTS1G72FY667A1D4

Abstract: RE87 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Features DDR2 SDRAM FBDIMM MT36HTS1G72F ­ 8GB For the latest data sheet, refer to Micron's Web site: www.micron.com Features · 240-pin DDR2 fully buffered , behavior · Automatic DDR2 SDRAM bus and channel calibration · Transmitter de-emphasis to reduce ISI · MBIST and IBIST test functions · Transparent mode for DDR2 SDRAM test support · VDD = VDDQ = +1.8V for DDR2 , (DDR2-667) ­ 3.75ns @ CL = 4 (DDR2-533) Marking Y -667 -53E Table 1: Speed Grade -667 -53E
Micron Technology
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MT36HTS1G72FY667A1D4 RE87 E40002 HTS36C1G
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