NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: ) DCT Low gate count Single clock cycle per sample 2-D Forward Discrete Cosine Transform Core operation Low latency (87 cycles) Design Quality The DCT core implements the 2D Forward Cosine , the Discrete Cosine Transform (DCT). The DCT core, able to operate over 8x8 and 16x16 blocks of , Finally the 2-4-8 DCT transform, as this is specified in the DVC (or DV) standard, can be optionally supported by the DCT core. Comprehensive documentation and a complete verification environment - including ... | Original |
2 pages, |
dct verilog code datasheet abstract |
|
|||
| Abstract: ) DCT Low gate count 2-D Forward Discrete Cosine Transform Megafunction Low latency (87 , standard The DCT megafunction implements the 2D Forward Cosine Transform. Most of the image/video compression standards (JPEG, MPEGx, H.261, H.263, DV etc) are based on the Discrete Cosine Transform (DCT). The DCT megafunction, able to operate over 8x8 and 16x16 blocks of samples, covers the needs of , 2-4-8 DCT transform, as this is specified in the DVC (or DV) standard, can be optionally supported by ... | Original |
2 pages, |
EP20K100E-1 dct verilog code datasheet abstract |
|
|||
| Abstract: ) DCT Low gate count Single clock cycle per sample 2-D Forward Discrete Cosine Transform Core operation Low latency (87 cycles) Design Quality The DCT core implements the 2D Forward Cosine , the Discrete Cosine Transform (DCT). The DCT core, able to operate over 8x8 and 16x16 blocks of , Finally the 2-4-8 DCT transform, as this is specified in the DVC (or DV) standard, can be optionally supported by the DCT core. Comprehensive documentation and a complete verification environment - including ... | Original |
2 pages, |
dct verilog code datasheet abstract |
|
|||
| Abstract: the Discrete Cosine Transform (DCT). Able to operate over 8x8 and 16x16 blocks of samples/DCT , coefficients. Finally the 2-4-8 DCT/IDCT transform, as this is specified in the DVC (DV) standard, can as well , over 16x16 blocks of samples/DCT coefficients Down-scaling in the frequency domain by run-time , SP dout_wen dout_rdy sob eob January 2008 Functional Description The forward DCT (DCT , set of coefficients. The inverse DCT (IDCT) reconstructs the original signal from its constituent DCT ... | Original |
2 pages, |
dct verilog code datasheet abstract |
|
|||
| Abstract: signal processing algorithms and DCT/IDCT is suggested. Users should be familiar with Verilog or VHDL , · Supports Virtex, VirtexTM-E, and SpartanTM-II devices · X_DCT_IDCT supports both DCT and IDCT on an 8x8 block of samples · DCT and IDCT operations performed at one clock/ sample · DCT input , Instantiation Templates VHDL, Verilog Reference Designs and None Application Notes Additional Items None , DCT_ IDCT 1027 1027 1140 DCT only 912 912 943 Clock IOBs1 DCT_ DCT IDCT only 1 1 ... | Original |
3 pages, |
VHDL code DCT H261 X9104 dct verilog code IDCT idct vhdl code datasheet abstract |
|
|||
| Abstract: etc) are based on the Discrete Cosine Transform (DCT). Able to operate over 8x8 and 16x16 blocks of samples/DCT coefficients, the DCT-FI covers the needs of hardware image/video compression and , from the same input stream of coefficients. Finally the 2-4-8 DCT/IDCT transform, as this is specified , , scan-ready design Optional add-on Features Operation over 16x16 blocks of samples/DCT coefficients , January 2008 Functional Description The forward DCT (DCT) is a transform that converts a signal into ... | Original |
2 pages, |
FI 201 datasheet FI 201 EP20K200E-1 dct verilog code datasheet abstract |
|
|||
| Abstract: standards (JPEG, MPEGx, H.261, H.263, DV etc) are based on the Discrete Cosine Transform (DCT). Able to operate over 8x8 and 16x16 blocks of samples/DCT coefficients, the DCT-FI covers the needs of hardware , reconstruction at various resolutions from the same input stream of coefficients. Finally the 2-4-8 DCT/IDCT , 16x16 blocks of samples/DCT coefficients Down-scaling in the frequency domain by run-time , SP dout_wen dout_rdy sob eob February 2009 Functional Description The forward DCT (DCT ... | Original |
2 pages, |
dct verilog code datasheet abstract |
|
|||
| Abstract: the Discrete Cosine Transform (DCT). Able to operate over 8x8 and 16x16 blocks of samples/DCT , coefficients. Finally the 2-4-8 DCT/IDCT transform, as this is specified in the DVC (DV) standard, can as well , over 16x16 blocks of samples/DCT coefficients Down-scaling in the frequency domain by run-time , SP dout_wen dout_rdy sob eob January 2008 Functional Description The forward DCT (DCT , set of coefficients. The inverse DCT (IDCT) reconstructs the original signal from its constituent DCT ... | Original |
2 pages, |
datasheet abstract |
|
|||
| Abstract: the Discrete Cosine Transform (DCT). The IDCT, able to operate over 8x8 and 16x16 blocks of , various resolutions from the same input stream of coefficients. Finally the 2-4-8 DCT/IDCT transform, as , , scan-ready design Optional add-on Features Operation over 16x16 blocks of DCT coefficients , Implementation Results The forward DCT (DCT) is a transform that converts a signal into its constituent frequency components as represented by a set of coefficients. The inverse DCT (IDCT) reconstructs the ... | Original |
2 pages, |
datasheet abstract |
|
|||
| Abstract: compression standards (JPEG, MPEGx, H.261, H.263, DV etc) are based on the Discrete Cosine Transform (DCT). , from the same input stream of coefficients. Finally the 2-4-8 DCT/IDCT transform, as this is specified , Operation over 16x16 blocks of DCT coefficients Down-scaling in the frequency domain by run-time , sob eob January 2008 Functional Description Implementation Results The forward DCT (DCT , set of coefficients. The inverse DCT (IDCT) reconstructs the original signal from its constituent DCT ... | Original |
2 pages, |
EP20K100E-1 EP1S10-C5 dct verilog code datasheet abstract |
|
|||
| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
|||||
| XAPP610 XAPP610 XAPP610 XAPP610 Zip file contains The word document for DCT Verilog files (*.v) dct.v test_dct.v Vhdl file (*.vhd) dct.vhd The verilog synthesized using Synplicity (Synplify Pro) and placed and routed using Foundation 4.1.03i. The multiplier instantiation in the verilog files the behavioral multiplier code is used. Test_dct contains the test bench which uses the input values . Konstantinides. Dct-dct.v is the top level file that calls the lower level dct.v and idct.v files. The lower www.datasheetarchive.com/download/89363467-995997ZC/xapp610.zip (readme.txt) |
Xilinx | 07/03/2002 | 64 Kb | ZIP | xapp610.zip |
| XAPP611 XAPP611 XAPP611 XAPP611 Zip file contains The word document for DCT Verilog files (*.v) idct.v test_dct.v Vhdl file (*.vhd) idct.vhd The verilog synthesized using Synplicity (Synplify Pro) and placed and routed using Foundation 4.1.03i. The multiplier instantiation in the verilog files the behavioral multiplier code is used. Test_dct contains the test bench which uses the input values . Konstantinides. Dct-dct.v is the top level file that calls the lower level dct.v and idct.v files. The lower www.datasheetarchive.com/download/74913078-995998ZC/xapp611.zip (readme.txt) |
Xilinx | 21/03/2002 | 53.64 Kb | ZIP | xapp611.zip |
| 2 dimensional IDCT function implemented on a Xilinx FPGA. Behavioral Verilog code is provided for . The DCT code can be used to target any Xilinx device. The code can be optimized by instantiating the parametrizeability and performance guarantee. The code is fully pipelined and after the initial latency of 84 clock uncompress DCT compressed data in the decoder. DCT/IDCT are two of the most computation intensive funtions in compression. A fast and optimized DCT/IDCT implementation is therefore essential in improving the www.datasheetarchive.com/download/74913078-995998ZC/xapp611.zip (idct.doc) |
Xilinx | 21/03/2002 | 53.64 Kb | ZIP | xapp611.zip |
| XAPP610 XAPP610 XAPP610 XAPP610 Video Compression using DCT - 8x8 points. Summary: The application note describes a 2 dimensional DCT function implemented on a Xilinx FPGA. Behavioral code is provided for the implementation on files show the efficient implementation of the DCT algorithm on Xilinx chips. The DCT code can be used guarantee. The code can be further optimized by instantiating embedded adders and multipliers when targeting Virtex2 family. After an initial latency of 92 clock cycles, one DCT value is output at every clock www.datasheetarchive.com/download/89363467-995997ZC/xapp610.zip (dct.doc) |
Xilinx | 07/03/2002 | 64 Kb | ZIP | xapp610.zip |
| -/* -* - - dct give consideration to the productivity - enhancements afforded the user of this code by the INFRINGEMENT. -* Module: dct8x8 : -* A 1D-DCT is implemented on the input pixels first. The output of this -* called the intermediate value is stored in a RAM. The 2nd 1D-DCT operation -* is done on this stored value to give the final 2D-DCT ouput dct_2d. The -* inputs are 8 bits wide and the www.datasheetarchive.com/download/89363467-995997ZC/xapp610.zip (dct.vhd) |
Xilinx | 07/03/2002 | 64 Kb | ZIP | xapp610.zip |
| /* * -* * dct give consideration to the productivity * enhancements afforded the user of this code by the INFRINGEMENT. * Module: dct8x8 : * A 1D-DCT is implemented on the input pixels first. The output of this * called the intermediate value is stored in a RAM. The 2nd 1D-DCT operation * is done on this stored value to give the final 2D-DCT ouput dct_2d. The * inputs are 8 bits wide and the 2d-dct ouputs are 9 www.datasheetarchive.com/download/89363467-995997ZC/xapp610.zip (dct.v) |
Xilinx | 07/03/2002 | 64 Kb | ZIP | xapp610.zip |
| Multiplicative Complexity Implementation of the 2-D DCT using Xilinx FPGAs 300 KB Summary 11 Verilog VHDL Both Source WS 50 KB 50 KB 100 KB PC Design Guide 1.8 MB Summary 6/99 FPGA Verilog VHDL using the same technology. Minimum Multiplicative Complexity Implementation of the 2-D DCT using -performance 2-D discrete cosine transform (DCT) processor for real-time applications. The paper provides an www.datasheetarchive.com/files/xilinx/docs/rp00003/rp0031b.htm |
Xilinx | 06/03/2000 | 36.71 Kb | HTM | rp0031b.htm |
| the internal Block RAM and it writes values to the DCT core via the Local Link bus. After every 8th result can be seen in a Hyperterminal. This program is located in code/system.c. Hyperterminal _modelsim.c file (without print statements). EDK provides behavioral simulation for VHDL or Verilog designs in a www.datasheetarchive.com/download/40314210-995985ZC/xapp529_6_2.zip (readme.txt) |
Xilinx | 26/03/2004 | 189.07 Kb | ZIP | xapp529_6_2.zip |
| Efficiency For DSP Functions Improved logic synthesis results HDL Code, DSP Cores Verilog, VHDL Fast Image Processing More complex 2-dimensional algorithm 2D FIR, 2D DCT, Wavelet Larger computational mask error control - Turbo codes Software / configurable radio Multiple modulation, error correction and data Performance + Flexibility VHDL Verilog DSP Functions IRL Tools Network- Configurable Radio Reaching for the www.datasheetarchive.com/files/xilinx/docs/rp0006b/rp06b50.pps |
Xilinx | 23/02/2000 | 3735.5 Kb | PPS | rp06b50.pps |
| control - Turbo codes and MAP decoders Software / configurable radio Multiple modulation, error correction algorithm (2D FIR, 2D DCT, Wavelet) Larger computational mask Real time image processing Emerging standards , Verilog) for DSP designs. FPGAs now offer similar performance to a custom hardware solution with the parameterizable DSP cores and VHDL / Verilog design methodology is proving itself to be the ideal DSP design computationally intensive communications algorithms such as Turbo codes and MAP decoders (yields 1.5 dB better www.datasheetarchive.com/download/71018457-977823ZC/rp06f2e.ppt |
Xilinx | 23/02/2000 | 1023 Kb | PPT | rp06f2e.ppt |