MATRIX CONTROLLER DRIVER general description NJU6426 Matrix
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4-LINE WITH EXTENSION FUNCTION
MATRIX CONTROLLER DRIVER
general description
NJU6426 Matrix controller driver 8-character 24-character 4-line with icon display single coirbine with some extension driver.
contains voltage converter, bleeder resistance, oscillator, microprocessor interface circuits, instruction decoder control ler, character generator ROM/RAM, high voltage operation comnon segment drivers extension driver interface circuits.
voltage converter bleeder resistance generates about twofold voltage(lOV) bias voltage driving waveform internally from single power supply (5V). Consequently, high-contrast display performed though simple power sipply circuits.
oscillator incorporates therefore external components oscillation required.
microprocessor interface circuits which operate 2MHz, connected directly 4/8bit microprocessor.
character generator consists 9,600 bits bytes RAM.
33-common character, icon 40-segment drivers operated 13.5V, icon common driver display icon single combine with some extension driver.
features
8-character 4-1ine Matrix Controller Driver
Maximum icon Display (Using C0M33)
Microprocessor Direct Interface
Display Data bits Maximum 24-character 4-line Display
Character Generator 9,600 bits Characters Dots
Character Generator bits PatternsC Dots
High Voltage Driver 33-common 40-segment
Maximum Display Character Number
Disp. Line Ext. Display Char. Disp. Line Ext. Display Char.
Lines NJU6407C NJU6407C NJU6417C Characters Characters Characters Characters bits Lines NJU6417C Characters Characters bits
NJU6416 6415 Characters bits
Useful Instruction Clear Display, Return Home, Display ON/OFF Cont, Cursor ON/OFF Cent,
Display Blink, Cursor Shift, Character Shift
Extension Function
Power Initialize Hardware Reset Function
Voltage Converter Bleeder Resistance On-chip
Oscillation Circuit On-chip
Power Consumption
Operating Voltage
Package Outline Chip C-M0S Technology
package outline
nju6426f
5-340
faon Radio ltd.
configuration
o<vj 3333333333333300 uuidbjuuuuuu OOOOOOOOOOOOOOOOV31/3 LJCJ OOOOOOOOOOOOOOOO
<nomt">p>c*>m*
0333333 3333
QjtjjUJUJU-iCiJUJOOOOOO 00000000000003Q
vscscapiviiiOfcotooouiLjoo ooooooooooo
]RESET
block diagram
R/W-
Instruction Decoder <ID)
Address Counter
RESET
Reset
Vss"
Busy Flag
Character Generator
RAM)
Vo1ta&e
Character Generator
ROM)
9600b
Parallel Convertor
Display Data RAM) bits
Gen.
COM, -COM3;
SEG,
Shift Reg.
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5-341
terminal description
SYMBOL FUNCTION
Power Source
Power Source
30,31,32 V2.V3.V5 Driving Voltage Output Extension Driver Driving Voltage Adjust Terminals.
OSCi 0SC2 Oscillation Frequency Adjust Terminals. Normally Open. (Oscillation incorporated, Freq.=330kHz) external clock operation, clock should input osci.
Register selection signal input(Pul|-up resistance On-chip) Instruction Register (Writing) Busy Flag, Address Counter (Reading) Data Register (Writing/Reading)
Read/Write selection signal input(Pul|-up Resistance On-chip) Write Read
Read/Write activation signal input
45-48 3-state Data Bus(Upper) transfer data between NJU6426. also used Busy Flag reading.
41-44 3-state Data Bus(Lower) transfer data between NJU6426. These used 4-bit operation.
Latch Clock Output Serial Data
Shift Clock Output Serial Data
Alternating signal Driving Output Terminal
Serial Data Output Terminal serial character pattern data output correspond each common signals. No-active Active
68-61 9-16 60-53 17-24 9~C0Mi6 C0M25-C0M32 Common Driving Signal used, please keep open
Icon Common Driving Signal
69-100 ,~SEG32 Segment Driving Signal
Capacitor Voltage Doubler Connecting Terminal Capacitor Voltage Doubler Connecting Terminal
Input Terminal Voltage Doubler (Normally vdd)
V50UT Voltage Doubler Output Terminal
RESET Reset Terminal. When level input over 1.2ms this terminal, system will reset(fosc=330kHz)
5-342
Radio CoMd
functional description
Description each blocks Register
NJU6426 incorporates 8-bit registers, Instruction Register (IR) Data Register(DR). Register(IR) stores instruction codes such "Clear Display" "Return Home", address data Display Data RAM(DD RAM) Character Generator RAM(CG RAM).
write instruction code address data Register(IR), camot read from ister OR).
Register(DR) temporary stored register, data stored Register(DR) written into read from RAM.
data Register(DR) written transferred automatically internal operation.
When address data written into Register(IR), addressed data transferred Register(DR). read data Register(DR), data transmitting process performed completely.
After reading data Register(DR) MPU, next address data transferred automatically Register(DR) provide next reading.
These registers selected selection signal shown below.
Table shows register operation controlled signals.
Table Register Operation
Selected Register Operation
Write
Read busy flag(DB?) address counter(DBoMJBe)
Write (RegisteKDR) RAM)
Read Register(DR))
Busy Flag (BF)
When internal circuits operation mode, busy flag (BF) "1", instruction reading inhibited. busy flag (BF) output when RS="0" R/W="1" shown Table next instruction should written after busy flag(BF) goes "0".
(1-3) Address Counter (AC)
address counter(AC) addressing RAM.
When address setting instruction written into Register(IR), address information transferred from Register(IR) Counter(AC). selection either also determined this instruction.
After writing reading) display data from) RAM, Counter (AC) increments decrements) automatically.
address data Counter(AC) output from DB6~DB0 when RS="0" R/W="1" shown Table
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Display Data RAM)
display data RAM) consists bits stores 96-character display data represented 8-bit code. Normally, only bits display data RAM) using specially bits using 24-character 4~line display.
unused display data memory area used general data memory area. address data address counter(AC) represented hexadecimal.
order
Lower order bit-
Exaitple) address
Hexadecimal
Hexadecimal
-4-1 16-character Display N=0, E1=0, E0=0
relation between address display position shown below.
Line Line
NJU6426(COM9 ~C0M
16''
Display Position
Address (Hexadecimal)
NJU6426(C0M17~C0M24)
JU6426 (COM2
Note Iines display mode, line address defined (00)H (27)h (40)h (67)h. Please note that address beginning address consecutive.
When display shift performed, address changes follows:
Left Shift Display
(00) (40)
Right Shift Display
*(0F) K4F)
5-344
gapan Radio
U6426
-4-2) 24-character 2-Iine Display (N=0,El =0,E0=D.(Extension Driver NJU6407C) relation between address display position shown below: NJU6426(C0M NJU6407C NJU6426(COM9~COM16) NJU6407C
Line Line
55156 1^57]
Display Position
Address (Hexadecimal)
NJU6426(C0Mi7~C0M24) NJU6407C NJU6426(C0M?5~C0M32) NJU6407C When display shift performed, address changes follows: Left Shift Display
_L.J.L.
Right Shift Display
T-1-
16:17118:
56]57 j_58j
(17)
-4-3) 32-character 2-line Display (N=0,El=1,E0=0).(Extension Driver NJU6407C) relation between address display position shown below: JU6426(COM NJU6407C NJU6426(C0M9~C0Mi6) NJU6407C
Line Line
16'17
NJU6426(COMi7~COM24) NJU6407C NJU6426(C0M25~C0M32) NJU6407C When display shift performed, address changes follows: Left Shift Display
Display Position
Address (Hexadecimal)
-P-1
Right Shift Display
\5E]
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5-345
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-4-4) 40-character 2-line Display (N=0,E1=1,E0=1).(Extension Driver NJU6417) relation between address display position shorn below: NJU6426(COMi~COMa) NJU6407C NJU6426(C0M9~C0M,6) NJU6407C
Line Line
"'27-1
167!
Display Position
Address
(Hexadecimal)
NJU6426(C0Mi7~C0M24) NJU6407C NJU6426(C0M25~C0M32) NJU6407C When display shift performed, address changes follows: Left Shift Display
(40)
;oo:
Right Shift Display)
-4-5) 8-character 4-line Display (N=1,E0=O)
relation between address display position shown below: Display Position
COMi ~C0M8 Line
com9 -COMie Line
C0Mi7~C0M Line
C0M2 5-C0M Line
Address (Hexadecimal)
When display shift performed, address changes follows:
Left Shift Display
Right Shift Display
>(07) <47) >(67)
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Neugapan Radio Co.,lid.
(1-4-6) 16-character 4-line Display (N=1 ,E0=0).(Extension Driver NJU6407C)
relation between address display position shown below:
COMi ~C0M8 Line
COM9 Line
C0Mi7~C0M24 Line
C0M25-C0M32 Line
NJU6426
NJU6407C
Display Position
Address (Hexadecimal)
When display shift performed, address changes follows! Left Shift Display
Right Shift Display
>(2F) K4F) K6F)
-4-7) 20-character 4-line Display (N=1,E0=0).(Extension Driver NJU6417C)
relation between address display position shown below:
COMi -COMe Line
com9 ~C0Mi6 Line
C0Mi7~C0M24 Line
C0M25~C0M32 Line
NJU6426
NJU6407C
Display Position
Address (Hexadecimal)
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5-347
When display shift performed, address changes follows! Left Shift Display
Right Shift Display
(1-4-8) 24-character 4-|ine Display (N=1,EO=1).(Extension Driver NJU6416)
relation between address display position shown below:
COM, ~C0M8 Line
COM9 Line
C0Mi7~C0M24 Line
C0M?5~C0M32 Line
NJU6426
NJU6416
When display shift performed, address changes follows". Left Shift Display
Right Shift Display
Display
Position
Address
(Hexadecimal)
28:29
5-348
gapan Radio lid.
(1-5) Character Generator ROM)
Character Generator ROM) generates dots character pattern represented 8-bit character codes. storage capacity kinds dots character pattern. correspondence between character code standard character pattern NJU6426 shown Table 2-2. User-defined character patterns (Custom Font) also available mask option.
^apon Radio Co.,Ud.
5-349
JBma
Table 2-1. Character Pattern version
Upper bits Hexadecimal
(021
(03)
(04)
105) il.:.
(06)
107)
(08)
(02) ::::
(03)
(04)
(05)
(06)
(07) l'i-
(08)
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gapan Radio Co^JUcL
Table 2-2. Character Pattern version
Upper bits Hexadecimal
(Ol)
(02) iiiii e"S** aaSaa
(03) j.j.
(04) .j.j. a"*"*
(05) Blee aale" a**" aSaaS
(06) *ee*e :!.:
(07) lias
(08) .""S l.i.l
(Ol) :a.a! :::: jttt naie alala
(02) aaaea
(03) Ilia """"S allia
(04) *|**
(05)
(06) ::::: aaSaa
(07) .""a Saia" !!"! BeaSa
(08) s"': *iaa* Saale 1***5
fapan Radio Co.Iid
5-351
Character Generator
character generator store kind character pattern dots written user program display user's original character pattern icon data. store kind character dots mode kind character dots mode icon data.
display user's original character pattern stored RAM, address data (00)H -(073h (08)h (0F)h should written shown Table 2-2. Table show correspondence among character pattern, address Data. Unused memory area also used general data memory area.
Table Correspondence address, character code
character pattern( dots
Character Code Data) Address Character Pattern Data)
Upper Lower Upper Lower Upper Lower
0000*000 IUMO
0*001 Olii
Character Pattern Example(l)
Position
Character Pattern Example(2)
"-Cursor Position
Don't Care
Notes Character code correspond add. 5(3bits:8 patterns).
address designate character pattern line position. line cursor position display performed logical with cursor. Therefore, gase cursor display, line should
there ine, always displayed cursor position regardless cursor existence.
Character pattern position correspond data bits shown above. bits appear display meaning display), memory elements existing, therefore used general purpose RAM.
CG.RAM character patterns selected when character code bits addressed character code bits Therefore, address (00)h (08)h, (01)h (09)H,-. (07)h (0F)h select same character pattern shown Table 2-2. data correaonds display display Off. address (30)h (3F)h using both character pattern memory icon data memory.
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hkufapan Radio
Icon Display Function
NJU6426 display only bits character pattern also maximum icons. icon display writing each data address (30)h (3F)h RAM.
icon display data affected except writing display ON/OFF instruction. relation between address icon display position fixed even display shift executed. relation shown below:
HOLD
SEG/display 1112131415 Till
COMMK 3F*~3Fn 3E4~3Eo 3D4~3Do 3cl~3Co 304~30O
NoteD corresponds (3F)h RAM. terminal
icon splay
data
address 76543210 terminal
###00110 76-80
###11100 71-75
###00000 66-70
###00000 61-65
###00000
###00000 51-55
###00000 46-50
###00000 41-45
###00000 36-40
###00000 31-35
###00000 26-30
###00000 21-25
###00100 16-20
###00000 11-15
###00100 6-10
###00000
Icon Disp. Number Max. Chara Nimber Note
Chara.
Icons Chara. (07)h (0F)h Character Memory.
Icons Chara. (06)h,(07)h,(0E)h (0F)H Character Memory.
Note2) When icon display function using, system should initialized software initialization because does initialize except software initialization.
Icon Diso Number
Line Digit Extent Driver Max. Icon Diso.Nunber Line Digit Extent Driver Max. Icon Disp.Number
NJU6407C, NJU6407CR NJU6407C, NJU6407CR
NJU6407C, NJU6407CR NJU6417C
NJU6417C NJU6415, NJU6416
fapan Radio
5-353
CJRC3
Timing Generator
timing generator generates timing signals RAM, RAM, other internal circuits operation.
read timing display internal operation timing access separately generated, that they interfere with each other.
Therefore, when data write example, there will undesirable influence, such flickering, areas other than display area.
This circuit also generates control signals extension driver NJU640TC, 6417C 6416.
Driver
driver consist 33-common driver 40-segment driver.
When line nuifcer selected program, required common drivers output common driving waveform other common drivers output non-selection waveform automatically.
bits character pattern data shifted shift-register latched when bits shift performed completely. This latched data controls display driver output driving waveform.
(1-10) Cursor Blinking Control Circuit
This circuits controls cursor On/Off cursor position character blinks. cursor blinks appear digit residing address address counter (AC).
When address counter (08)h, cursor position shown follows:
(AC)
Display
Cursor position
Display
Display position address (Hexadecimal)
Display position
address (Hexadecimal)
Cursor position
(Note) cursor blinks also appear when address counter (AC) selects RAM. displayed cursor blink meaningless.
storing address data, cursor blink displayed meaningless position.
5-354
papati Radio Co.,
Power Initialization internal circuits
Initial ization Software
NJU6426 automatically initialized internal power initialization circuits when power turned internal power initialization, following instructions executed. During Internal power initialization, busy flag (BF) this status kept after rises 4.5V.
Initialization flow shown below:
Clear Display
Function
Display On/Off Control
Entry Mode
DL=1 :8-bit long
interface data :2-Line Display E1=0, EQ=1 24-character Display
display Cursor Cursor
NOTE
condition power supply rise time described Electrical Characteristics satisfied, internal Power Initialization Circuits will operated initialization will performed.
this case initialization software required.
I/D=1: Increment Shift
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5-355
Initialization Hardware
NJU6426 incorporates RESET terminal initialize system. When level input over 1.2ms RESET terminal, reset sequence executed. this time, busy signal output during 10ms after RESET terminal goes "H".
Reset Circuit
Timing Chart
External Reset Signal
Counter Output
RS-F/F Output Internal Reset Signal
Over 1.2ms
Busy
10ms
Instructions
NJU6426 incorporates registers, Instruction Register (IR) Data Register (DR). These registers store control information tenporarily allow interface between NJU6426 peripheral operating different cycles. operation NJU6426 determined this control signal from MPU. control information includes register selection signals (RS), read/write signals CR/W) data signals (DB0 DB?). Table shows each instruction operating time.
Note execution time mentioned Table based fosc=330kHz.
oscillation frequency changed, execution time also changed. Note When reset function executed, 40-character 2-line selected.
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Neugapan Radio Co.Md
Table Table Instructions
INSTRUCTIONS CODE DESCRIPTION EXEC TIME
Maker Testing 0000000 code using maker testing. 30us
Clear Display 0000000001 Display clear sets address 1.24ms
Return Home 000000001 Sets address returns display being shifted original position. contents remain unchanged 1.24ms
Entry Mode 0000000 11/DS Sets cursor move direction specifies shift display performed data read/write. 1/D=1:1ncrement, I/D=01 rement S=11Accompanies display shift 30us
Display On/Off Control 0000001 Sets display On/Off(D), cursor 0n/0ff(C) blink cursor position 30us
Cursor Display Shift Moves cursor shifts display without changing contents S/C=1 Display shift S/C=0 Cursor shift R/L=1 Shift right R/L=0 Shift left 45us
Function Sets interface data length(DL), number display lines(N) display character number. Character font fixed DL=1 bits DL=0 bits 4-line 2-line Please refer 30us
Address Sets address. After this instruction, data transferred to/from RAM. 30us
Address Sets address. After this instruction, data transferred to/from RAM. 30us
Read Busy Flag Address Reads busy flag contents. BF=1 Internal operating BF=0 accept instruction
Write Data Write Writes data into RAMs. 30us
Read Data from Read Data Reads data from RAMs. 45us
Explanation Abbreviation Display data Character generator address address, Corresponds cursor address Address counter used both RAMs
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Description each instructions
Maker Testing
Code
code 4-bit length using Therefore, please avoid input (Especially please attention output on.)
device testing mode only maker meaning Enable signal input data "0". condition Enable signal when power turns
Clear Display
Code
Clear display instruction executed when code written into DBo. When this instruction executed, space code (20)h written into every address, address into address counter entry mode increment.
cursor blink displayed, they returned left (the left line display mode).
entry mode does change. Note: character pattern character code (20)H must blank code user-defined character pattern(Custom font).
Return Home
Return home instruction executed when instruction executed, address returned original position shifted, (the left line display.
contents change.
code written into DBi. When this into address counter. Display cursor blink returned left 2-line display mode) cursor blink
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Entry Mode
Code
Entry mode instruction which sets cursor moving direction display shift On/Off, executed when code written into codes (l/D) written into DBiO/D) DBo(S), shown below.
(I/D) sets address increment decrement, sets entire display shift writing.
Function
Address increment: address increment when read/write, cursor blink move right.
Address decrement: address decrement when read/write, cursor blink move left.
Function
Entire display shift. shift direction determined l/D.: shift left l/D=1 shift right l/D=0. shift operated only character, that looks cursor stands still display moves. display does shift when reading from writing/reading into/from RAM.
display does shifting.
Newgapcut, Radio Coglici
5-359
"jrc
Display On/Off Control
Code
Display On/Off control instruction which controls whole display On/Off. cursor cursor position character blink, executed when code written into codes (D), written into 0B2(D), DBi(C) DBo(B), shown below.
Function
Display
Display Off. this mode, display data remains that retrieved immediately display when change
Cursor cursor displayed dots line.
Cursor Off. Even display data write, does change.
cursor position character blinking. Blinking rate 518.4ms fosc=330kHz 24-character 433.2ms fo=300kHz others. cursor blink displayed simultaneously.
character does blink.
Note) blink time alters proportionately 1/fosc 1/fcP. example, when fCP=300kHz 518.4 (330/300) 570.2ms. (For 24-Character 4-Line) 433.2 (330/300) 476.5ms. (For others)
Sffil
Cursor
Character Font dots Alternating display
Cursor display example Blink display example
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fapa* Radio Co.M
Cursor/Display Shift
Code
Cursor/Display shift instruction shifts cursor position display right left without writing reading display data. This function used correct search display. 2-line display, cursor moves line when passes 40th digit line. Notice that line displays will shift same time. When displayed data shifted repeatedly, each line moves only horizontally.
line display does shift into line position.
contents address counter(AC) does change operation display shift only.
This instruction executed when code written into DB-i codes (S/C) (R/l) written into DB3(S/C) DB?(R/l), shown below.
Shifts cursor position left [(AC) decremented
Shifts cursor position right ((AC) incremented
Shifts entire display left cursor lows
Shifts entire display right cursor follows
Function
Code
Don't care
Function instruction which sets interface data length number display lines, executed when code written into codes (DL), (N), (Ei) (Eo) written into DBtCDL), DB3(N), DBi(Ei) DBo(Eo), shown below (character font fixed dots).
(DL) sets interface data length sets number display lines either 2-line 4-line (Ei), (Eo) select display character nunber.
NOTE
This function instruction must performed head program prior other existing instruct ions(except Busy flag/Address read). This function instruction executed afterwards unless interface data length change.
Function
interface data length bits (DB? DBo)
interface data length bits (DB7 data must sent received twice this mode.
Display lines Display Digit Extension Driver
2-1i Character Character Character Character NJU6407C, NJU6407CR NJU6407CR
4-1i Character Character NJU6417C NJU6416, NJU6415
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Address
Lower
order order
address instruction executed when code written into DBr> address written into shown above.
address data mentioned binary code AAAAAA written into address counter (AC) together with addressing condition. After this instruction execution, data writing/reading performed into/from RAM.
Address
Code
order
Lower order bit-
address instruction executed when code written into address written into shown above.
address data mentioned binary code AAAAAAA written into address counter (AC) together with addressing condition. After this instruction execution, data writing/reading performed into/from RAM.
Note case ay(N=0), address data (00)h (27)h line (40)h (67)h line. 20-character 4-line display(N=1, EOO, TAAAAAAAJ line, (20)H line, (40)h (53)H line (60)H to(73)H line. However, case 24-character 4-line(N=1, E0=1), TAAAAAAAJ (00)h line, (20)H (37)h line, (40)H (57)H line line.
Display Line Line Line Line
2-Line (00)
20-Char. 4-Line (00) (13)
24-Char. 4-Line
Read Busy Flag Address
-Higher order Lower order
This instruction reads internal status NJU6426. When this instruction executed, busy flag (BF) which indicate internal operation read from address read from (the address determined previous instruction).
(BF)="1" indicates that internal operation progress. next instruction inhibited when (BF)=T\ Check (BF) status before next write operation.
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Write Data
order Lower order
Write Data instruction executed when code written into (RS) code written into (R/W).
execution this instruction, binary data DDDDDDDD written into RAM. selection determined previous instruction. After this instruction execution, address increment(+1) decrement (-1) performed automatically according entry mode set. display shift also executed according previous entry mode set.
Read Data from
order Lower order bit->
Read Data from instruction executed when code written into (RS) (R/W).
execution this instruction, binary data DDDDDDDD read from RAM. selection determined previous instruction.
Before executing this instruction, either address address must executed, otherwise first read data invalidated.
When this instruction serially executed, next address data normally read from second read.
address instruction required cursor shift instruction executed just beforehand (only reading).
cursor shift instruction same function address set, that after reading RAM, address increment decrement executed automatical according entry mode.
display shift does occur regardless entry mode.
Note: address counter(AC) automatically incremented decremented after write instruction either RAM. Even read instruction executed after this instruction, addressed data read correctly. correct data read out, either address instruction cursor shift instruction (only with RAM) must implemented just before this instruction from second time read instruction execution read instruction executed times consecutively.
NeuQapcui Radio Coglici
5-363
u6426
Initialization using internal reset circuits
16-character display 8-bit operation (Using internal reset circuits).
16-character display, Function set, Display On/Off Control Entry Instruction must executed before data input, shown below.
NJU6426 store characters, explained before, therefore advertising moving display available when combined with display shift operation. Since display shift operation changes only display position contents remain unchanged, display data which entered first output when return home operation performed.
Initialized. display appears.
8-bit operation, 16-character dots Font.
Turns display cursor. Entire display space mode
initialization.
Example address increment cursor right shift when data write RAM.
Power
Function
Disp.On/Off Cont
Entry Mode
Write data DD/CG Instruction
16-character 2-line 4-bit operation (Using internal reset circuits).
4-bit operation, function must performed user programming.
When power turned 8~bit operation selected automatically, therefore first input performed under 8-bit operation. this operation, full instruction input because terminals connection. Therefore, same instruction must rewritten shown below. Since operation completed accesses 4-bit operation mode, rewrite required instruction code
16-character 2-line 4-bit operation shown follows:
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Newgapan Radio Co.IicL
Power
Function
Disp.On/Off Cont
Entry Mode
Function
Initialized. display appears.
4-bit operation.
This step executed 8-bit mode
initialization.
4-bit oper display, dots Font. 4-bit operation starts from step.
this
Turn display cursor.
Entire display space mode
initialization.
Exanple address increment cursor right shift when data write RAM.
Write data DD/CG Instruction
20-character 4-line 8-bit operation (Using internal reset circuits). From line displays will shift same time.
Power
Function
Disp.On/Off Cont
Entry Mode
Initialized. display appears.
8-bit operation, 20-characte 4-1i s-play, dots Font.
Turns display cursor. Entire display space mode initialization.
Example address increment cursor right shift when data
Write data DD/CG Instruction
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Initialization instruction
power supply conditions correct operation internal reset circuits met, NJU6426 must initialized instruction.
Initial ization Instruction 8-bit interface length.
Power
Wait more than 15ms after rises 4.5V
Function
Wait more than 4.1ms
Function
Wait more than lOOus
Function
Function
Display
Display Clear
Entry Mode
Write data DD/CG Instruction
Initialized. display appears.
Function
(8-bit interface length
Function
(8-bit interface length
Function
(8-bit interface length
Busy Flag(BF) checked before this step, checked after this step. After this step, busy flag(BF) check longer waiting time than each instruction execution time required.
8~bit operation, 24-character 4-1ine display, dots Font.
Example address increment cursor right shift when data write RAM.
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fata* Radio Co.,IicL
\}RC
Initialization Instruction 4-bit interface length
Power
Wait more than 15ms after rises 4.5V
Function
Wait more than 4.1ms
Function
Wait more than 100us
Function
Function
Function
Display
Display Clear
Entry Mode
Write data DD/CG Instruction
Initialized. display appears.
Function
(8-bit interface length
Function
(8-bit interface length
Function
(8-bit interface length
Busy Flag (BF) checked before this step, checked after this step.
After this step, busy flag (BF) check longer waiting time than each instruction execution time requi red.
Function
4-bit interface length 8-bit interface length.
4-bit operation, 40-character 2-1ine display dots Font.
Exanple address increment cursor right shift when data write RAM.
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5-367
DISPLAY
Power Sipply Driving
NJU6426 incorporate voltage doubler generate driving high voltage bleeder resistance. voltage doubler generate about twofold voltage from input voltage 9.5V lout=2mA Vci=5V bleeder resistance generate each driving voltage.
bleeder resistance bias suitable 1/36 duty ratio each resistance value
Driving Voltage Duty Ratio
Power supply Duty Ratio 1/36
Bias
50ut Vlcd
NJU6426
v50ut
Vlcd
VDD(
Vdd(
NJII6426
v50ut
Vlcd
Bias(1/36 Duty)
(Voltage Doubler unused example)
Bias(1/36 Duty)
(Voltage Doubler used example)
5-368-
fapan Radio Co.,IicL
Ejr<3
(4-2) Relation between oscillation frequency frame frequency.
NJU6426 incorporate oscillation capacitor resistance osci11at ion, 330kHz oscillation available without external components. frame frequency example mentioned below based 330kHz oscillation. clock 3.0us
1/36 duty
^-100 clock
Frame
20-character 4-line Display
frame 3.0(us) 10.80ns) Frame frequency 1/10.8(ms) 92.6(Hz)
24-character 4-line Display
frame 3.0(us) 13(ms) Frame frequency 1/13.0(ms) 76.9(Hz)
faon Radio
5-369
Interface with
NJU6426 interfaced with both 4/8-bit two-time 4_bit one-time 8-bit data transfer available.
(5-1 4-bit interface
When interface length 4-bit, data transfer performed lines connected (DBo used). data transfer with completed two-time 4-bit data transfer.
data transfer executed sequence upper 4-bit (the data 8-bit length) lower 4-bit (the data 8-bit length).
busy flag check must executed after two-time 4bit data transfer instruction execution). this case data busy flag address counter also output twice.
Interniii
tion
Inst ruct Writing
Busy Check
Busy Check
Instruct Writing
x*c*
DB.,
Writing instruction into instruction Register(IR)
Readout Busy Flag(BF)
Adress counter(AC)
Readout data Register(DR)
(5-2) 8-bit interface
Internal Status
Writing Inst ruct into Instruction er(IR)
Busy Check
Busy
Busy Check
Flag Writing Instruction into Check lustriction Register(IR)
5-370
Radio Co.,
ABSOLUTE MAXIMUM RATINGS Ta=25'C
PARAMETER SYMBOL RATINGS UNIT
Supply Voltage
Input Voltage Vdd+0.3
Operating Tenperature Topr
Storage Temperature Tstg
Note used condition above absolute naximun ratings, destroyed. Using within electrical characteristics strongly recomended normal operation. beyond electric characteristics conditions will cause malfunction poor IiabiIity. Note voltage values specified Note relation VDD^Vci>V^V5ouT Vss=0V must maintained.
Turn same time turn first then turn must required. turn sequence does meet above conditions, latch will occur. Note Decoupling capacitor(Cn) should connected between stabilized operation voltage doubler.
ELECTRICAL CHARACTERISTICS Ta=-20
PARAMETER SYMBOL CONDITIONS unit note
Operating Voltage
Input Voltage
Output Voltage -Ioh=0.205mA
1ol=1.6mA
Driver On-resist.(COM) Rcom com. term.)
Driver On-resist.(SEG) Rseg seg.term.)
Input Leakage Current V,n=0
Pull-up Resist Current Vdd=5V,RS,R/W,DB Terminals
Operating Current Vdd=5V, fosc=330kHz
Voltage Doubler Output Voltage Vsout Terminal 1ouT-5mA -3.0 -4.0
ouT=1mA -4.6 -4.8
Input Volt.
Conv. Effici 95.0 99.9
Built-in Bleeder resistance (For Driving Voltage) 1.00
1.00
2.00
1.00
1.00
Osci11 Frequency Vdd=5V,
Driving Voltage Vlcd V50UT Terminal, Vdd=5V Vdd- Vdd- 13.5
Note Input/Output structure except driver shown below!
Input Terminal Structure
Terminal
ERPHOS
RS.R/W Terminals
Irput/Output Terminal Structure
HE"! Nnos
nfi0s
Terminals
Neugapan Radio Co.Iid
5-371
jjrc
Note Apply Output Input/Output Terminal.
Note Except pull-up resistance current output driver current.
Note Except Input/output current including current flow bleeder resistance.
input level mediun, current consumption will increase penetration
current. Therefore, input level must fixed "l".
Operating Current Measurement Circuit
Note Rcom Rsig resistance values between power sipply terminals (Vdd, Vsout) each common terminal(COMi COM33), supply voltage (Vdd, Vsout) each segment terminal(SEGi SEG->o) respectively, measured when current flown every ccrmon segment terminals same time.
NotelO) Apply output voltage from each less than against driving constant voltage (Vdd, load condition.
Voltage Doibler Measurement Circuit
Internal Bleeder Resistance
Voltage Dotbler Internal Clock Frequency 5kHz
5-372
gapan Radio
timing characteristics (Vdd +75C) Write operation Write fron NJU6426
PARAMETER SYMBOL CONDITION UNIT
Enable Cycle Time tCYCE
Enable Pulse Width "High" level PwEH
Enable Rise Time, Fall Time tEr,
Time R/W,
Address Hold Time
Data Time tDSW
Data Hold Time
Timing Characteristics (Write operation)
Vili
Vili
Vili
PffiEH
tDSW,
Valid Data
Vili
tCYCE
Vili
fig.
Read operation Read from NJU6426
PARAMETER SYMBOL CONDITION UNIT
Enable Cycle Time tCYCE
Enable Pulse Width "High" level PwEH
Enable Rise Time, Fall Time tEr,
Time R/W, fig.2
Address Hold Time
Data Delay Time
Data Hold Time
papati Radio Coglici
5-373
Timing Characteristics (Read operation)
^DB,
Vili
i.as
VILI;
PWbh
-iDDR
VlLl-
VOH1
Valid Data
Voli
Voli
tCYCE
Vili
fig.
Segment Extension Signal Timing Characteristics
PARAMETER SYMBOL CONDITION UNIT
Clock Pulse Width "High" level tcWH
Clock Pulse Width "Low" level tcWL
Clock Time tcsu
Data Time fig.3
Data Hold Time
Delay Time -1000 1000
Clock Rise Time, Fall Time
Segment Extension Signal Timing
v,,,,
V-A_t\_
fig.
5-374
Radio Co.IM.
load circuit
Segment signal load circuit
RL=2.4kQ
Test Point
130pF
Teal Point
60pF
Input Condition when using Hardware Reset Circuit Input Timing
tfiSL
RESET
PARAMETER SYMBOL CONDITION UNIT
Reset Input Level Width tRSL fosc=330kHz
Power Suply Condition when using internal initial ization circuitCTa
PARAMETER SYMBOL CONDITION UNIT
Power Supply Rise Time
Power Supply Time toFF
Since internal initialization circuits will operate normally unless above conditions met, such case initialize instruction. (Refer initialization instruction)
toFF specifies power time short period cyclical on/off.
papati Radio
5-375
DRIVING WAVEFORM
1/36 Duty Driving
COM, COM,, COM,, COM,
-vr-
5-376
Nwgapan Radio CoMd
APPLICATION CIRCUITS 16-character 2-line Display Example (1/6 Bias, 1/36 Duty)
papati Radio Co., lid.
5-377
40-characier Display Example (1/6 Bias, 1/36 Duty)
C0M9
COMI
COM8 COM17
COM24
IJU6426
COM25
COM33
SF.G1
SEG40
SEG1 -SEG60
NJU64I7C IOAI
Panel (40-Character
2-Line)
Icon Display
5-378
NeugapanRodio Co.,IM.
\JRCj
NJU6426
8-character Display Exanple (1/6 Bias, 1/36 Dirty)
Panel (8-Character 4-Line)
Icon Display
gapan Radio Co.,IicL
5-379
24-character 4-line Display Exanple (1/6 Bias, 1/36 Duty)
comi
com8 com9
com16 com17
com25
com33
Panel (24-Character 4-Line)
Icon Display
secl
-SEG80
ioa,
5-380
papati Radio Co,IicL
Bright
Contro
iorq
8255
c0m9
c0m8 c0m17
com24 NJII6426
seg1
seg40 com33 com32
com25
fWIHTNil
trade mark Inc.
interface exanple driving voltage generated NJU6426
Bright Control
-VdO
5VA7 10RQ
o255
C0M16
Viin
comi
C0M8 C0M17
com24 seg1
seg40 com33 com32
com25
-rfF
fciiiHIIki
Z8CKB) trade mark Inc. interface example driving voltage sLpplied from external power sLpply
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