4082 COUNTER/DIVIDERS: 4017 DECADE COUNTER WITH DECODED OUTPUTS 4

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4082 COUNTER/DIVIDERS: 4017 DECADE COUNTER WITH DECODED OUTPUTS 4

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4082
COUNTER/DIVIDERS: 4017 DECADE COUNTER WITH DECODED OUTPUTS 408S OCTAL COUNTER
WITH DECODED OUTPUTS
4017 MMC. 4022 5-stage stage Johnson counters having decoded outputs respectively.
4017 4022 monolithic integrated circuits, fabricated standard Al-gate CMOS technology. available 16-lead dual inline- plastic package.
Inputs include CLOCK, RESET CLOCK inhibit signal. Schmitt trigger CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise fall times. These counters advanced count positive clock signal transition CLOCK INHIBIT signal low, Counter advancement clock line inhibited when CLOCK INHIBIT signal high. high RESET signal clears counter zero count. Johnson decade-counter configuration permits highspeed operation. 2-input 'decimal-decode gating spike-free decoded outputs. Anti-lock gating provided, thus assuring proper counting sequence.
decoded outputs normally high only thPir respective decoded time slot. Each decoded Output remains high full clok cycle CARRY-OCT signal completes cycle every clock input Oycjes 4017 every dock input cycles 4022 used ripplp-clock ceding device mult!-device counting chain.
features
Fully static operation
Medium spfeed operation (typ)
applications
Decade counter/decimal decode display
Binary counter/decoder
Frequency division
Counter control/timers
Divide counting.
absolute maximum ratings
VQD* Supply voltage: types -0.5
types -0.5
Input voltage -0.5 VOD+0.5
input current (any input)
Total power dissipation [per package)
Dissipation output transistor
full package-temperature range
Operating
temperature types
types
Storage temperature
voltage values referred voltage
recommended operating conditions
VDD* Supply voltage: types
types
Input voltage
Operating
temperature types
tvoes
connection diagrams
40ss
DVDO 3vqo
RESET iRESFT
3CLOCK 3clock
CLOCK INHIBIT 3CL0CK INHIBIT
Dcarry 3CARRY
vssE vsst
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4d8b
logic diagram
567B
TLSr IT,TT
reset
CLOCK
4022
CARRf
RtSET
CLOCK
CL*CK INHIBIT
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mmc4q17 mmc4088
jrimlno diagram mmc401
CLOCK
RESET
CLOCK JNH0T
JWWWIAAAA/WIT
a_r\
CARRY-OUTPUT
4q22
CLOCK
RESET
CLOCK INHIBIT
iVWUWWWlAAA/WVWl
y^_TL
_r\_r\
_r\_
F\_F\
OUTPUT
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MWICaOI-7 MMCq0a,
static electrical characteristics
lover recommended operating conditions)
CONDITIONS VALUES
PARAMETER "flow ^high
(mA) min. max. max. min. max.
Quiescent current types 0/10 0/15 0/20 0.04 0.04 0.08 3000
types 0/10 0/15 0.04 0.04 0.04
Output high voltage 0/10 0/15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95
Output voltage 10/0 15/0 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0,05
Input high voltage 0.5/4.5 1.5/13.5
Input voltage 4.5/0.5 13.5/1.5
Output drive current types 0/10 0/15 13,5 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -3.2 -2.6 -6.8 -1.15 -0.36 -0.9 -2.4
types 0/10 0/15 13.5 "1.53 -0.52 -1.3 -3.6 -1.36 -0.44 -1.1 -3.0 -3.2 -2.6 -6.8 -1.1 -0.36 -0.9 -2.4
Output sink current types 0/10 0/15 0.64 0.51 0.36
types 0/10 0/15 0.52 0,44 0.36
'ih- Input leakage types 0/18
Current types 0/15 input
input capacitance input
Tlow devices; devices
Thigh 125fJC devices; devices. Noise Margin both level
min. with
min. with with
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40s8
dynamic electrical characteristics
kohm. typical temperature coefficient values, input rise fall times
PARAMETER TEST CONDITIONS VDDtV) VALUES UNIT
typ. max.
operation
tpLH-tpHL Propagation delay time Oecode
Carry
lTHL' lTLH Transition time Carry Decoded Line
Maximum clock input frequency
Minimum clock pulse width
Clock input rise fail time Unlimited
Data setup time Minimum clock inhibit
Heaet operation
tpth. Propagation delay time
tphl Carry Decoded
Lines
Minimum reset pulse width
Minimum reset removal time
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4qq;
typical applications
Divide counter with decoded outputs
When decoded output reached (Nth clock pulse) flip-flop (constructed from gates 4001) generates reset pulse which clears 4017 zero count; this time, decoded output greater than equal Cout line goes high clock next 4017 counter section. decoded output also goes high this time. Coincidence clock decoded output high resets flip-flop enable 4017. decoded output less than Cqut line will high and, therefore, cannot used. this case decoded output used perform clocking function next counter.
4017 4022
clock
reset

4082 COUNTER/DIVIDERS: 4017 DECADE COUNTER WITH DECODED OUTPUTS 4

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