MAX+PLUS i-WV MAX+PLUS Unified Development system entir

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MAX+PLUS i-WV MAX+PLUS Unified Development system entir

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PLS-MAX
MAX+PLUS
i-WV
MAX+PLUS
Unified Development system entire Multiple Array Matrix (MAX) family EPLDs.
Multiple design entry methods including hierarchical Graphic Editor, Boolean Equations, State Machine.
Hierarchical Graphic Editor multiple level schematics
Series special MacroFunctions
optimized architecture. defined MacroFunctions. path Predictor.
Logic Synthesis minimization ensures quick efficient design processing.
Automatic Error Location.
Interactive Timing Simulation.
Graphical Waveform Editor entering editing input waveforms viewing simulation results.
Runs PS/2, PC-AT compatible machines.
GENERAL DESCRIPTION
Altera PLS-MAX Programmable Logic Development System unified system implementing designs into Altera's (Multiple Array MatriX) family EPLDs based MAX+PLUS software. PLS-MAX includes design entry, design processing, timing simulation. Hosted PS/2, PC-AT compatible machine, PLS-MAX gives designer tools quickly efficiently create complex logic designs.
MAX+PLUS software compiles designs EPLDs matter minutes. Designs entered using variety design entry mechanisms. MAX+PLUS supports hierarchical Graphic entry, Boolean Equation, State Machine, Truth Table entry methods. Graphic Editor features include drag editing, multiple windows, multiple zoom levels, menu driven command structure. Graphic Editor also advanced features such multiple hierarchy levels, symbol editing, library 7400 series devices addition basic gates. Boolean Equation, State Machine Truth Table entry methods
Figure MAX+PLUS Block Diagram
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DESIGN PROCESSOR
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used seperately conjunction with Graphic Editor, giving added flexibility design environment.
addition multiple design entry mechanisms, MAX+PLUS includes sophisticated Compiler place designs within EPLDs. Compiler uses advanced logic synthesis minimization techniques conjunction with knowledge based fitting rules efficiently place designs within family EPLDs. programming file created compiler then used software program EPLDs using standard Altera programming hardware.
Simulations performed using powerful event driven timing simulator within MAX+PLUS. This simulator interactively displays timing results graphical Waveform Editor display, well hard copy tabular waveform output. graphical Waveform Editor allows entry modifications input vector waveforms, logical operations pairs waveforms. comparison between simulations performed Waveform Editor, difference between simulations highlighted.
integrated structure MAX+PLUS system features Automatic Error Location Delay Prediction. design contains error, MAX+PLUS only flags error, takes user actual location error original schematic. Propagation delays critical
paths determined Graphic Editor using Delay Predictor. simply tagging first last nodes with cursor, shortest longest timing delay calculated.
MAX+PLUS consistent graphical interface throughout, easing parts software. There always on-line help user.
DESIGN ENTRY
MAX+PLUS supports variety design entry methods. Boolean Equation entry available entering simple combinatorial logic register functions. State Machine Entry used enter designs high level language syntax, well Truth Table inputs. Since EPLDs offer designer large amount logic capability, Altera created hierarchical Graphic Editor ease design process.
MAX+PLUS will also accept various party netlists, well existing EPLD designs implemented with Altera's A+PLUS system, Intel's iPLDS iPLDS systems.
GRAPHIC EDITOR
hierarchical Graphic Editor supports top-down bottom-up design methodology. top-down method, designer starts with high level block diagram, which defines Inputs
Figure Hierarchical Graphic Editor
hierarchical Graphic Editor provides multi-windowed, menu driven environment.
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outputs each block. Then logic each block entered individually. bottom method allows simulation verification small building blocks, which then pieced together into final design.
Graphic Editor itself mouse driven, multiple windowed environment utilizing menus entering commands. Optionally, commands entered using single keystrokes. Graphic Editor shown Figure Hierarchy Window shown top, lists schematics used make design. Navigation between hierarchy levels accomplished simply placing mouse cursor name schematic edited pressing mouse button. Moving within schematic accomplished auto-panning through design, Total View Window. Total View Window shows entire design, clicking mouse area Total View Window, user automatically moved that area schematic. Error Report Window lists warnings errors compiled design, selecting error with cursor, offending node symbol highlighted.
Actual editing design done workspace area, powerful features design cycle. Auxiliary windows Editor removed enlarge workspace area. choose from library over 7400-series
special MacroF:unctions, them optimized architecture. Gate level primitives, such NAND, AND, EXCLUSIVE-OR gates flip-flops also provided. Since MAX+PLUS hierachical environment, designers create custom functions that used schematic.
user takes advantage hierarchy creating saving design. symbol function created automatically, modified with symbol editor.
drag editing used move individual symbols, areas defined moved. Lines stay connected with true orthogonal rubber-banding. This means that symbols areas moved connection wires retain clean 90-degree angles they move maintain connectivity schematic. Hardcopy output completed design produced Epson compatible printer, plotter.
SYMBOL EDITOR
symbol needs modified, custom symbol created represent schematic, this accomplished using Symbol Editor. Symbol Editor shown Figure this environment user defines input output stubs symbol their position. function symbol defined using Graphic
Figure MAX+PLUS Symbol Editor Screen
MAX+PLUS Symbol Editor allows creation editing custom symbols hierarchical Graphic Editor.
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Entry, State Machine, Boolean descriptions. This provides wide range flexibility designer, allowing Boolean Equations mixed with State Machine entry hierarchical schematic. created function entered into higher level schematic, schematic subsequent designs.
SYMBOL LIBRARIES
library provided with MAX+PLUS system contains over MacroFunctions increase design productivity. This library includes most commonly used 7400 series devices such counters, decoders, encoders, shift registers, flip-flops, latches, multipliers. Altera created special MacroFunctions take advantage architecture. MacroFunctions have been optimized maximize speed utilization. Table shows presently available MacroFunctions.
Since Graphic Editor hierarchical, schematic created automatically represented symbol. Thus user create library user-defined MacroFunctions addition those supplied Altera.
DELAY PREDICTOR
additional feature Graphic Editor Delay Predictor. This tool provides instant feedback concerning timing processed design. placing mouse cursor starting point then point, user determine minimum maximum propagation delays speed critical paths. result calculation displayed bottom Graphic Editor. This valuable tool design debugging documentation.
BOOLEAN ENTRY
Boolean Equations entered into MAX+PLUS using simple design language. source design created with convenient text editor. language supports free-form entry syntactical elements. Boolean equations need entered sum-of-products form, intermediate equations supported. This feature permits significant reduction size Boolean Equation source code allows designer define logic most natural conceptual manner.
STATE MACHINE
Designs that easily represented with state diagrams entered State Machine approach. This method uses high-level language description featuring IF-THEN constructs define state transitions. Mealy Moore state machines supported state machine entry. Outputs state machine defined conditionally unconditionally, allowing flexible output structures that merged with other portions
Table MacroFunction Library
ADDERS: 7480, 7482, 7483, 75183
ALU: 74181
COMPARATORS: 7485, 74518, 8MCOMP
CODE CONVERTERS: 74184, 74185
COUNTERS: 7493, 74160, 74161, 74162, 74163, 74190, 74191, 74192, 74193, 74393, 4COUNT, 8COUNT, UNICNT, 16CUDSLR, GRAY4
DECODERS: 7442, 7443, 7444, 7445, 7446, 7447, 7448, 7449, 74138, 74139, 74154, 74155, 74156
FLIP FLOPS: 7470, 7471, 7472, 7473, 7474, 7476, 7478, 74173, 74174, 74175, 74273, 74374
FREQUENCY DIVIDER: FREQDIV
LATCHES: 7475, 7477, 74116, 74259, 74279, 74373, NANDLTCH, NORLTCH, INPLTCH
MULTIPLIERS: 74261, MULT2, MULT4, MULT24
MULTIPLEXERS: 74147, 74148, 74151, 74153, 74157, 74158, 74298
PARITY GENERATORS: 74180, 74280
SHIFT REGISTERS: 7491, 7494, 7499, 74164, 74165, 74166, 74178, 74179, 74194, 74198, 16CUDSLR, UNICNT, BARRLST
GATES: 7400, 7402, 7404, 7408, 7410, 7411, 7420, 7421, 7427, 7430, 7432, 7486, INHB, CBUF
STORAGE REGISTERS: 7498, 74278
TRUE/COMP ELEMENT: 7487
design. Boolean equations allowed offering definition high level intermediate logic expressions, truth tables used define output equations.
state machine file then converted into format that MAX+PLUS software process directly, automatically generated symbol state machine, including inputs outputs, loaded into Graphic Editor integrated with other logic.
DESIGN PROCESSING
Compiler, which processes designs, shown Figure There variety options within compiler. degree detail report file generated user-defined
maximum number errors warnings before process termination set. designer toggle whether extract netlist file simulation.
Also, design been processed previously, only portion design been changed, incremental compile chosen, only changed parts design re-extracted, decreasing compilation time.
first module extracts netlist from each file used define design. this time design rules checked errors. errors found, user option directly edit design using hierarchical Graphic Editor. Error Processor then invokes Graphic Editor, error window used highlight exact place where error took place. example this shown Figure successfully extracted design then built into database Database Builder Module.
Logic Synthesizer then works database. Logic synthesis translates optimizes user-defined logic architecture. design first minimized using SALSA (Speedy Altera Logic Simplification Algorithm). unused logic design automatically removed. logic synthesizer uses several knowledge-based synthesis rules factor logic within
multi-level architecture. will then choose approach that ensures most efficient silicon resources.
next module, Fitter, uses heuristic rules optimally place synthesized design within chosen EPLD. EPM5128, EPM5127, EPM5064 used, Fitter also routes signals across Programmable Interconnect Array, freeing designer from having worry about interconnection issues. report issued fitter, showing exactly design implemented into specified part, well unused resources EPLD. result, designer this determine much additional logic placed EPLD.
simulator netlist extracted from compiled design simulation desired. Simulation Netlist Extractor creates file Timing Simulator.
Finally, Assembler takes compiled design creates Programming Object File. This file used with Altera hardware program desired part.
Because advanced synthesis minimization techniques employed Compiler, designs placed within architecture matter minutes. example, counter/ shift register compiles under minutes.
Figure MAX+PLUS Error Processing
Error processing within MAX+PLUS automatically locates highlights errors hierarchical Graphic Editor.
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DESIGN SIMULATION
Verification analysis completed design accomplished with powerful timing simulator within MAX+PLUS. Simulator interactive, event-driven simulator that yields true timing functional characteristics compiled design.
Input stimulus defined using straightforward vector input language, waveforms directly drawn using Graphical Waveform Editor. Outputs also viewed Waveform Editor, hardcopy tabular waveform files printed out.
SIMULATOR
Simulator uses Simulation Netlist file extracted from compiled design perform timing simulation with 1/10 nanosecond resolution. command file used batch operation, commands entered interactively. Simulator commands allow user perform such things breaking simulation dependant user-defined conditions, forcing grouping nodes, A.C. timing detection.
simulator will warn user flip-flop set-up hold times have been violated. Minimum pulse
width period oscillation user-defined time periods. pulse shorter than minimum pulse width specified, simulator will flag user. Likewise, period oscillation defined, node oscillates longer than specified time, simulator warns this condition.
GRAPHICAL WAVEFORM EDITOR
Waveform Editor mouse driven menu environment which timing waveforms viewed edited. functions logic analyzer, giving ability observe results simulation. Simulated waveforms viewed manipulated multiple zoom levels. Nodes added, deleted, combined into busses. These busses contain signals, which represented binary, octal, hexadecimal format. Logical operators also performed pairs waveforms, that waveforms inverted, OR'd, AND'd, even XOR'ed together.
Waveform Editor includes sophisticated editing features that input vectors defined modified. input waveforms created using mouse familiar text editing commands. Waveforms copied, patterns repeated, blocks moved
Figure MAX+PLUS Compiler Screen
MAX+PLUS Compiler uses minimization, Logic Synthesis heuristic fitting algorithms place designs into EPLDs.
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copied. example, part waveform contracted simulate increase clock frequency.
Graphical Waveform Editor also compare highlight difference between different simulations. This simulation run, results observed edited, then re-run, with Waveform Editor showing differences between simulations.
Device programming integrated into MAX+PLUS development environment. PLDS-MAX combines PLS-MAX development software with basic programming hardware/software EPLDs. Adapters included programming EPM5032 EPM5128 devices. Additional adapters purchased separately support other devices. MAX+PLUS programming software drives PC-AT PS/2 card programming unit (PLE3-12A). user program verify EPLDs. also read contents device this information program additional devices.
SYSTEM REQUIREMENTS
MINIMUM SYSTEM CONFIGURATION
PS/2 model higher, PC-AT compatible computers. PC-DOS version higher. 640K bytes RAM, recommended byte Expanded Memory
EGA, VGA, Hercules Monochrome display.
byte hard disk drive.
1.2M byte 5V*" 1.44M byte 314" floppy disk
drive.
button serial port mouse. Full card slot programming. RECOMMENDED SYSTEM CONFIGURATION
PS/2 model higher, Compaq 20MHz computer. PC-DOS version 3.3. 640K bytes RAM.
byte Expanded Memory with compatible driver. graphics display. byte hard disk.
1.2M byte 1.44M byte 31/2" floppy disk drive.
button serial port mouse. Full Card slot programming. Notes:
Some larger designs compile simulate without Expanded Memory.
Figure Graphical Waveform Editor
Waveform Editor allows entry modifications input stimulus, viewing, comparing simulator waveforms.
PLAESW-PC
month renewable warranty PC-based Altera software. This contract covers software contained within PLS-MAX well other Altera software owned registered user. PLAESW-PC includes automatic upgrade each revision Altera software guarantees software support family EPLDs introduced Altera. also includes toll-free hotline hour modem interface Altera Electronic Bulletin Service.

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